KR100355608B1 - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR100355608B1 KR100355608B1 KR1019990067387A KR19990067387A KR100355608B1 KR 100355608 B1 KR100355608 B1 KR 100355608B1 KR 1019990067387 A KR1019990067387 A KR 1019990067387A KR 19990067387 A KR19990067387 A KR 19990067387A KR 100355608 B1 KR100355608 B1 KR 100355608B1
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- 238000000034 method Methods 0.000 title claims abstract description 78
- 238000002955 isolation Methods 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000010408 film Substances 0.000 claims abstract description 82
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 3
- 239000012298 atmosphere Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 238000009279 wet oxidation reaction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 4
- 238000007517 polishing process Methods 0.000 abstract description 3
- 238000005498 polishing Methods 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000001556 precipitation Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체장치의 셀로우 트렌치(shallow trench)형 소자분리막 형성방법에 관한 것으로서, 이 방법은 반도체기판에 순차적으로 패드산화막 및 질화막을 적층한 후에 소자분리마스크용 감광막을 이용한 식각 공정을 진행하여 질화막부터 기판의 소정 깊이까지 트렌치를 형성하고, 감광막을 제거한 후에 트렌치가 형성된 기판에 이후 실시될 고온의 어닐링 공정시 기판의 원소(element)가 외부로 석출되는 것을 방지하기 위하여 저온에서 산화공정을 실시하여 산화박막을 형성하고, 산화박막이 형성된 기판에 식각 데미지 제거 및 정션 특성을 높이기 위하여 고온에서 어닐링 공정을 실시하고, 기판의 트렌치 내부에 갭필 산화막으로 채워넣는 다음, 화학적기계적연마 공정으로 질화막이 드러날때까지 갭필 산화막을 연마한 후에 질화막을 제거하여 기판내에 소자분리막을 형성한다. 이에 따라, 본 발명은 고온의 열처리 공정이전에 저온의 산화공정으로 트렌치 내부에 불순물의 아웃-디퓨전을 막을 수 있는 방어용 산화막이 형성되기 때문에 STI 구조의 소자분리 공정의 수율 및 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a shallow trench type device isolation film in a semiconductor device. The method sequentially deposits a pad oxide film and a nitride film on a semiconductor substrate and then performs an etching process using a photoresist film for device isolation mask. After forming a trench from a nitride film to a predetermined depth of the substrate, and removing the photosensitive film, an oxidation process is performed at a low temperature to prevent precipitation of elements of the substrate to the outside during the subsequent high temperature annealing process on the trench formed substrate. To form an oxide thin film, annealing at high temperature in order to remove etch damage and improve junction characteristics on the substrate on which the oxide thin film is formed, and to fill the inside of the trench with a gap-fill oxide film, and then to expose the nitride film by a chemical mechanical polishing process. After polishing the gapfill oxide film until the nitride film was removed, An element isolation film is formed in the film. Accordingly, the present invention can improve the yield and reliability of the device isolation process of the STI structure because a protective oxide film is formed in the trench to prevent out-diffusion of impurities by the low temperature oxidation process before the high temperature heat treatment process. .
Description
본 발명은 반도체장치의 소자분리막 형성방법에 관한 것으로서, 특히 고집적 반도체장치에서 소자분리 영역과 활성 영역을 정의하기 위한 STI(Shallow Trench Isolation) 공정시 기판의 트렌치 식각 손상을 보상할 수 있는 반도체장치의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device. In particular, a semiconductor device capable of compensating for trench etch damage of a substrate during a shallow trench isolation (STI) process for defining device isolation regions and active regions in a highly integrated semiconductor device. The present invention relates to a device isolation film forming method.
최근 반도체장치의 제조기술의 발달과 메모리소자의 응용분야가 확장되어 감에 따라 대용량의 메모리소자의 개발이 진척되고 있는데, 이러한 메모리소자의 대용량화는 각 세대마다 2배로 진행하는 미세공정기술을 기본으로 한 메모리셀 연구에 의해 추진되어 오고 있다. 특히 소자간을 분리하는 소자분리막의 축소는 메모리소자의 미세화 기술에 있어서 중요한 항목중의 하나로 대두되고 있다.Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, the development of large-capacity memory devices has been progressed. It has been promoted by a memory cell study. In particular, the reduction of the device isolation film that separates the devices has emerged as one of the important items in the technology of miniaturization of memory devices.
종래의 소자분리기술로는 반도체기판상에 두꺼운 산화막을 선택적으로 성장시켜 소자분리막을 형성하는 로커스(LOCal Oxidation of Silicon: 이하 LOCOS라 함) 기술이 최근까지 주종을 이루었다. 그러나, 상기 LOCOS 기술은 소자분리막의 측면확산 및 버즈비크(bird's beak)에 의해 소자분리영역의 폭을 감소시킬 수 없었다. 따라서, 소자설계치수가 서브미크론(submicron) 이하로 줄어드는 대용량의 메모리소자에 있어서는 상기 LOCOS 기술의 적용이 불가능하기 때문에 새로운 소자분리 기술이 필요하게 되었다.Conventional device isolation technology has mainly been a LOCal Oxidation of Silicon (LOCOS) technology to selectively grow a thick oxide film on the semiconductor substrate to form a device isolation film. However, the LOCOS technique cannot reduce the width of the device isolation region due to side diffusion and bird's beak of the device isolation layer. Accordingly, the LOCOS technology cannot be applied to a large-capacity memory device whose device design dimension is reduced to submicron or less, and thus a new device isolation technology is required.
이에 따라, 새로운 소자분리기술의 필요성과 식각(etching) 기술의 발달로 반도체기판에 폭이 수천 Å이하, 깊이가 수십 내지 수천 Å 정도의 트렌치를 형성하여 소자간을 전기적으로 분리할 수 있는 트렌치(trench) 구조의 소자분리 기술이나오게 되었다. 이 트렌치를 이용한 소자분리기술은 종래의 LOCOS 기술에 비해 80%에 가까운 소자분리영역의 축소가 가능해졌다.Accordingly, the necessity of a new device isolation technology and the development of etching techniques have formed trenches that can electrically separate the devices by forming trenches of several thousand Å or less in width and tens to thousands of 깊이 in depth. device isolation technology with trench structure. The device isolation technology using this trench can reduce the device isolation region by nearly 80% compared to the conventional LOCOS technology.
최근에는, 웨이퍼기판에 가해지는 스트레스의 크기가 적다는 장점을 갖는 STI 공정이 많이 이용되고 있다. 이는 반도체기판에 일정한 깊이를 갖는 트렌치를 형성하고 이 트렌치에 화학기상증착법으로 산화막을 증착하고서 화학적기계적연마(Chemical Mechanical Polishing) 공정으로 이 산화막의 표면을 부분 식각하여 소자분리막을 형성하는 기술이다.In recent years, many STI processes have been used which have an advantage that the amount of stress applied to the wafer substrate is small. This is a technique of forming a device isolation film by forming a trench having a constant depth in a semiconductor substrate, depositing an oxide film on the trench by chemical vapor deposition, and partially etching the surface of the oxide film by a chemical mechanical polishing process.
그러나, 이 STI 공정또한 기판에 트렌치를 형성한 후에 표면에 존재하는 식각 손상을 제거하지 않을 경우에는 접합 누설 전류 특성을 양호하게 할 수 없다는 한계점이 있었다.However, this STI process also has a limitation in that the junction leakage current characteristics cannot be improved unless the etching damage present on the surface is removed after the trench is formed in the substrate.
따라서, 트렌치 식각 후에 고온 열처리 및 희생산화막 처리 공정으로 식각 손상을 제거하며 부가적으로 식각된 트렌치 프로파일을 완만하게 형성시켜 모서리 부분에 집중될 수 있는 스트레스의 집중을 방지한다.Therefore, after the trench etching, the high temperature heat treatment and the sacrificial oxide treatment process remove the etching damage and additionally form the etched trench profile smoothly to prevent concentration of stress that may be concentrated on the edge portion.
도 1은 종래기술에 의한 STI형 소자분리막의 제조공정시 발생하는 식각 공정의 문제점을 설명하기 위한 단면도로서, 이를 참조하여 종래의 STI 소자분리공정을 설명하면 다음과 같다.1 is a cross-sectional view illustrating a problem of an etching process occurring during a manufacturing process of an STI type device isolation film according to the prior art. Referring to this, a conventional STI device isolation process is described below.
우선, 반도체기판인 실리콘기판(10)위에 패드산화막(12)을 형성한 다음 그 위에 질화막(14)을 적층한다. 소자분리 마스크를 이용한 사진 및 식각 공정을 진행해서 적층된 질화막(14)부터 기판(10)을 식각하여 기판(10)내에 트렌치(16)를 형성한다.First, a pad oxide film 12 is formed on a silicon substrate 10 that is a semiconductor substrate, and then a nitride film 14 is laminated thereon. The photolithography and the etching process using the device isolation mask are performed to etch the substrate 10 from the stacked nitride films 14 to form trenches 16 in the substrate 10.
그리고, 도면에 도시하지는 않았지만 트렌치 식각 손상을 보상하기 위하여 트렌치(16)가 형성된 기판(10)상에 고온에서 희생산화막(도시하지 않음)을 50∼200Å정도 형성하고, 매립 특성이 양호한 산화막으로 트랜치 내부를 완전히 채우고 화학적기계적연마공정으로 상기 산화막을 평탄화한다. 그리고나서, 남아 있는 질화막(14) 및 패드산화막(12)을 제거하여 기판(10)에 활성영역과 소자분리영역을 정의하는 STI형 소자분리막을 형성한다.Although not shown in the drawings, a sacrificial oxide film (not shown) is formed on the substrate 10 having the trench 16 formed thereon at a high temperature to compensate for the trench etch damage, and the trench is formed of an oxide film having good buried characteristics. The inside is completely filled and the oxide film is planarized by a chemical mechanical polishing process. Then, the remaining nitride film 14 and pad oxide film 12 are removed to form an STI type device isolation film that defines an active region and a device isolation region on the substrate 10.
상기와 같은 STI 소자분리 공정은 희생 산화막 제조공정시 산화막의 균질도 및 언더 임퓨리터(under impurity)의 아웃-디퓨전을 억제하기 위해 온도 안정화, 승온 단계에서 적은량의 산소를 포함한 N2분위기에서 진행하게 된다.The STI device separation process as described above is carried out in an N 2 atmosphere containing a small amount of oxygen in the temperature stabilization and temperature rising step to suppress the homogeneity of the oxide film and the out-diffusion of the under impurity during the sacrificial oxide film manufacturing process. do.
그러나, 1000℃이상의 고온 열처리 공정시 보트가 튜브로 인입되기 시작하는 순간부터 실제 어닐링 처리 온도까지 적은 O2를 포함한 N2분위기에서 공정을 진행할 경우 균일하지 않은 자연 산화막이 생성되는 단점이 있어 100Å이하의 얇고 균일한 희생 산화막을 형성하기 어려운 단점이 있었다. 희생산화막의 두께를 증가시킬 경우 패드 산화막으로 침투되는 산소량이 증가하고 질화막 하부에 언더 컷팅(A) 현상이 발생하게 되어 후속 산화 공정시 갭필 산화막이 트렌치 에지에서 내부를 완전히 채울수 없게 된다.However, during the high temperature heat treatment process of 1000 ℃ or higher, if the process is carried out in the N 2 atmosphere including the small O 2 from the moment when the boat starts to enter the tube to the actual annealing temperature, a non-uniform natural oxide film is generated. It was difficult to form a thin and uniform sacrificial oxide film. Increasing the thickness of the sacrificial oxide layer increases the amount of oxygen that penetrates into the pad oxide layer and causes undercut (A) under the nitride layer, so that the gapfill oxide layer cannot fully fill the inside of the trench edge during the subsequent oxidation process.
이를 위해서 STI 공정시 고온의 열처리 공정에서 보트가 튜브로 인입 및 승온되는 단계까지 일정시간동안 적은량의 O2를 플로우시키지 않고 N2가스만을 투입하고 있다. 그러나, 이와 같이 N2가스만을 플로우하는 상태에서 고온의 열처리 공정을 실시하면 "산소(O)" 및 "보론(B)" 등의 불순물의 아웃-디퓨전(out-diffusion)을 막을 수 있는 산화막의 두께가 확보되지 않을 뿐더라 웨이퍼 기판에서 불순물 석출이 심해져 기판에 구멍이 형성되는 등 소자 분리공정의 수율을 열화시키는 문제점이 있었다.For this purpose, and the boat without the O 2 flow in a small amount for a predetermined time to the incoming phase and the tube temperature was raised to input only the N 2 gas in the heat treatment process at the time of a high temperature STI process. However, if the high temperature heat treatment process is performed in the state of flowing only N 2 gas, an oxide film capable of preventing out-diffusion of impurities such as “oxygen (O)” and “boron (B)” may be prevented. In addition, the thickness was not secured, but the impurity deposition in the wafer substrate increased, resulting in deterioration of the yield of the device isolation process, such as forming holes in the substrate.
본 발명의 목적은 상기 종래기술의 문제점을 해결하기 위하여 트렌치 식각후에 저온에서 산화공정을 실시한 후에 고온 어닐링 공정을 실시함으로써 고온의 열처리 공정시 불순물의 아웃-디퓨전을 막을 수 있는 방어용 산화막을 형성하여 STI 구조의 소자분리 공정의 수율 및 신뢰성을 향상시킬 수 있는 반도체장치의 소자분리막 형성방법을 제공하는데 있다.An object of the present invention to solve the problems of the prior art by performing an oxidation process at a low temperature after the trench etching and then performing a high temperature annealing process to form a protective oxide film that can prevent the out-diffusion of impurities during the high temperature heat treatment process STI Disclosed is a method of forming a device isolation film of a semiconductor device capable of improving the yield and reliability of a device isolation process having a structure.
도 1은 종래기술에 의한 STI형 소자분리막의 제조공정시 발생하는 식각 공정의 문제점을 설명하기 위한 단면도,1 is a cross-sectional view for explaining the problem of the etching process occurs during the manufacturing process of the STI device isolation film according to the prior art;
도 2a 내지 도 2e는 본 발명에 따른 STI형 소자분리막 형성 방법을 설명하기 위한 공정 순서도.2A to 2E are flowcharts illustrating a method of forming an STI type isolation layer in accordance with the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
100 : 실리콘기판 102 : 패드산화막100: silicon substrate 102: pad oxide film
104 : 질화막 106 : 비반사막104: nitride film 106: anti-reflective film
108 : 감광막 패턴 110 : 트렌치108: photosensitive film pattern 110: trench
112 : 산화박막 114 : 갭필 산화막112: oxide thin film 114: gap fill oxide film
ISO : 소자분리막ISO: Device Separator
상기 목적을 달성하기 위해 본 발명은 반도체기판에 소자의 활성 영역 및 분리 영역을 정의하기 위한 트렌치 구조의 소자분리막을 형성함에 있어서, 반도체기판에 순차적으로 패드산화막 및 질화막을 적층하는 단계와, 소자분리마스크용 감광막을 이용한 식각 공정을 진행하여 질화막부터 기판의 소정 깊이까지 트렌치를 형성하는 단계와, 감광막을 제거한 후에 트렌치가 형성된 기판에 저온에서 산화공정을 실시하여 산화박막을 형성하는 단계와, 산화박막이 형성된 기판에 고온에서 어닐링 공정을 실시하는 단계와, 산화박막이 형성된 기판의 트렌치 내부에 갭필 산화막으로 채워넣는 단계와, 상기 결과물을 평탄화하고 질화막을 제거하여 기판내에 소자분리막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of forming a device isolation film having a trench structure for defining an active region and an isolation region of a device on a semiconductor substrate, sequentially depositing a pad oxide film and a nitride film on the semiconductor substrate, and separating the device. Forming a trench from a nitride film to a predetermined depth of the substrate by performing an etching process using a mask photosensitive film; and forming an oxide thin film by performing an oxidation process at a low temperature on the trench formed substrate after removing the photosensitive film; Performing an annealing process at a high temperature on the formed substrate, filling a gap fill oxide film into the trench of the substrate on which the oxide thin film is formed, and planarizing the resultant and removing the nitride film to form a device isolation film in the substrate. Characterized in that made.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 STI형 소자분리막 형성 방법을 설명하기 위한 공정 순서도로서, 이를 참조하면 본 발명의 STI형 소자분리막 형성 공정은 다음과 같다.2A to 2E are flowcharts illustrating a method of forming an STI device isolation film according to the present invention. Referring to this, the STI device isolation film forming process of the present invention is as follows.
우선, 도 2a에 도시된 바와 같이 반도체기판인 실리콘기판(100)에 순차적으로 30∼100Å정도의 얇은 패드산화막(102) 및 500∼2000Å두께의 질화막(104)을 적층한다. 그 위에 소자분리마스크용 감광막(108)을 도포한 후에 도 2b에 도시된 바와 같이, 식각 공정을 실시하여 질화막(104)부터 기판(100)을 식각하여 기판(100) 내에 트렌치(110)를 형성한다. 이때, 트렌치(110) 식각 깊이는 적용 디바이스의 디자인 룰에 따라 차이가 있으나 약 1500∼7000Å정도로 한다.First, as shown in FIG. 2A, a thin pad oxide film 102 having a thickness of about 30 to 100 microseconds and a nitride film 104 having a thickness of 500 to 2000 microseconds are sequentially stacked on a silicon substrate 100 which is a semiconductor substrate. After the photosensitive film 108 for device isolation mask is applied thereon, as shown in FIG. 2B, an etching process is performed to etch the substrate 100 from the nitride film 104 to form the trench 110 in the substrate 100. do. At this time, the etching depth of the trench 110 is different depending on the design rules of the applied device, but it is about 1500 to 7000 Å.
또한, 상기 공정에서 트렌치 식각 공정시 정확한 패터닝을 위해서 상기 질화막(104) 상부에 추가적으로 비반사막을 200∼500Å정도 형성할 수도 있다.In addition, an anti-reflective film may be additionally formed on the nitride film 104 in an amount of about 200 to 500 kPa for accurate patterning during the trench etching process.
그 다음 감광막을 제거하고, 도 2c에 도시된 바와 같이 고온의 열처리 공정을 실시하기 전에 트렌치(110)가 형성된 기판(100)에 이후 실시될 고온의 어닐링 공정시 기판의 원소가 외부로 석출되는 것을 방지하기 위하여 저온에서 산화공정을 실시하여 산화박막(112)을 50∼200Å정도로 형성한다. 이때, 저온의 산화 공정은750∼900℃에서 실시되며 건식 또는 습식 산화 공정을 이용하는 것이 바람직하다. 산화 공정 전에 온도 승온, 온도 안정화 스텝에서의 낮은 O2비율은 비휘발성 가스 분위기상에서 10%이하 O2몰분율을 유지한다. 또한, 실제 산화 분위기는 O2, O2+H2, 희석 건식 산화(O29%이상의 몰분율 비활성 가스 분위기), 희석 습식 산화(O29%이상의 몰분율, H29∼36% 몰분율 비활성 가스 분위기)중에서 어느 하나를 선택한다.Then, the photoresist film is removed, and as shown in FIG. 2C, before the high temperature heat treatment process is performed, an element of the substrate is deposited to the outside during the high temperature annealing process to be performed later on the substrate 100 having the trench 110 formed thereon. In order to prevent the oxidation process at low temperature, the oxide thin film 112 is formed to about 50 to 200 kPa. At this time, the low temperature oxidation process is carried out at 750 ~ 900 ℃ and it is preferable to use a dry or wet oxidation process. The low O 2 ratio in the temperature rise and temperature stabilization steps prior to the oxidation process maintains a mole fraction of O 2 below 10% in a non-volatile gas atmosphere. In addition, the actual oxidizing atmosphere is O 2 , O 2 + H 2 , diluted dry oxidation (mole fraction inert gas atmosphere of more than 9% O 2 ), diluted wet oxidation (mole fraction of more than 9% O 2 , H 2 9-36% mole fraction inert gas) Atmosphere).
이어서, 산화박막(112)이 형성된 기판에 식각 데미지 제거 및 정션 특성을 높이기 위하여 1000∼1200℃이상의 고온에서 어닐링 공정을 실시한다. 이때, 어닐링 공정은 15∼150분동안 실시하며 N2가스만을 이용한 건식 산화공정 내지 희석된 산화분위기(비휘발성 가스 분위기에서 10% 이하 O2몰분율 유지)에서 실시한다.Subsequently, an annealing process is performed at a high temperature of 1000 ° C. to 1200 ° C. or higher in order to remove etch damage and improve junction characteristics on the substrate on which the oxide thin film 112 is formed. At this time, the annealing process is carried out for 15 to 150 minutes in a dry oxidation process using only N 2 gas to diluted oxidation atmosphere (maintaining a mole fraction of O 2 or less in 10% or less in a nonvolatile gas atmosphere).
도 2d에 도시된 바와 같이, 고온의 열처리 공정이 실시된 기판의 트렌치 내부에 화학기상증착공정으로 갭필 산화막(114)을 채워넣은 후에 평탄화 공정(예컨대, 화학적기계적연마)을 실시하여 질화막(104)의 일정부분이 제거될때까지 증착된 산화막(114) 및 질화막(104)을 연마한다. 그리고, 인산용액을 이용하여 나머지 질화막(104)을 제거한 후에 세정공정을 실시하여 패드산화막(102)도 제거한다.As shown in FIG. 2D, the gap fill oxide film 114 is filled into the trench of the substrate subjected to the high temperature heat treatment process by chemical vapor deposition, followed by a planarization process (for example, chemical mechanical polishing) to form the nitride film 104. The deposited oxide film 114 and nitride film 104 are polished until a portion of the film is removed. After the remaining nitride film 104 is removed using a phosphoric acid solution, a cleaning process is performed to remove the pad oxide film 102.
이에 따라, 도 2e에 도시된 바와 같이, 기판(100)내에는 소자의 분리영역과 활성영역을 구분하는 본 발명의 STI형 소자분리막(ISO)이 형성된다.Accordingly, as shown in FIG. 2E, an STI type device isolation layer (ISO) of the present invention is formed in the substrate 100 to distinguish the isolation region and the active region of the device.
그러므로, 본 발명은 트렌치 식각후 저온(750∼900℃)의 산화 공정에 의해 웨이퍼 기판의 내부에 존재하는 산소(또는 보론)의 아웃-디퓨전을 억제하기 위한방어용 산화막이 형성되기 때문에 이후 고온(1000∼1200℃)의 열처리 공정을 실시할 경우 안전하게 트렌치의 식각 데미지 제거, 표면 피트성 결함의 발생을 억제한다.Therefore, since the oxide film for preventing the out-diffusion of oxygen (or boron) existing inside the wafer substrate is formed by the oxidation process of low temperature (750-900 ° C.) after the trench etching, the present invention has a high temperature (1000 ° C). When the heat treatment step of ˜1200 ° C. is performed, the etching damage of the trench is safely removed and the occurrence of surface fit defects is suppressed.
상기한 바와 같이 본 발명에 따른 반도체장치의 소자분리막 형성방법은, 트렌치 식각 후 실시되는 고온의 열처리 공정이전에 저온의 산화 공정을 실시하여 기판에 함유된 산소 및 보론이 웨이퍼 표면으로 석출되는 것을 방지하기 위한 산화막을 형성함으로써 STI 공정의 제조수율을 향상시킬 수 있다.As described above, in the method of forming an isolation layer of a semiconductor device according to the present invention, a low temperature oxidation process is performed before a high temperature heat treatment process performed after trench etching to prevent the oxygen and boron contained in the substrate from being deposited on the wafer surface. By forming the oxide film for this purpose, the production yield of the STI process can be improved.
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| JPH0786393A (en) * | 1993-09-17 | 1995-03-31 | Toshiba Corp | Device isolating method of semiconductor device |
| JPH10214889A (en) * | 1997-01-21 | 1998-08-11 | Siemens Ag | Method of forming thin film of crystalline silicon nitride film in shallow trench isolation structure, shallow trench isolation structure for submicron integrated circuit device, and crystalline silicon nitride film |
| KR19990065087A (en) * | 1998-01-07 | 1999-08-05 | 윤종용 | How to form trench isolation |
| US6110793A (en) * | 1998-06-24 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
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| JPH0786393A (en) * | 1993-09-17 | 1995-03-31 | Toshiba Corp | Device isolating method of semiconductor device |
| JPH10214889A (en) * | 1997-01-21 | 1998-08-11 | Siemens Ag | Method of forming thin film of crystalline silicon nitride film in shallow trench isolation structure, shallow trench isolation structure for submicron integrated circuit device, and crystalline silicon nitride film |
| KR19990065087A (en) * | 1998-01-07 | 1999-08-05 | 윤종용 | How to form trench isolation |
| US6110793A (en) * | 1998-06-24 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
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