KR100352371B1 - Line buffer for enlarging an moving image in display and its method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing apparatus, and more particularly, to provide a line buffer for an image enlarged display and a control method thereof for displaying an image of an image compression / restore codec processor.

According to the present invention, a DMA interface for receiving and outputting data carried on the DMA data bus; An input buffer for temporarily storing data input from the DMA interface and outputting data stored according to a write control signal; A line memory for writing data input from the input buffer to a write address according to a write control signal, and reading and outputting data stored at a read address according to a read control signal; A multiplexer for alternately applying a read address and a write address to the line memory according to a control signal; A read address generator for outputting a read address to the line memory in accordance with a control signal; A write address generator for outputting a write address to the line memory in accordance with a control signal; And a line buffer controller for generating a write control signal to the input buffer, generating an address generation control signal to the read address generator and the write address generator, and generating a write read control signal to the line memory. A buffer device is provided.

Description

Line buffer for enlarging an image and controlling it {Line buffer for enlarging an moving image in display and its method}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing apparatus and a control method thereof, and more particularly, to a line buffer for an image enlarged display and a control method thereof for displaying an image of an image compression / restore codec processor.

In the prior art, a method of calculating video scaling is obtained by multiplying a coefficient with respect to an average value of an input pixel by a luminance and a color component.

In the prior art, the coefficients are obtained in the vertical and horizontal directions with respect to the input video stream.

Thus, when the size of the image increases or decreases, first, a pixel scaled with respect to the vertical direction is obtained, and then applied with respect to the next horizontal direction. In addition, when resizing, the first step is to create a pixel that is doubled with respect to the input pixel, and then reduce it to the desired size.

However, the prior art has a problem that the device occupies a large size in the configuration because the external memory to store the entire frame in the frame buffer has a problem, and when the read operation is completed for one frame, the read frame is completed Due to the deletion, there is a problem that the memory usage that is not suitable for the characteristics of the image is not implemented.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and does not use a general FIFO or dual port memory used to configure a general line buffer, and uses a general memory having a single port. Once saved, the line data can be reused, and in order to improve the efficiency of the line memory, the data is stored in the form of a circular FIFO, and the diary pointer can be returned as necessary to the starting point of the line so that the stored line can be reused. It is an object of the present invention to provide a line buffer and a method of controlling the same for an image enlarged display that enables data to be used multiple times.

1 is a block diagram of a video compression / restoration system to which the present invention is applied.

2 is an explanatory diagram of a configuration of a codec memory of FIG. 1 and a DMA transfer packet;

3 is a block diagram of a line buffer for an image enlarged display according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a memory content and an address relationship of the line buffer of FIG. 3; FIG.

5 is a control flowchart of the write address generator of FIG.

6 is a control flowchart of the read address generator of FIG.

♠ Explanation of symbols on the main parts of the drawing ♠

510: DMA interface 520: input buffer

530: line memory 540: inflation filter

550: multiplex 560: line buffer controller

570: timing and controller 580: write address generator

590 read address generator

According to the present invention for achieving the above object, a DMA interface for receiving and outputting data carried on the DMA data bus; An input buffer for temporarily storing data input from the DMA interface and outputting data stored according to a write control signal; A line memory for writing data input from the input buffer to a write address according to a write control signal, and reading and outputting data stored at a read address according to a read control signal; A multiplexer for alternately applying a read address and a write address to the line memory according to a control signal; A read address generator for outputting a read address to the line memory in accordance with a control signal; A write address generator for outputting a write address to the line memory in accordance with a control signal; And a line buffer controller for generating a write control signal to the input buffer, generating an address generation control signal to the read address generator and the write address generator, and generating a write read control signal to the line memory. A buffer device is provided.

In addition, according to the present invention, a first step of determining whether the line memory is empty after initializing the write pointer (WP), write base pointer (WBP), component mode (COMP); A second step of making a DMA transfer request if the line memory is empty as a result of the determination in the first step; If the component of the transmitted data is Cb WP = WBP; WP = WBP + 4; WP = WBP + 8; A third step of repeating the step of determining whether the line memory of the first step is empty after generating the write addresses in the order of WP = WBP + 12; If the component is Cr WP = WBP + 2; WP = WBP + 6; WP = WBP + 10; A fourth step of repeating the step of determining whether the line memory of the first step is empty after generating an address of WP = WBP + 14; If component is Y0 WP = WBP + 1; WP = WBP + 3; WP = WBP + 5; A fifth step of repeating the step of determining whether the line memory of the first step is empty after generating an address of WP = WBP + 7; If the component is Y1 WP = WBP + 9; WP = WBP + 11; WP = WBP + 13; A sixth step of repeating the step of determining whether the line memory of the first step is empty after generating an address of WP = WBP + 15; A seventh step of determining whether the increased value exceeds the maximum address of the line memory by increasing the write base point (WBP) by 16 after designating Cb as a component; And an eighth step of repeating from the step of determining whether the line head of the first step is empty if it is determined that WBP = 0 if exceeded. A control method is provided.

According to the present invention, there is also provided a method comprising: a first step of initializing a read address pointer RF, a read base pointer RBP, and a vertical line state variable VNUM; Waiting for the active state of the horizontal line, and in the active state, checking the line data read request in the interpolation filter; A third step of waiting for valid data in a line memory when there is a read request as a result of the check in the second step; Synchronizes the read address with the control signal so that RP = RBP; RF = RBP + 1; RP = RBP + 2; RP = RBP + 3; A fourth step of incrementing the read base pointer RBP after generating an address of '4' and repeating the process of waiting for the active line state of the second step; A fifth step of checking whether the vertical line state variable VNUM is '0' when the active state of the horizontal line is released in the active line state; As a result of the inspection in the fifth step, if the value is '0', the read base pointer is increased by '4', the read base pointer RBP is applied to the next line start variable LSP, and the vertical line enlarged variable VNUM is initialized. A sixth step of waiting for the horizontal line to become active; If the vertical zoom variable is not '0' in the active line state, decrease the vertical zoom variable by '1', initialize the read base pointer (RBP) to the line start pointer (LSP), and wait for the horizontal line to become active. Provided is a method of controlling a line buffer comprising seven steps.

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of a line buffer and a control method for an image enlarged display according to the present invention will be described in detail.

In order to implement an image compression / restore codec, a method of displaying a reconstructed image or an overlaid image on a general video output device is required.

Image compression / restore standards, such as H.261 / H.263, compress and restore images of a smaller size as compared to display devices, so they are too small to be displayed directly on standard NTSC video output devices. It is common to display through an enlargement process.

The present invention is the same size as the image stored in the image buffer in order to display the image image of the QCIF (176 * 144) or Sub QCIF (128 * 96) stored in the image image buffer of the image compression / restore codec on a general video output device, or The present invention relates to an apparatus for making an image at a magnification of 2 times and 4 times.

In particular, the video codec has a structure that reads pixel data directly from the codec frame buffer so that the component is reduced by not having a separate display frame buffer.

In implementing the image codec, the following considerations are needed to display a real-time image without a separate display frame memory.

First, the NTSC video output device has an idle image area of 720 * 480, one frame consists of two fields, and 30 images are displayed per second.

Since the present invention does not store the entire frame to be displayed, data must be continuously read from the codec memory in accordance with the display refresh cycle.

At this time, if data is read again from the codec memory when the image line is copied to enlarge the size of the image to be displayed, the DMA performance of the codec is greatly degraded, so a method of reusing the read data is needed.

In addition, there is a need for a structure that does not sufficiently lose data even if there is a delay due to sequential services in the codec DMA by increasing the efficiency of the line buffer.

In the present invention, the line buffer is configured using a general memory having a single port without using a general FIFO or a dual port memory used to configure a general line buffer, and the line data stored once can be reused.

At this time, to improve the efficiency of the line memory, data is stored in the form of a circular FIFO, and the read pointer can be returned to the starting point of the line as needed so that the stored line data can be used many times.

1 is a block diagram of a video compression / restoration system to which the present invention is applied. Looking at the video compression process, the video signal applied by the camera 100 is digitalized through the NTSC decoder 150. The CCIR 601 (720x480) sized image is converted into a QCIF (176x144) or SQCIF (128x96) image through a video input interface.

The reduced image is stored in the codec memory 400 through the DMA controller 300.

The image data thus stored may be converted into a code form compressed by the image compression / restore processor 700 and transmitted through communication means under the control of the host processor 800 through the host bus, or may be stored in the memory 810 of the system. Can be.

On the contrary, in the process of restoring the image, when the compression code to be restored in the communication means or the memory 810 is sent from the host processor 800 to the image decompression processor 700 through the host bus, the image compression processor 700 may compress the compressed code. The coded data is stored in the codec memory 400 through the DMA controller 300 through interpretation of the code.

Image data stored in the codec memory 400 is again applied to the video output interface 500 through the DMA controller 300.

At this time, the video output interface 500 enlarges the image of the QCIF or SQCIF size 2 times or 4 times and applies the enlarged image data to the NTSC encoder 600 so that the restored image can be viewed through the display 650 means. do.

Image data stored in the codec memory 400 is divided into brightness components (Y) and color components (Cb, Cr) and stored.

2 is a diagram illustrating the configuration of the codec memory of FIG. 1 and the DMA transfer packets.

FIG. 2 shows separately stored brightness components 410 and color components 420 and 430. The data format when transmitted to the video output interface 500 through the DMA controller 300 is in the form of a data packet 310. 320, 330, 340).

Once a DMA transfer is made, a burst transfer is made in units of four clocks for the same component.

That is, one packet composed of four pixel data 310 for the Cb color component is transmitted to the video output interface 500 in one DMA transmission, and the same process is performed for the Cr and Y components in the same manner.

The video output interface 500 is an apparatus that enlarges horizontally and vertically the pixel data thus transmitted and provides a data format and timing suitable for the NTSC encoder 600.

3 is a block diagram of a line buffer for displaying an enlarged image according to an embodiment of the present invention.

As shown in the figure, a line buffer for displaying an enlarged image according to an embodiment of the present invention may include a DMA interface 510, an input buffer 520, a line memory 530, an inflation filter 540, and a multiplier. A flexure 550, a line buffer controller 560, a timing and controller 570, a write address generator 580, and a read address generator 590 are provided.

Now, the operation of the line buffer for the enlarged image display according to an embodiment of the present invention will be described.

The DMA interface 510 requests the data transfer (DRQ) to the DMA controller and applies the data carried on the DMA data bus (MBUS) to the input buffer 520 according to the signals DACK and MWRB in response thereto.

The input buffer 520 outputs the applied data to the line memory 530 according to the write control signal.

The line memory 530 performs a write operation on the data input from the input buffer 520 at the address created by the write address generator 580 according to the write control signal, and stores the data stored at the read address according to the read control signal. Read and print

Here, the line memory 530 is configured as a general memory of a unidirectional port, and crosses the write section and the read section one cycle at a time to perform a virtual dual pod function.

That is, the line buffer controller 560 applies a control signal corresponding to the multiplexer 580 and the line memory 530 so that the read address and the write address can be alternately applied through the multiplexer 590.

Data stored in the line memory 530 is stored in a repeating unit in the form of Cb Y Cr Y as shown in FIG. 4. These repeated units are structures that can be easily arranged when outputting data in CCIR 656 format.

Although the line memory of FIG. 4 operates like a kind of FIFO, the write data packet is composed of 16 cells (addresses) and the read data packet is 4 cells (addresses), not a structure that is stored and read in one cell (address) unit like a general FIFO. Can be written or read.

In addition, when it is necessary to read the data of the same line again for vertical enlargement, the line data can be read back from the line memory without reading the line data from the codec frame.

First, the write operation is as follows. The write address WP in the control order of the write address generator of FIG. 5 will be described below.

First, the write pointer WP, the write base pointer WBP, and the component mode COMP are initialized (501), and if the line memory is empty (502), a DMA transfer request is made (503).

If the component of the transmitted data is Cb (504) WP = WBP; WP = WBP + 4; WP = WBP + 8; The write address is generated in synchronization with the control signal of the control circuit in the order of WP = WBP + 12 (513), and the process returns to step 502 to determine whether the line memory is empty.

In the same way, if the component is Cr (506) WP = WBP + 2; WP = WBP + 6; WP = WBP + 10; Generates an address of WP = WBP + 14 (514), and if Y0 (507), WP = WBP + 1; WP = WBP + 3; WP = WBP + 5; Generate an address of WP = WBP + 7;

If the component is Y1 (507) WP = WBP + 9; WP = WBP + 11; WP = WBP + 13; Generates an address of WP = WBP + 15; (508) assigns Cb to the next component, and then increases the write base point (WBP) by 16 (510), if this value exceeds the maximum address in memory (511). 0 (512), otherwise, return to step 502 to determine if the line memory is empty.

This process generates an address for converting the DMA packet of FIG. 2 into the line memory format of FIG. 4.

In addition, the write operation fills data in asynchronous FIFO order in order to make full use of the free space in the line buffer.

Next, the read address generator will be described with reference to the read address pointer RP.

6 is a control flowchart of the write address generator of FIG. 3.

As shown in the figure, the control of the write address generator of FIG. 3 firstly initializes the read address pointer RF, the read base pointer RBP, the vertical line state variable VNUM (601), and the active of the horizontal line. After waiting for the state (602), the interpolation filter checks whether there is a line data read request (606). If there is a read request, waits until there is valid data in the line memory (607). RP = RBP in synchronization; RF = RBP + 1; RP = RBP + 2; RP = RBP + 3; After generating the address (608), the read base pointer (RBP) is increased by '4' (610) and returns to the process waiting for the active line state (602).

When the active state of the horizontal line is released by checking the active line state, it is checked whether the vertical line state variable (VNUM) is '0' (603). If it is '0', the read base pointer is increased by '4', and the next line starts. After applying the read base pointer RBP to the variable LSP and initializing the vertical line expansion variable VNUM (609), waiting for the horizontal line to become active (611), and then checking the active line state (602). Return to.

After the active state of the horizontal line is released and the vertical line state variable (VNUM) is decremented (604) and the read base pointer (RBP) is initialized to the line start pointer (LSP) (605), the horizontal line becomes active. Wait until 611.

That is, the process of repeating the filling of the next pixel line with the previous pixel line value is repeated, and the result is that the vertical line is enlarged by copying the previous pixel line until VNUM becomes '0'.

As described in detail above, the line buffer and the control method for the image enlargement display according to the present invention can display a video image of QCIF (176x144) or Sub-QCIF (128x96) stored in the image image buffer of the image compression / restore codec. It is used in a device that creates an image with the same size as the image stored in the image buffer or enlarged twice or four times for display on the image. Especially, the image codec has a structure that reads pixel data directly from the codec frame buffer. The effect is to reduce the components by avoiding the display frame buffer.

In the above description, the technical idea of the line buffer and the control method for the image enlarged display according to the present invention has been described with the accompanying drawings, but the exemplary embodiments of the present invention have been described by way of example and are not intended to limit the present invention. In addition, it is obvious that any person skilled in the art can make various modifications and imitations without departing from the scope of the technical idea of the present invention.

Claims (7)

A DMA interface for receiving and outputting data carried on a DMA data bus; An input buffer for temporarily storing data input from the DMA interface and outputting data stored according to a write control signal; A line memory for writing data input from the input buffer to a write address according to a write control signal, and reading and outputting data stored at a read address according to a read control signal; A multiplexer for alternately applying a read address and a write address to the line memory according to a control signal; A read address generator for outputting a read address to the line memory in accordance with a control signal; A write address generator for outputting a write address to the line memory in accordance with a control signal; And A line buffer configured to generate a write control signal to the input buffer, to generate an address generation control signal to the read address generator and the write address generator, and to generate a write read control signal to the line memory. Device. The method of claim 1, And an interflation filter for forming a pixel for horizontal enlargement on a horizontal line by using adjacent data among data input from the line memory. The method of claim 2, The line buffer controller, Generates a control signal for generating a write address for converting a DMA packet into the line memory format, outputs the control signal to the write address generator, and reads a read address for performing a repetitive read operation of each line according to a vertical line state variable. And generating and outputting a control signal to the read address generator. The method of claim 2, The line buffer controller, Initializes the write pointer (WP), the write base pointer (WBP), and the component mode (COMP), and outputs a DMA transfer request control signal to the input buffer if the line memory is empty, and if the component of the transmitted data is Cb, WP. = WBP; WP = WBP + 4; WP = WBP + 8; Outputting a control signal to the write address generator to generate write addresses in the order of WP = WBP + 12, and if the component is Cr, WP = WBP + 2; WP = WBP + 6; WP = WBP + 10; Outputs a control signal to the write address generator to generate addresses in the order of WP = WBP + 14; and if Y0, WP = WBP + 1; WP = WBP + 3; WP = WBP + 5; Outputs a control signal to the write address generator to generate a write address to generate an address of WP = WBP + 7; if the component is Y1, WP = WBP + 9; WP = WBP + 11; WP = WBP + 13; After outputting a control signal to the write address generator to generate an address of WP = WBP + 15; assigning Cb to a component and increasing the write base point WBP by 16, a write base pointer ends the write memory. And a line buffer device for initializing when larger than the address. The method according to claim 2 or 4, The line buffer controller, Initializes the read address pointer (RF), the read base pointer (RBP), and the vertical line state variable (VNUM), waits for the active state of the horizontal line, and when the active state becomes active, checks if there is a line data read request by the interpolation filter. Waits until there is valid data in the line memory when requested; RP = RBP; RF = RBP + 1; RP = RBP + 2; RP = RBP + 3; Outputs a control signal for generating an address to the read address generator, and when the active state of the horizontal line is released from the active line state, the read base pointer RBP is lined according to the vertical line state variable VNUM. Line buffer device, characterized in that initialized by the start pointer (LSP). A first step of determining whether the line memory is empty after initializing the write pointer (WP), the write base pointer (WBP), and the component mode (COMP); A second step of making a DMA transfer request if the line memory is empty as a result of the determination in the first step; If the component of the transmitted data is Cb WP = WBP; WP = WBP + 4; WP = WBP + 8; A third step of repeating the step of determining whether the line memory of the first step is empty after generating the write addresses in the order of WP = WBP + 12; If the component is Cr WP = WBP + 2; WP = WBP + 6; WP = WBP + 10; A fourth step of repeating the step of determining whether the line memory of the first step is empty after generating an address of WP = WBP + 14; If component is Y0 WP = WBP + 1; WP = WBP + 3; WP = WBP + 5; A fifth step of repeating the step of determining whether the line memory of the first step is empty after generating an address of WP = WBP + 7; If the component is Y1 WP = WBP + 9; WP = WBP + 11; WP = WBP + 13; A sixth step of repeating the step of determining whether the line memory of the first step is empty after generating an address of WP = WBP +15; A seventh step of determining whether the increased value exceeds the maximum address of the line memory by increasing the write base point (WBP) by 16 after designating Cb as a component; And As a result of the determination of the seventh step, if it exceeds WBP = 0, otherwise, the control of the line buffer device comprising the eighth step of performing repeatedly from the process of determining whether the line head of the first step is empty Way. A first step of initializing the read address pointer RF, the read base pointer RBP, and the vertical line state variable VNUM; Waiting for the active state of the horizontal line, and in the active state, checking the line data read request in the interpolation filter; A third step of waiting for valid data in a line memory when there is a read request as a result of the check in the second step; Synchronizes the read address with the control signal so that RP = RBP; RF = RBP + 1; RP = RBP + 2; RP = RBP + 3; A fourth step of repeating the process of waiting for the active line state of the second step after generating an address of the second step; A fifth step of checking whether the vertical line state variable VNUM is '0' when the active state of the horizontal line is released in the active line state; As a result of the inspection in the fifth step, if the value is '0', the read base pointer is increased by '4', the read base pointer RBP is applied to the next line start variable LSP, and the vertical line enlarged variable VNUM is initialized. A sixth step of waiting for the horizontal line to become active; And If the active state of the horizontal line is released and the vertical zoom variable is not yet '0', decrease the vertical zoom variable by '1', initialize the read base pointer (RBP) to the line start pointer (LSP), and then activate the horizontal line. Method of controlling a line buffer comprising a seventh step of waiting until.