KR100351991B1 - Data writing circuit for semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data write circuit of a semiconductor memory. In particular, an object of the present invention is to shorten the data writing time compared to the prior art by writing data simultaneously to a plurality of cells during a parallel test of the semiconductor memory. The present invention for this purpose pre-decodes the Y-address YADDR <0: 8> on the basis of the clock YCLK to address (AY0H <0: 7>, AY3H <0: 7>, AY6H <0: 7>). ) And a line selection signal YS <0> to a decoded Y-address predecoder 210 and the addresses AY0H <0: 7>, AY3H <0: 7>, and AY6H <0: 7>. Y-address decoder 220 for determining eight line selection signals YS <0>, YS <64>, YS <128>, ..., YS <448> among YS <511>, Sense amplification unit for amplifying external data and writing to the memory cell array 260 after determining the number of line selection signals YS <0>, YS <64>, YS <128>, ..., YS <448> And a main amplifier 230 for amplifying external input data and outputting the input / output selection signal IOSW to the sense amplifier 250 when the input / output selection signal IOSW is enabled, and an X-address by a control command CMD. Calculates XADDR, outputs a word line signal WL to the memory cell array 260, and then senses amplifies control signals CSP and CSN. And outputting (250) is composed of X- system controller 240 to drive a plurality of sense amplifiers.

Description

DATA WRITING CIRCUIT FOR SEMICONDUCTOR MEMORY}

The present invention relates to a semiconductor memory, and more particularly, to a data write circuit in a parallel test mode of a semiconductor memory.

1 is a block diagram of a data write circuit of a general semiconductor memory, as shown in FIG. 1, four memory banks 111 to 114 composed of four memory cell arrays each having 8 M bits, and the four memory banks 111 to 114. 114) four Y-address decoders 121 to 124 for outputting Y addresses respectively, and to the Y-address decoders 121 to 124 among the divided regions of the four memory banks 111 to 114, respectively. Four main amplifiers 131 to 134 for writing data to the corresponding area selected by the controller.

Referring to the operation of the prior art as follows.

When the 64-bit parallel test mode is set to write four input data to the four memory banks 111 to 114 at once, the four memory banks 111 to 114 are all activated, and then the four memory banks ( Four Y-address decoders 121 to 124 connected to 111 to 114 respectively select regions to be accessed for each of the memory banks 111 to 114.

At this time, each of the memory banks 111 to 114 is activated with only one of four divided regions accessible by the main amplifiers 131 to 134.

Accordingly, each of the main amplifiers 131 to 134 amplifies the external input data at the input / output terminals IO 2, 6, 9, and D, respectively, and then activates each of the four memory banks 111 to 114, respectively. Will be written to

That is, since the main amplifiers 131 to 134 can have their own data values for the adjacent main amplifiers (for example, 0-F-1-E), the independent data is also provided between adjacent cells connected to one line YS. You can write

For example, memory banks 111 are areas 0, 2, 4, and 6, memory banks 112 are areas 1, 3, 5, and 7, and memory banks 113 are 8, A, C, and E. Region and the memory bank 114 assumes that the regions 9, B, D, and F are activated by the respective Y-address decoders 121 to 124, the main amplifier 131 is connected to the input / output terminal IO. The external input data of the memory bank 111 is written to areas 0, 2, 4, and 6 of the memory bank 111, and the main amplifier 132 writes the external input data of the input / output terminal IO 6 to 1, 1, of the memory bank 112. The main amplifier 133 writes the external input data at the input / output terminal IO 9 to the areas 8, A, C, and E of the memory bank 113, and the main amplifier (133). 134 writes the external input data at the input / output terminal (IO) D in the areas 9, B, D, and F of the memory bank 114.

That is, 16 bits, that is, a total of 64 bits of data can be written to the four memory banks 111 to 114 at once.

However, conventionally, since 16 bits of data can be written to each memory bank at one time, that is, 16 main amplifiers are connected to each memory bank and one cell is connected to each main amplifier, thereby writing data to all cells of the semiconductor memory. This requires as many as 'memory capacity / 64-bit' writes.

Therefore, in the related art, as the capacity of the memory increases, the number of writes gradually increases, thereby degrading the performance of the memory.

For example, a 128M bit semiconductor memory requires 2M writes.

Accordingly, the present invention provides a data write circuit of a semiconductor memory invented to shorten the data writing time compared to the prior art by writing data to a plurality of cells at the same time in parallel testing of the semiconductor memory in order to improve the conventional problems. There is a purpose.

1 is a block diagram of a data write circuit of a conventional semiconductor memory.

2 is a block diagram of a data write circuit for an embodiment of the present invention.

3 is a waveform diagram of each part in FIG. 2;

Explanation of symbols on the main parts of the drawings

210: Y-address predecoder 220: Y-address decoder

230: main amplifier 240: X-based control unit

250: sense amplifier 260: memory cell array

The present invention provides a memory cell array for storing data in a parallel test mode of a semiconductor memory in order to achieve the above object, and a Y- that decodes Y-addresses to determine a plurality of lines YS. A plurality of sense amplifiers for amplifying data to be written to the memory cell array after the plurality of lines YS are determined by being connected to a plurality of bit lines of the memory cell array and the plurality of lines YS; One main amplifier to write to the amplifier, and X-based control unit for driving the word line and sense amplifier by decoding the X-address in the test mode.

The X-based control unit is configured to operate the plurality of sense amplifiers after one main amplifier writes data to the plurality of sense amplifiers.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

2 is a block diagram of a data write circuit for an embodiment of the present invention, as shown therein, a memory cell array 260 for storing data and a test mode signal TEST enabled for a clock YCLK. Y-address predecoder 210 which pre-decodes the Y-address YADDR <0: 8> and outputs the addresses AY0H <0: 7>, AY3H <0: 7>, and AY6H <0: 7>. ) And the line selection signals YS <0> to YS by processing the addresses AY0H <0: 7>, AY3H <0: 7>, AY6H <0: 7> in the Y-address predecoder 210. A Y-address decoder 220 for determining eight line selection signals YS <0>, YS <64>, YS <128>, ..., YS <448> among the < 511 > The eight line selection signals YS <0>, YS <64>, YS <128>, ..., YS <448> are connected to a plurality of bit lines BL and BLB of the array 260. After the amplification of the external data and the sense amplifier 250 for writing to the memory cell array 260, and amplifies the external input data When the input / output selection signal IOSW is enabled, the main amplifier 230 which outputs to the sense amplifier 250 and the test mode signal TEST are enabled and the X-address is generated by the control command CMD. X-D outputs a word line signal WL to the memory cell array 260 by calculating XADDR, and then outputs control signals CSP and CSN to the sense amplifier 250 to drive a plurality of sense amplifiers. The system control unit 240 is configured.

The memory cell array 260 includes a plurality of memory cells each formed of a MOS transistor and a cell capacitor.

Referring to the waveform and the waveform of Figure 3 will be described the operation and effect of the embodiment of the present invention configured as described above are as follows.

According to the present invention, the circuit is configured to have a signal reaching the main amplifier 230 of each bank with the same path as in the prior art, but the connection of the signal line is changed from the mirror afterwards.

First, the test signal TEST is high as shown in Fig. 3 (a), that is, the input / output selection signal IOSW is made high as shown in Fig. 3 (c), and is then inputted to the test signal TEST. The enabled X-system controller 240 calculates the X-address XADDR based on the clock YCLK as shown in FIG. 3 (d) by the control command CMD, and thus, the word line of the memory cell array 260. Will be selected.

In addition, when the test signal TEST from the outside is high, that is, when the test mode is entered, the Y-address predecoder 210 displays the Y-address YADDR as shown in FIG. 3E based on the clock YCLK. ), All of the addresses (AY6H <0: 7>) of the output addresses (AY0H <0: 7>, AY3H <0: 7>, AY6H <0: 7>) are output high and the Y-address decoder 220 ) Calculates the eight selection signals of the line selection signals YS <0: 511> high by calculating the address AY6H <0: 7>.

For example, it is assumed that eight of YS <0>, YS <64>, YS <128>, ..., YS <448> are high as shown in FIG.

At this time, the eight line selection signals YS <0> and YS <64 while the external input data is transmitted from the external input / output terminals MIO and MIOB to the internal input / output terminals LIO and LIOB by the main amplifier 230. >, YS <128>, ..., YS <448> are high, the data contained in the internal input and output terminals (LIO, LIOB) is written to each sense amplifier provided in the sense amplifier 250.

However, in the related art, since the sense amplifier is operated when data is written to each sense amplifier, when the data stored in the sense amplifier and the data to be written are opposite to each other, the write driving capability of the main amplifier must be stronger than that of each sense amplifier. do.

Therefore, in the past, when a plurality of sense amplifiers are connected to one main amplifier, data having opposite values cannot be written.

However, in the present invention, the respective sense amplifiers do not operate when the main amplifier 230 receives data from the sense amplifier 250.

That is, the control signals CSN and CSP in the X-based control unit 240 are in the 1 / 2Vdl state.

As a result, the signals loaded on the internal input / output terminals LIO and LIOB are sufficiently loaded on the respective sense amplifiers so that a small voltage difference occurs between the bit lines BL and BLB at the time when the clock YCLK rises.

Therefore, when the X-based control unit 240 operates the control signal CSP (CSN) as shown in FIG. 3 (i) (j) after the clock YCLK becomes low, each of the sense amplifiers 250 is provided. The sense amplifier amplifies the voltage difference between the bit lines BL and BLB as shown in FIG. 3 (k) and writes them to the respective cell capacitors of the memory cell array 260.

Meanwhile, in the present invention, if the number of upper bits having a high level among the output signals of the Y-address predecoder 210 is adjusted, the number of sense amplifiers connected to one main amplifier 230 may be adjusted.

As described in detail above, the present invention improves the problem that only 64 data can be written at a time in the 64-bit parallel test mode in the prior art, depending on the number of memory cells connected to one main amplifier. 64, including 512 Can be increased in multiples.

Therefore, the present invention has an effect that the data write time can be shortened even when the memory capacity increases.

Claims (2)

A data write circuit in a parallel test mode of a semiconductor memory, the data write circuit comprising: a memory cell array for storing data; a Y-address decoding unit configured to decode Y-addresses to determine a plurality of lines YS; A plurality of sense amplifiers connected to a plurality of bit lines of a plurality of lines YS to determine amplification of data, and to write the memory cell array; and a main amplifier to write external input data to the plurality of sense amplifiers. And an X-based controller configured to decode the X-address in a test mode to drive a word line and a sense amplifier. The data write circuit of claim 1, wherein the X-based controller is configured to operate the plurality of sense amplifiers after one main amplifier writes data to the plurality of sense amplifiers.