[go: up one dir, main page]

KR100351066B1 - Method of manufacturing recessed electrode type solar cell - Google Patents

Method of manufacturing recessed electrode type solar cell Download PDF

Info

Publication number
KR100351066B1
KR100351066B1 KR1019950059494A KR19950059494A KR100351066B1 KR 100351066 B1 KR100351066 B1 KR 100351066B1 KR 1019950059494 A KR1019950059494 A KR 1019950059494A KR 19950059494 A KR19950059494 A KR 19950059494A KR 100351066 B1 KR100351066 B1 KR 100351066B1
Authority
KR
South Korea
Prior art keywords
semiconductor substrate
electrode
forming
type
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019950059494A
Other languages
Korean (ko)
Other versions
KR970054561A (en
Inventor
유. 에봉 에이.
조영현
이수홍
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR1019950059494A priority Critical patent/KR100351066B1/en
Publication of KR970054561A publication Critical patent/KR970054561A/en
Application granted granted Critical
Publication of KR100351066B1 publication Critical patent/KR100351066B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00Individual photovoltaic cells, e.g. solar cells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00Individual photovoltaic cells, e.g. solar cells
    • H10F10/10Individual photovoltaic cells, e.g. solar cells having potential barriers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00Manufacture or treatment of devices covered by this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00Constructional details of devices covered by this subclass
    • H10F77/20Electrodes
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

PURPOSE: A method for fabricating a solar cell of a depressed electrode shape is provided to reduce a manufacturing cost by using only a spin coater and a rapid thermal annealer. CONSTITUTION: An n+ type dopant is coated on a front face of a semiconductor substrate(1) and a baking process is performed. A p+ type dopant is coated on a back face of the semiconductor substrate(1) and the baking process is performed. Oxide layers(3) are formed on the front face and the back face of the semiconductor substrate(1), respectively. An n+ layer(2) and a p+ layer(7) are respectively formed on the front face and the back face of the semiconductor substrate(1) by performing an annealing process. A groove is formed on the front face of the semiconductor substrate(1). The dopant is injected into the groove. The groove is etched. A front electrode(6) is formed on the groove. An anti-reflective layer(4) is formed on the resultant. The oxide layer is selectively removed from the back face of the semiconductor substrate(1). A back electrode(8) is formed on the back face of the semiconductor substrate(1).

Description

함몰전극형 태양전지의 제조방법Method of manufacturing recessed electrode type solar cell

본 발명은 함몰전극형 태양전지의 제조방법에 관한 것으로서, 보다 상세하기로는 우수한 변환효율을 갖는 함몰진극형 태양전지를 낮은 제조원가로 제조할 수 있는 방법을 제공하는 것이다.The present invention relates to a method of manufacturing a recessed electrode solar cell, and more particularly, to provide a method of manufacturing a recessed polarized solar cell having excellent conversion efficiency at a low manufacturing cost.

태양전지는 반도체의 광 기전력 효과를 이용한 것으로서, p형 반도체와 n형반도체를 조합하여 만든다. p형 반도체와 n형 반도체가 접한 부분(pn 접합부)에 빛이 들어오면, 빛 에너지에 의하여 반도체 내부에서 마이너스의 전하(전자)와 플러스의 전하(정공)가 발생한다.The solar cell uses the photovoltaic effect of the semiconductor and is made by combining a p-type semiconductor and an n-type semiconductor. When light enters a portion (pn junction) where the p-type semiconductor and the n-type semiconductor come into contact with each other, negative charges (electrons) and positive charges (holes) are generated within the semiconductor by the light energy.

빛에너지에 의해 발정된 전자와 정공은 내부의 전계에 의하여 각각 n형 반도체측과 p형 반도체측으로 이동하여 양쪽의 전극부에 모아진다. 이러한 두 개의 전극을 도선으로 연결하면 전류가 흐르고 외부에서 전력으로 이용할 수 있게 된다.The electrons and holes ignited by the light energy move to the n-type semiconductor side and the p-type semiconductor side by the internal electric field, and are collected at both electrode portions. Connecting these two electrodes with wires allows the current to flow and can be used as power from the outside.

태양전지는 전극의 형태에 따라 스크린 프린팅형 태양전지(Screen Printing Solar Cell: SPSC)와 함몰전극형 태양전지(Buried Contact Solar Cell: BCSC)로 구분할 수 있다.Solar cells can be classified into screen printing solar cells (SPSCs) and buried contact solar cells (BCSCs) according to the shape of the electrodes.

SPSC는 일반적으로 제조하기가 용이하지만 금속 전극에서의 반사, 후면 전류 흐름에서 기인된 저항 및 일반적으로 깊게 도핑되어 있는 이미터 영역에서의 캐리아들의 높은 재결합률로 인하여 전지의 변환효율이 낮은 편이고 어스펙트비가 불량하다.SPSCs are generally easy to manufacture, but the conversion efficiency of the battery is low due to reflections in the metal electrode, resistance due to back current flow and high recombination rates of the carriers in the deeply doped emitter regions. Spect ratio is bad.

한편, BCSC는 금속 전극을 반도체 기판 전면내로 깊게 파인 홈에 형성시키는데, 이 전지의 변환효율은 SPSC보다 높은 편이다. 반도체 기판 전면내로 깊게 도핑되어 있는 금속 전극은 전지의 활성영역으로 떨어져 있기 때문에 개방회로전압 및 전지 변환효율을 감소시키는 원인으로 작용하는 캐리아들의 재결합이 감소된다.BCSC, on the other hand, forms metal electrodes in grooves deep into the front surface of the semiconductor substrate, and the conversion efficiency of the battery is higher than that of SPSC. Since the metal electrode deeply doped into the front surface of the semiconductor substrate is separated from the active region of the cell, the recombination of the carriers, which causes the open circuit voltage and the cell conversion efficiency, is reduced.

제1도는 통상적인 BCSC의 구조를 도시한 도면으로서, 이를 제조하는 방법은 다음과 같다.1 is a view showing the structure of a conventional BCSC, a method of manufacturing the same as follows.

먼저 반도체 기판 (1)에 텍스처링을 실시하여 기판 전면과 후면에 피라미드구조를 형성한다. 상기 반도체 기판 전면 (1)상부에 pn접합을 형성하여 n+층 (2)를 형성한 다음, 산화공정을 실시하여 반도체 기판 (1) 전면과 후면에 산화막 (3)을 형성한다. 상기 반도체 기판 (1) 전면내로 홈을 깊게 스크라이빙한 다음, 이 홈내에 전도성 금속을 도금하여 전면전극 (6)를 형성한다. 이 때 전면전극 (6)이 형성되어 있는 홈의 하부에는 n++층 (5)가 형성되어 있다.First, texturing is performed on the semiconductor substrate 1 to form pyramid structures on the front and rear surfaces of the substrate. A pn junction is formed on the front surface of the semiconductor substrate 1 to form an n + layer 2, and then an oxidation process is performed to form an oxide film 3 on the front and rear surfaces of the semiconductor substrate 1. After deeply scribing a groove into the front surface of the semiconductor substrate 1, a conductive metal is plated in the groove to form the front electrode 6. At this time, an n ++ layer 5 is formed in the lower portion of the groove in which the front electrode 6 is formed.

반도체 기판 (1) 후면에는 알루미늄을 증착, 소결하여 P+층 (7)를 형성한다. 그 상부에 전도성 금속을 도금하여 후면전극 (8)을 형성한다.Aluminum is deposited on the back surface of the semiconductor substrate 1 and sintered to form a P + layer 7. The back electrode 8 is formed by plating a conductive metal on the upper portion thereof.

BCSC를 상기 방법에 따라 제조하는 경우, 고가의 용광로(furnace)와 진공증발기 등이 필요하며 많은 비용과 시간이 소요된다. 또한 제조공정중에 몇몇의 공정이 고온조건하에서 실시되는데, 이러한 고온조건하의 공정 수가 많으면 많을수록 오염발생률이 높아지고 제조비용이 상승되는 원인으로서 작용한다.In the case of manufacturing the BCSC according to the above method, an expensive furnace, a vacuum evaporator, and the like are required, which is expensive and time consuming. In addition, some of the processes are performed under high temperature conditions during the manufacturing process. The more processes under such high temperature conditions, the higher the incidence of contamination and the higher the manufacturing cost.

그러므로 본 발명의 목적은 상기 문제점을 해결하여 낮은 제조원가와 단시간내에 우수한 변환효율 특성을 갖는 함몰전극형 테양전지를 제조할 수 있는 방법을 제공하는 것이다.Therefore, an object of the present invention is to solve the above problems and to provide a method for manufacturing a depressed electrode-type solar cell having low conversion cost and excellent conversion efficiency characteristics in a short time.

상기 목적을 달성하기 위하여 본 발명에서는 (a) p형 반도체 기판 전면에 n형 불순물을 제1스핀코팅한 다음, 베이킹하는 단계;In order to achieve the above object, the present invention comprises the steps of: (a) first spin-coating an n-type impurity on the entire surface of a p-type semiconductor substrate, and then baking;

(b) 반도체 기판 후면에 p형 불순물을 스핀코팅한 다음, 베이킹하고나서, 반도체 기판 전면과 후면에 산화막을 형성하는 단계;(b) spin-coating a p-type impurity on the back surface of the semiconductor substrate, baking and forming an oxide film on the front and back surfaces of the semiconductor substrate;

(c) 급속 열적 어닐링기를 이용한 어닐링으로 상기 반도체 기판 전면과 후면에 n+층과 p+층을 각각 형성하는 단계;(c) forming n + and p + layers on the front and back surfaces of the semiconductor substrate by annealing using a rapid thermal annealing group, respectively;

(d) 상기 반도체 기판 전면에 n형 불순물을 제2스핀코팅하는 단계;(d) second spin coating n-type impurities on the entire surface of the semiconductor substrate;

(e) 레이저를 이용하여 상기 반도체 기판 전면내에 홈을 형성하면서 홈내로 n형 불순물을 주입하는 단계;(e) implanting n-type impurities into the grooves while forming grooves in the entire surface of the semiconductor substrate using a laser;

(f) 상기 홈을 식각한 다음, 이 홈에 전면전극을 형성하는 단계;(f) etching the groove, and then forming a front electrode in the groove;

(g) 반도체 기판 전면에 형성된 상기 결과물상에 반사방지막을 형성하고, 마스크를 이용하여 반도체 기판 후면의 산화막만을 선택적으로 제거하는 단계;(g) forming an anti-reflection film on the resultant formed on the entire surface of the semiconductor substrate, and selectively removing only the oxide film on the back side of the semiconductor substrate using a mask;

(h) 스크린 프린팅 방법을 이용하여 산화막이 제거된 반도체 기판 후면에 후면전극을 형성하는 단계를 포함하는 것을 특징으로 하는 함몰전극형 태양전지의 제조방법이 제공된다.(h) there is provided a method of manufacturing a recessed electrode type solar cell, comprising forming a back electrode on a back surface of a semiconductor substrate from which an oxide film is removed using a screen printing method.

상기 (a) 단계에서 n형 불순물의 농도는 7∼13wt%이고, 베이킹은 120 ∼170℃에서 15∼20분정도 실시되며, 상기 (b) 단계에서 p형 불순물의 농도가 4∼6wt%이고 베이킹이 120∼170℃에서 15∼20분정도 실시된다. 또한 상기 (d) 단계에서 n형 불순물의 농도는 약 100%이다.In step (a), the concentration of the n-type impurity is 7 to 13 wt%, the baking is carried out at 120 to 170 ° C. for about 15 to 20 minutes, and in the step (b), the concentration of the p-type impurity is 4 to 6wt%. Baking is performed at 120-170 degreeC for about 15 to 20 minutes. In addition, the concentration of the n-type impurity in step (d) is about 100%.

상기 (g) 단계에서의 산화막 식각시, 버퍼불산(Buffered Hydrofluoric acid)을 이용한 습식식각을 이용하여 석각한다.When the oxide layer is etched in the step (g), it is etched using wet etching using buffered hydrofluoric acid.

전면전극과 후면전극은 니켈, 구리, 은, 티타늄, 팔라듐, 주석, 아연, 인듐 구리, 알루미늄 및 그 산화물중에서 선택된 적어도 하나를 무전해 도금방법 또는 전기 도금방법을 이용하여 형성시킨다.The front electrode and the back electrode are formed of at least one selected from nickel, copper, silver, titanium, palladium, tin, zinc, indium copper, aluminum, and oxides thereof using an electroless plating method or an electroplating method.

종래의 함몰전극형 태양전지 제조시, 고가의 진공증착설비를 사용하여 반도체 기판에 불순물을 주입하는 데 반해, 본 발명에서는 이를 위하여 급속 열적 어닐링기(Rapid Thermal Annealer: RTA)를 사용한다. 여기에서 RTA를 이용하면 매우 단시간 즉, 30초 내지 1분동안의 열처리로 충분하므로 제조비용이 절감될 뿐만 아니라, 반도체 기판내에 불순물이 재분포되는 것이 방지되고 품질이 낮은 반도체 기판에서의 벌크의 수명이 유지될 수 있다.In manufacturing a conventional recessed electrode type solar cell, an impurity is implanted into a semiconductor substrate using an expensive vacuum deposition apparatus, whereas in the present invention, a Rapid Thermal Annealer (RTA) is used for this purpose. In this case, the use of RTA is sufficient for heat treatment for a very short time, that is, 30 seconds to 1 minute, which not only reduces the manufacturing cost, but also prevents the redistribution of impurities in the semiconductor substrate and the bulk life of the low quality semiconductor substrate. This can be maintained.

상기 n형 불순물과 p형 불순물로는 통상적으로 사용하는 물질을 이용한다.As the n-type impurity and the p-type impurity, a material commonly used is used.

이하, 본 발명에 따른 함몰전극형 태양전지의 제조방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, a method of manufacturing a recessed electrode solar cell according to the present invention will be described in detail with reference to the accompanying drawings.

제2A도는 반도체 기판 (1) 전면에는 n+층 (2), 산화막 (3)을 형성하고, 기판 (1) 후면에는 p+층 (7)과 산화막 (3')을 형성하는 단계를 도시한 것이다.2A illustrates the steps of forming an n + layer 2 and an oxide film 3 on the front surface of the semiconductor substrate 1, and forming a p + layer 7 and an oxide film 3 ′ on the back surface of the substrate 1. will be.

먼저 반도체 기판 (1)을 세정한 다음, 반도체 기판 (1) 전면에 n형 불순물인 인을 7∼13wt% 농도로 스핀코팅한다. 그 후 120∼170℃에서 15∼20분동안 베이킹한다.First, the semiconductor substrate 1 is cleaned, and then spin-coated with phosphorus, which is an n-type impurity, on the entire surface of the semiconductor substrate 1 at a concentration of 7 to 13 wt%. Then bake at 120-170 ° C. for 15-20 minutes.

반도체 기판 (1) 후면에는 p형 불순물인 보론을 4∼6wt% 농도로 스핀코팅한다. 그 후 120∼170℃에서 15∼20분동안 베이킹한다. 그리고 나서 산화공정을 실시하여 반도체 기판 (1) 전면과 후면에 산화막 (3) 및 (3')을 각각 형성한다.The back surface of the semiconductor substrate 1 is spin-coated with boron as a p-type impurity at a concentration of 4 to 6 wt%. Then bake at 120-170 ° C. for 15-20 minutes. Then, an oxidation process is performed to form oxide films 3 and 3 'on the front and rear surfaces of the semiconductor substrate 1, respectively.

RTA를 이dyd하여 30초 내지 1분정도 아닐링하여 반도체 기판 (1) 전면에 경이미터를 형성하여 n+층 (2)을, 반도체 기판 후면에는 p+층 (7)을 형성한다.The RTA is then annealed for about 30 seconds to 1 minute to form an emitter on the front surface of the semiconductor substrate 1 to form the n + layer 2 and the p + layer 7 on the back surface of the semiconductor substrate.

제2B도는 n+층 (2)과 산화막 (3)이 형성되어 있는 반도체 기판 (1) 전면내로 홈을 형성하는 단계를 도시한 것이다.FIG. 2B shows a step of forming a groove into the entire surface of the semiconductor substrate 1 in which the n + layer 2 and the oxide film 3 are formed.

반도체 기판 (1) 전면에 n형 불순물인 인을 약 100% 농도로 스핀코팅한 다음, 레이저를 이용하여 반도체 기판 (1) 전면에 홈을 새기면서 형성된 홈내로 인을 주입한다.The phosphor is n-type impurity phosphorus is coated on the entire surface of the semiconductor substrate 1 at a concentration of about 100%, and then phosphorus is injected into the grooves formed while carving the grooves on the front surface of the semiconductor substrate 1 using a laser.

제2C도는 반도체 기판 (1) 전면내로 깊게 파인 홈에 전도성 금속을 도금하여 전면전극 (6)을 형성하는 단계를 도시한 것이다.FIG. 2C shows a step of forming the front electrode 6 by plating a conductive metal in a groove deep into the front surface of the semiconductor substrate 1.

반도체 기판 (1) 전면내에 형성된 홈을 약 5분정도 직각한 다음, 무전해 도금방법을 이용하여 홈내에 전도성금속을 도금한다. 이 때 전극 (6)은 약 3000Å정도의 두께로 형성된다.The grooves formed in the front surface of the semiconductor substrate 1 are perpendicular to each other for about 5 minutes, and then the conductive metal is plated in the grooves using the electroless plating method. At this time, the electrode 6 is formed to a thickness of about 3000 kPa.

제2D도는 전면전극 (6) 영역을 제외한 반도체 기판 (1) 전면에 반사방지막 (4)를 형성한 다음, 반도체 기판 (1) 후면의 산화막 (3')을 제거한 다음, 후면전극 (8)을 형성하는 단계를 도시한 것이다.2D shows an anti-reflection film 4 formed on the entire surface of the semiconductor substrate 1 except for the region of the front electrode 6, then the oxide film 3 'behind the semiconductor substrate 1 is removed, and then the rear electrode 8 is removed. It shows the step of forming.

전면전극 (6)이 형성되어 있는 상기 반도체 기판 (1) 전면에 반사방지물질을 분무하여 반사방지막 (4)를 형성한다. 반사방지물질로는 통상적으로 사용하는 물질이면 모두 사용할 수 있는데, 특히 산화티탄이 바람직하다.An antireflection material is sprayed on the entire surface of the semiconductor substrate 1 on which the front electrode 6 is formed to form an antireflection film 4. As the antireflection material, any material that is commonly used may be used, and titanium oxide is particularly preferable.

마스크를 이용하여 반도체 기판 (1) 전면을 보호한 상태에서 반도체 기판을 BHF용액에 침적시켜서 반도체 기판 (1) 후면의 산화막 (3')을 선택적으로 식각한다. 이 때 반도체 기판 (1) 전면에 형성되어 있는 산화티탄막은 산화막 제거시 일반적으로 포지티브 포토레지스트로 사용되는 마스크 물질막으로서 산화막의 식각액으로 사용된 BHF의 농도하에서는 식각되지 않는다.The oxide film 3 'on the back surface of the semiconductor substrate 1 is selectively etched by depositing the semiconductor substrate in the BHF solution while the entire surface of the semiconductor substrate 1 is protected using a mask. At this time, the titanium oxide film formed on the entire surface of the semiconductor substrate 1 is a mask material film generally used as a positive photoresist when the oxide film is removed and is not etched under the concentration of BHF used as an etching solution of the oxide film.

산화막 (3')이 제거된 반도체 기판 (1) 후면에 스크린 인쇄방법을 사용하여 전극을 인쇄한 다음, 소결하여 후면전극 (8)을 형성하면 제1도의 구조를 갖는 함몰전극형 태양전지를 얻을 수 있다.When the electrode is printed on the back surface of the semiconductor substrate 1 from which the oxide film 3 'is removed by using a screen printing method, and then sintered to form the back electrode 8, a depressed electrode solar cell having the structure of FIG. 1 is obtained. Can be.

상기에서 알 수 있듯이, 통상적인 함몰전극형 태양전지 제조시 고가의 진공 증착 설비가 필요하고 제조시간 및 비용이 많이 소요되는 데 반해, 본 발명에서는 스핀 코터와 RTA만이 필요하며 고온조건하의 공정의 수가 적기 때문에 오염발생률이 적고 제조비용이 절감된다. 따라서 통상적인 화석연료와 유리하게 경쟁할 수 있는 유리한 위치에 서게 되는 것이다. 또한 본 발명에서는 종래의 포토리소그래피 공정을 사용하지 않고서도 이미터 확산 및 후면전계를 동시에 이끌어내며, 특히 캐리아의 확산거리가 긴 반도체 기판을 사용한 경우, 보다 향상된 후면 활성화를 유도해 낼 수 있게 된다.As can be seen from the above, in the case of manufacturing a conventional recessed electrode type solar cell, an expensive vacuum deposition apparatus is required and manufacturing time and cost are high. However, in the present invention, only a spin coater and an RTA are required, and the number of processes under high temperature conditions is high. Due to the low pollution rate and the manufacturing cost is reduced. It is therefore in an advantageous position to compete favorably with conventional fossil fuels. In addition, the present invention derives the emitter diffusion and the backside field simultaneously without using the conventional photolithography process, and in particular, when using a semiconductor substrate with a long diffusion distance of the carrier, it is possible to induce improved backside activation. .

본 발명에 따르면, 낮은 생산단가로 변환효율이 우수한 함몰전극형 태양전지를 제조할 수 있다.According to the present invention, it is possible to manufacture a sunken electrode solar cell excellent in conversion efficiency at a low production cost.

제1도는 함몰전극형 태양전지의 구조를 도시한 도면이고,1 is a view showing the structure of a recessed electrode type solar cell,

제2A도, 제2B도, 제2C도 및 제2D도는 본 발명의 제조방법을 설명하기 위한 도면이다.2A, 2B, 2C and 2D are views for explaining the manufacturing method of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1. p형 반도체 기판 2. n+1. p-type semiconductor substrate 2. n + layer

3. 산화막 4. 반사방지막3. Oxide 4. Antireflection

5. n++층 6. 전면전극5. n ++ layer 6. Front electrode

7. p+층 8. 후면전극7. p + layer 8. Back electrode

Claims (6)

(a) p형 반도체 기판 전면에 n형 불순물을 제1스핀코팅한 다음, 베이킹하는 단계;(a) first spin-coating an n-type impurity on the entire surface of the p-type semiconductor substrate and then baking it; (b) 반도체 기판 후면에 p형 불순물을 스핀코팅한 다음, 베이킹하고 나서, 반도체 기판 전면과 후면에 산화막을 형성하는 단계;(b) spin-coating a p-type impurity on the back side of the semiconductor substrate, baking and forming an oxide film on the front side and the back side of the semiconductor substrate; (c) 급속 열적 어닐링기를 이용한 어닐링으로 상기 반도체 기판 전면과 후면에 n+층과 p+층을 각각 형성하는 단계;(c) forming n + and p + layers on the front and back surfaces of the semiconductor substrate by annealing using a rapid thermal annealing group, respectively; (d) 상기 반도체 기판 전면에 n형 불순물을 제2스핀코팅하는 단계;(d) second spin coating n-type impurities on the entire surface of the semiconductor substrate; (e) 레이저를 이용하여 상기 반도체 기판 전면내에 홈을 형성하면서 홈내로 n형 불순물을 주입하는 단계;(e) implanting n-type impurities into the grooves while forming grooves in the entire surface of the semiconductor substrate using a laser; (f) 상기 홈을 식각한 다음, 이 홈에 전면전극을 형성하는 단계;(f) etching the groove, and then forming a front electrode in the groove; (g) 반도체 기판 전면에 형성된 상기 결과물상에 반사방지막을 형성하고, 마스크를 이용하여 반도체 기판 후면의 산화막만을 선택적으로 제거하는 단계;(g) forming an anti-reflection film on the resultant formed on the entire surface of the semiconductor substrate, and selectively removing only the oxide film on the back side of the semiconductor substrate using a mask; (h) 스크린 프린팅 방법을 이용하여 산화막이 제거된 반도체 기판 후면에 후면전극을 형성하는 단계를 포함하는 것을 특징으로 하는 함몰전극형 태양전지의 제조방법.(h) forming a back electrode on the back side of the semiconductor substrate from which the oxide film has been removed using a screen printing method. 제1항에 있어서, 상기 (a)단계에서 n형 불순물의 농도가 7∼13 wt%이고, 베이킹이 120∼170℃에서 15∼20분정도 실시되는 것을 특징으로 하는 함몰전극형 태양전지의 제조방법.The method of claim 1, wherein the concentration of the n-type impurities in the step (a) is 7 to 13 wt%, baking is carried out for 15 to 20 minutes at 120 to 170 ℃ manufacturing of the recessed electrode type solar cell Way. 제1항에 있어서, 상기 (b) 단계에서 p형 불순물의 농도가 4∼6wt%이고, 베이킹이 120∼170℃에서 15∼20분정도 실시되는 것을 특징으로 하는 함몰전극형 태양전지의 제조방법.The method of claim 1, wherein the concentration of the p-type impurity in step (b) is 4 to 6 wt%, and baking is performed at 120 to 170 ° C. for about 15 to 20 minutes. . 제1항에 있어서, 상기 (d) 단계에서 n형 불순물의 농도가 약 100wt%인 것을 특징으로 하는 함몰전극형 태양전지의 제조방법.The method of claim 1, wherein the concentration of the n-type impurity in step (d) is about 100wt%. 제1항에 있어서, 상기 (g) 단계에서 산화막 식각시 버퍼불산을 이용하여 식각하는 것을 특징으로 하는 함몰전극형 태양전지의 제조방법.The method of claim 1, wherein in the step (g), the oxide film is etched using buffer hydrofluoric acid. 제1항에 있어서, 상기 전극이 니켈, 구리, 은, 티타늄, 팔라듐, 주석, 아연, 인듐 구리, 알루미늄 및 그 산화물로 이루어진 군으로부터 선택된 물질로 이루어지는 것을 특징으로 하는 함몰전극형 태양전지의 제조방법.The method of claim 1, wherein the electrode is made of a material selected from the group consisting of nickel, copper, silver, titanium, palladium, tin, zinc, indium copper, aluminum, and oxides thereof. .
KR1019950059494A 1995-12-27 1995-12-27 Method of manufacturing recessed electrode type solar cell Expired - Fee Related KR100351066B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950059494A KR100351066B1 (en) 1995-12-27 1995-12-27 Method of manufacturing recessed electrode type solar cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950059494A KR100351066B1 (en) 1995-12-27 1995-12-27 Method of manufacturing recessed electrode type solar cell

Publications (2)

Publication Number Publication Date
KR970054561A KR970054561A (en) 1997-07-31
KR100351066B1 true KR100351066B1 (en) 2002-12-18

Family

ID=37489107

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950059494A Expired - Fee Related KR100351066B1 (en) 1995-12-27 1995-12-27 Method of manufacturing recessed electrode type solar cell

Country Status (1)

Country Link
KR (1) KR100351066B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101160114B1 (en) * 2009-05-07 2012-06-26 주식회사 효성 A fabricating method of buried contact solar cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101160114B1 (en) * 2009-05-07 2012-06-26 주식회사 효성 A fabricating method of buried contact solar cell

Also Published As

Publication number Publication date
KR970054561A (en) 1997-07-31

Similar Documents

Publication Publication Date Title
US6524880B2 (en) Solar cell and method for fabricating the same
US8697475B2 (en) Solar cell and method for manufacturing the same
US5258077A (en) High efficiency silicon solar cells and method of fabrication
US5468652A (en) Method of making a back contacted solar cell
US8399287B1 (en) Method of manufacturing solar cell
KR101225978B1 (en) Sollar Cell And Fabrication Method Thereof
CN102623517B (en) Back contact type crystalline silicon solar cell and production method thereof
KR19990063990A (en) Self-Regulating (SALDE) Solar Cells with Partially Deeply Dispersed Emitters and Methods of Manufacturing the Same
CN103904138A (en) Full back side contact crystalline silicon cell and preparation method thereof
JP2024082212A (en) Solar cell and its manufacturing method, photovoltaic module
US6277667B1 (en) Method for fabricating solar cells
KR100416740B1 (en) Manufacturing method of back side sintered silicon solar cell
KR101045859B1 (en) Solar cell and manufacturing method thereof
KR100366350B1 (en) Solar cell and method for manufacturing the same
KR100351066B1 (en) Method of manufacturing recessed electrode type solar cell
KR20160090084A (en) Solar cell and method for manufacturing the same
KR100322708B1 (en) Method for fabricating self-voltage applying solar cell
KR20140049624A (en) Solar cell and method for fabricating the same
JP2012212769A (en) Solar cell element
KR100416739B1 (en) Method of manufacturing silicon solar cell
KR101779057B1 (en) Wafer type solar cell and method for manufacturing the same
KR100397596B1 (en) Recessed electrode solar cell and manufacturing method thereof
KR100374810B1 (en) Method of manufacturing recessed electrode type solar cell
KR100416741B1 (en) Rear locally sintered silicon solar cell
KR100378347B1 (en) Method of manufacturing recessed electrode type solar cell

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19951227

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20000216

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19951227

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20011221

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20020708

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20020820

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20020821

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20050701

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20060703

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20070703

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20080708

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20090728

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20100812

Start annual number: 9

End annual number: 9

FPAY Annual fee payment

Payment date: 20110804

Year of fee payment: 10

PR1001 Payment of annual fee

Payment date: 20110804

Start annual number: 10

End annual number: 10

FPAY Annual fee payment

Payment date: 20120720

Year of fee payment: 11

PR1001 Payment of annual fee

Payment date: 20120720

Start annual number: 11

End annual number: 11

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

Termination category: Default of registration fee

Termination date: 20140709