KR100349806B1 - Method for Sequence Error Detection and Correction in AAL 1 Type Cell - Google Patents

Abstract

The present invention relates to a sequential error detection / correction method of an ATM cell. The sequential error detection / correction method of an ATM cell according to the present invention includes checking an SC field of an SN field of a SAR-PDU header, and then selecting the SAR-PDU. Determining whether it is normal (a); (B) checking an SNP field to detect an error of the CRC field according to the determination result of the SC field order, and correcting the SC field or the CRC field according to the error detection result; (C) detecting an error of a parity bit by checking the SNP field according to an error detection and correction result of the CRC field; And (d) determining whether the SN is valid or invalid based on the determination result and the error detection result of the steps (a) to (c) and transmitting the result to the convergence sublayer. According to the sequential error detection / correction method of an ATM cell according to the present invention, a conventional SN error analysis in a correction mode is performed by comparing an SC value, a CRC field value, and a parity bit value to compare a CRC field value and a parity bit value. It provides a more advanced error analysis method than SN error analysis in correction mode. Accordingly, the BER between the terminal and the terminal can be reduced, and in particular, the call quality in the voice transmission service sensitive to the BER between the terminal and the terminal can be improved.

Description

Method for Sequence Error Detection and Correction in AAL 1 Type Cell}

The present invention relates to a sequential error detection / correction method of an AAL type 1 cell in an asynchronous transmission mode (hereinafter referred to as 'ATM'), and more particularly, to a cell division assembly sub-assembly of an AAL type 1 cell in an ATM device processing an AAL type 1 cell. Effectively detects and corrects sequence number errors in the Segmentation and Reassembly-Protocol Data Unit (SAR-PDU) headers, minimizing cell loss and occurring in the process The present invention relates to a sequential error detection / correction method that is suitable for a service that is sensitive to delay occurring between terminal and terminal by minimizing delay.

1 illustrates the format of an AAL Type 1 SAR-PDU.

ATM is a protocol that carries various kinds of traffic in B-ISDN. ATM handles one of the AAL types 1 to 5 according to the type of traffic. The protocol for processing double voice is AAL type 1. AAL is divided into a cell division assembly sublayer and a convergence sublayer. One of the most important functions of the cell division assembly sublayer is serial number management. If the cell division assembly sublayer of the transmitting end receives the serial number for each SAR-PDU from the convergence sublayer and transmits it through the ATM layer, the cell division assembly sublayer of the receiving end extracts the serial number from the SAR-PDU and convergence sublayer. The convergence sublayer uses this to locate missing or misinserted SAR-PDUs.

In addition, the cell division assembly sublayer of the transmitting end protects and transmits the serial number using cyclic redundancy checking (CRC) and parity bits, and the cell division assembly sublayer of the receiving end decodes the serial number by decoding the CRC and parity bits. Check whether there is an error, and if an error is detected, process it in the convergence sublayer.

2 is an exemplary diagram illustrating a conventional error detection / correction method. A conventional error detection / correction method will be described in detail with reference to the SAR-PDU shown in FIG. 1.

The CRC value for the first 4 bits of the SAR-PDU header of the transmitting end is recorded in the 3-bit CRC field 21 in the SNP (Sequence Number Protection) 20 field, and the CRC field 21 and the sequence number (SN) Even parity bits for the field 10 are recorded in the last bit of the SAR-PDU header and sent to the receiver through the ATM layer. The cell division assembly sublayer of the receiving end detects an error in the SAR-PDU header by checking the SNP field 20 in the SAR-PDU header in the SAR-PDU received from the ATM layer.

The cell division assembly sublayer of the receiving end operates in two modes, a correction mode and a detection mode. The dual basic mode is a correction mode that provides single bit error detection. If an error is detected in the correction mode, the single bit error is corrected (S10), and the mode of the cell division sublayer is switched to the detection mode. In the detection mode, when an error is detected, the SN field 10 to be processed in the convergence sublayer is invalid (S11), and when the error is not detected, it is switched back to the correction mode (S12). Table 1 and Table 2 summarize the operation in each mode.

TABLE 1

CRC Parity SN status mode normal normal Not calibrated Serial number valid Switch calibration mode error error Not calibrated Serial number invalid Keep detection mode normal error Not calibrated Serial number invalid Keep detection mode error normal Not calibrated Serial number invalid Keep detection mode

TABLE 2

CRC Parity SN status mode normal normal Valid SAR-PDU Serial Number Valid Keep calibration mode error error Validate the SC serial number based on the CRC value, assuming a single bit error in the SC field Detection mode switch normal error Parity bit is valid because the parity bit is regarded as an error. Detection mode switch error normal Unable to correct because a multi-bit error occurred Detection mode switch

Cell splitting assembly sub-layer of the receiving end in the SAR-PDU header to extract the CSI (11) and the serial number, and informs the convergence sublayer with this of the state of the SN field 10 is checked by the SNP field 20. The convergence sublayer uses this to locate lost or misinserted SAR-PDU payloads and maintain serial numbers.

As described above, the conventional sequential error detection and correction method checks the error of the SN field 10 in accordance with the CRC field 21 and the parity bit 22 of the SNP field 20 in the cell division sublayer. In the correction mode, if an error occurs in both the CRC field and the parity bit, it is defined as a single bit error, and the CRC field is corrected on the assumption that there is no error and an error occurs in the SN field. In this case, when an error occurs in the CRC field, there is a problem of correcting a normally received SN field. In addition, when an error occurs in the CRC field and there is no error in the parity bit, there is a problem in that a range of error correction is small because no correction is defined as a multi-bit error.

An object of the present invention is to solve the above problems, to effectively detect and correct the serial number error of the SAR-PDU header of the AAL type 1 cell in the ATM device processing the AAL type 1 cell to minimize the loss of the cell, the processing Provides a sequential error detection / correction method that analyzes the cause of the error in detail when the error occurs in the correction mode to minimize the delay in the process and to be suitable for a service sensitive to delay occurring between the terminals and the terminal. It is.

1 illustrates the format of an AAL Type 1 SAR-PDU,

2 is an exemplary diagram illustrating a conventional error detection / correction method;

3 is a flowchart illustrating a sequential error detection / correction process of an asynchronous transmission mode cell according to an embodiment of the present invention.

In order to achieve the above object, the sequential error detection / correction method of the ATM cell according to the present invention, by checking the SC field of the SN field of the SAR-PDU header to determine whether the order of the SAR-PDU is normal (a); (B) checking an SNP field to detect an error of the CRC field according to the determination result of the SC field order, and correcting the SC field or the CRC field according to the error detection result; (C) detecting an error of a parity bit by checking the SNP field according to an error detection and correction result of the CRC field; And (d) determining whether the SN is valid or invalid based on the determination result and the error detection result of the steps (a) to (c) and transmitting the result to the convergence sublayer.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

Prior to the detailed description, terms used in the detailed description are summarized.

'CBR' stands for Constant Bit Rate.

'SRTS' stands for Synchronous Residual Time Stamp.

'SDT' stands for Structure Data Transfer.

'BER' stands for Bit Error Rate.

'SAR-PDU' stands for Segmentation and Reassembly-Protocol Data Unit.

3 is a flowchart illustrating a sequential error detection / correction process of an asynchronous transmission mode cell according to an embodiment of the present invention. Reference will be made to the reference numerals of FIG. 1.

If the serial number used for the sequential error detection / correction process is checked and transmitted to the convergence sublayer in the cell division assembly sublayer of the receiver as in the conventional method, the convergence sublayer is a Robust SN Algorithm or Fast SN. Using Algorithm Maintain the serial number. In addition, the cell division assembly sublayer of the receiving end operates with two modes, a correction board and a detection mode, and sets the correction mode as the basic mode. Conventionally, error analysis of serial number has only CRC field and parity bit, but it provides improved correction function by comparing not only CRC field and parity bit but also SC field of SN field in SAP-PDU header. When the CSI bit of the SN field is used to recover the frequency of the source clock using the SRTS method in an asynchronous CBR service that is not synchronized to the synchronizer clock, or when the structure data having a size larger than 1 octet is transmitted using the SDT method. Is used to indicate that there is a pointer field. Unlike the SC, the CSI bits are not related to each other before and after the CSI bits, and thus only the CSI bits do not detect an error of the CSI bits. Therefore, in the present embodiment, it is assumed that the CSI bit is always transmitted without error, and the error of the SN is detected and corrected with three factors, SC, CRC, and parity bit.

Briefly describing the sequential error detection / correction process of the asynchronous transmission mode cell according to the present invention carried out in the cell division assembly sublayer of the receiver, 1) Check the SC field of the SN field of the SAR-PDU header to determine the sequence number 2) correct the serial number, CRC field value or parity bit value by checking the CRC field of the SNP field, and 3) enable / disable the serial number using the corrected serial number, CRC and parity bit. Determining and delivering to the convergence sublayer. The process is described in detail below.

The cell division assembly sublayer of the receiving end checks the SN field 10 in the SAR-PDU header received from the ATM layer to determine whether the SC field is in order with the SC field of the immediately preceding SAR-PDU (S100, S110). .

In step S110, if the SC field order is not correct, it is determined whether or not there is an error in the CRC field (S120).

If there is an error in the CRC field, the SC field is corrected to match the SC field of the SAR-PDU received immediately before (S130), and it is determined whether there is an error in the parity bit (S140). If there is an error in the parity bit, the serial number is invalidated and the detection mode is switched (S160). If the parity bit is normal, the serial number is valid and the mode is switched to the detection mode (S161).

If the CRC field is normal, the serial number is invalid and the detection mode is switched (S160). If the order of the SC fields is not correct and the CRC field is normal, it is assumed that the corresponding SAR-PDU is incorrectly inserted regardless of whether the parity bit is in error.

In step S110, if the SC field order is correct, it is determined whether there is an error in the CRC field (S121).

If there is an error in the CRC field, the CRC field value is corrected (S131), and it is determined whether there is an error in the parity bit (S141). If there is an error in the parity bit, the serial number is invalidated and the detection mode is switched (S160). If the parity bit is normal, the serial number is valid and the detection mode is switched (S161).

If the CRC field is normal, it is determined whether there is an error in the parity bit (S142). If there is an error in the parity bit, the parity bit is corrected (S150), the serial number is valid, and the detection mode is switched (S161). If the parity bit is normal, the serial number is valid.

Maintain a positive mode (S162). Table 3 summarizes the status of serial numbers according to the SC field, CRC field, and parity bits and modes according to FIG. 3.

TABLE 3

SC CRC Parity SN status mode normal normal normal Valid SAR-PDU Serial Number Valid Keep calibration mode normal error error Assuming a single bit error in the CRC, correct the CRC based on the SC value. Correct the CRC and recalculate the parity. Detection mode switch normal normal error Parity bit is valid because the parity bit is regarded as an error. Detection mode switch normal error normal The CRC is considered to be a multi-bit error, and the CRC is corrected based on the SC value.When the CRC is corrected and the parity is recalculated, the serial number is valid if it is normal and the serial number is invalid. Detection mode switch error normal normal Do not calibrate as incorrectly inserted SAR-PDUs Serial Number Invalid Detection mode switch error error error Assuming that the SC has a multi-bit error, the SC is calibrated based on the SC value of the SAR-PDU received just before, and after recalculating the CRC and parity, the serial number is valid if both are normal. Is invalid, serial number is invalid Detection mode switch

error normal error Do not calibrate as incorrectly inserted SAR-PDUs Serial Number Invalid Detection mode switch error error normal Based on the SC value of the SAR-PDU received just before, the SC is assumed to have a single bit error, and the SC is corrected based on the corrected CRC and the parity is recalculated. Detection mode switch

As described above, according to the sequential error detection / correction method of the ATM cell according to the present invention, by comparing the SC field, the CRC field, and the parity bits in the error analysis of the serial number in the correction mode, only the CRC field and the parity bits are used. It provides a better error analysis method than the serial number error analysis in the conventional calibration mode. Accordingly, the BER between the terminal and the terminal can be reduced, and in particular, the call quality in the voice transmission service sensitive to the BER between the terminal and the terminal can be improved.

Claims (8)

Checking the SC field of the SN field of the SAR-PDU header to determine whether the order of the SAR-PDU is normal (a); (B) checking an SNP field to detect an error of the CRC field according to the determination result of the SC field order, and correcting the SC field or the CRC field according to the error detection result; (C) detecting an error of a parity bit by checking the SNP field according to an error detection and correction result of the CRC field; And Sequential error detection of an ATM cell, comprising the step (d) of determining whether the SN is valid or invalid based on the determination result and the error detection result of the steps (a) to (c). / Correction method. The method of claim 1, wherein the SAR-PDUs are not in the correct order in step (a), and an error is detected in the CRC field in step (b). Step (b) corrects the SC field based on the SC field of the SAR-PDU received immediately before; The step (d) is characterized in that if the error is detected in the parity bit, the SN is determined to be invalid, switch to the detection mode, and forwarded to the convergence sublayer, characterized in that the ATM cell sequential error detection / correction method. The method of claim 2, wherein if the parity bit in step (d) is normal, The step (d) is to determine the SN invalid, switch to the detection mode and forwarded to the convergence sub-layer, characterized in that the error detection / correction method of the ATM cell. The method of claim 1, wherein the SAR-PDUs are out of order in step (a) and the CRC field is normal in step (b). Without going through step (c), Step (d) determines the invalidity of the SN, switches to the detection mode, and forwards it to the convergence sublayer. The method of claim 1, wherein the SAR-PDU order is normal in step (a), and if there is an error in the CRC field in step (b), Step (b) corrects the SC field based on the SC field of the SAR-PDU received immediately before; The step (d) is characterized in that if the error is detected in the parity bit, the SN is determined to be invalid, and switched to the detection mode, and forwarded to the convergence sublayer. 6. The ATM of claim 5, wherein in step (d), if the parity bit is normal, step (d) determines that the SN is valid, switches to detection mode, and forwards it to the convergence sublayer. Sequential error detection / correction method for cells. The method of claim 1, wherein if the order of SAR-PDUs is normal in step (a), the CRC field is normal in step (b), and there is an error in the parity bit in step (c), (E) correcting the parity bits after the step (c), The step (e) is to determine the validity of the SN, switch to the detection mode, and forwarded to the convergence sub-layer sequential error detection / correction method of the ATM cell. The method of claim 1, wherein the SAR-PDU order is normal in step (a), the CRC field is normal in step (b), and the parity bit is normal in step (c). The step (e) is to determine the validity, maintain the correction mode, and deliver to the convergence sub-layer sequential error detection / correction method.