KR100344764B1 - Method of isolating semiconductor device - Google Patents
Method of isolating semiconductor device Download PDFInfo
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- KR100344764B1 KR100344764B1 KR1019990043996A KR19990043996A KR100344764B1 KR 100344764 B1 KR100344764 B1 KR 100344764B1 KR 1019990043996 A KR1019990043996 A KR 1019990043996A KR 19990043996 A KR19990043996 A KR 19990043996A KR 100344764 B1 KR100344764 B1 KR 100344764B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000005368 silicate glass Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 39
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체장치의 크기가 점차로 감소되는 추세에 따라 활성영역과 비활성영역을 구분하는 PGI(Profilled Grooved Isolation) 형성 시, 트렌치의 선폭이 좁게 콘트롤됨에 따라 PGI 주변부위에 전계가 밀집하여 소자특성이 악화되는 것을 방지할 수 있는 소자격리방법에 관한 것이다.According to the present invention, when the PGI (Profilled Grooved Isolation) is formed to separate the active and inactive regions according to the trend of decreasing size of the semiconductor device, the electric field is concentrated in the peripheral area of the PGI as the line width of the trench is controlled narrowly. It relates to a device isolation method that can prevent deterioration.
본 발명의 소자격리방법은 반도체기판 상에 산화막 및 질화막을 순차적으로 형성하는 공정과,질화막 상에 소자격리영역을 덮도록 패터닝된 마스크를 형성하는 공정과, 마스크를 이용하여 질화막의 일부까지 제거함으로써 제 1트렌치를 형성하는 공정과, 마스크를 제거하는 공정과, 질화막을 마스크로 하여 반도체기판의 일부까지 식각하여 제 1트렌치의 하부를 라운드처리하는 공정과, 라운딩처리된 제 1트렌치 측면에 전도층 측벽을 형성하는 공정과, 전도층 측벽을 포함한 질화막을 마스크로 하여 반도체기판을 식각하여 제 2트렌치를 형성하는 공정과, 제 2트렌치 표면를 산화시키는 공정과, 질화막 상에 표면산화된 제 2트렌치를 채우도록 격리막을 형성하는 공정을 구비한 것이 특징이다.The device isolation method of the present invention comprises the steps of sequentially forming an oxide film and a nitride film on a semiconductor substrate, forming a patterned mask to cover the device isolation region on the nitride film, and removing a part of the nitride film by using a mask Forming a first trench, removing a mask, etching a portion of the semiconductor substrate using a nitride film as a mask, and rounding a lower portion of the first trench; and a conductive layer on the rounded first trench side. Forming a sidewall; etching a semiconductor substrate using a nitride film including a conductive layer sidewall as a mask; forming a second trench; oxidizing a second trench surface; and oxidizing the second trench surface-oxidized on the nitride film. It is characterized by including the step of forming the separator so as to fill.
따라서, 상기 특징을 갖는 본 발명에서는 소자의 활성영역과 활성영역을 구분짓는 격리막 형성에 있어서, 트렌치 코너에 다결정실리콘 측벽을 형성하여 라운드처리시킴에 따라, 트렌치 코너에 미치는 전계밀집현상을 방지할 수 있는 잇점이 있다.Accordingly, in the present invention having the above characteristics, in forming an isolation layer that separates an active region and an active region of the device, a polysilicon sidewall is formed and rounded at the trench corners, thereby preventing electric field concentration on the trench corners. There is an advantage.
따라서, 본 발명에서는 소자특성의 안정화할 수 있다.Therefore, in the present invention, device characteristics can be stabilized.
Description
본 발명은 소자격리방법에 관한 것으로, 특히, 반도체장치의 크기가 점차로 감소되는 추세에 따라 활성영역과 비활성영역을 구분하는 PGI(Profilled Grooved Isolation) 형성 시, 트렌치(trench)의 선폭이 좁게 콘트롤됨에 따라 PGI 주변부위에 전계가 밀집하여 소자특성이 악화되는 것을 방지할 수 있는 소자격리방법에 관한 것이다.The present invention relates to a device isolation method, and in particular, when a PGI (Profilled Grooved Isolation) is formed that separates an active region from an inactive region according to a trend of decreasing size of a semiconductor device, the width of the trench is narrowly controlled. Accordingly, the present invention relates to a device isolation method capable of preventing a deterioration of device characteristics due to dense electric fields around PGI.
도 1a 내지 도 1f는 종래기술에 따른 반도체장치의 제조공정도이다.1A to 1F are manufacturing process diagrams of a semiconductor device according to the prior art.
도 1a와 같이, 반도체기판(100) 상에 산화실리콘을 증착하여 제 1산화막(102)을 형성하고, 그 상부에 질화막(104)을 순차적으로 형성시킨다.As shown in FIG. 1A, silicon oxide is deposited on the semiconductor substrate 100 to form a first oxide film 102, and a nitride film 104 is sequentially formed thereon.
이 후, 질화막(104) 상에 감광막을 도포한 후, 노광 및 현상하여 소자 격리영역(Ⅰ)이 정의된 감광막패턴(106)을 형성한다. 도면부호 Ⅱ는 소자 활성영역을 도시한 것이다.Thereafter, a photosensitive film is coated on the nitride film 104, and then exposed and developed to form a photosensitive film pattern 106 in which the element isolation region I is defined. Reference numeral II shows the device active region.
도 1b와 같이, 감광막패턴(106)을 마스크로 하여 질화막(104)과 제 1산화막(102)의 일부를 LOCOS(LOCal Oxide Silicon)건식식각을 진행시킴으로써 하부가 각진 형상을 갖는 LOCOS 건식식각 프로파일을 얻는다.As shown in FIG. 1B, LOCOS dry etching profiles having lower angles are formed by performing LOCOS dry etching on the nitride film 104 and the first oxide film 102 using the photoresist pattern 106 as a mask. Get
도 1c와 같이, 감광막패턴을 제거한다.As shown in FIG. 1C, the photoresist pattern is removed.
질화막(104)을 마스크로 이용하여 반도체기판(100)에 PGI건식식각을 하여 트렌치(t1)를 형성한다.Using the nitride film 104 as a mask, PGI dry etching is performed on the semiconductor substrate 100 to form a trench t1.
도 1d와 같이, 질화막(104)을 마스크로 이용하여 트렌치(t1) 내부를 산화시킴으로써 트렌치(t1)를 덮는 얇은 막인 제 2산화막(106)이 형성된다.As illustrated in FIG. 1D, the second oxide film 106, which is a thin film covering the trench t1, is formed by oxidizing the inside of the trench t1 using the nitride film 104 as a mask.
도 1e와 같이, 질화막(104) 상에 제 2산화막(106)을 덮도록 충전물질층(108)을 형성한다.As shown in FIG. 1E, the filling material layer 108 is formed on the nitride film 104 to cover the second oxide film 106.
이 충전물질층(108)은 갭필(gap fill)특성이 우수한 절연물질이 이용된다.As the filling material layer 108, an insulating material having excellent gap fill characteristics is used.
도 1f와 같이, 반도체기판(100)이 노출되는 시점까지 충전물질층(108) 및 질화막(104) 및 제 1산화막(202)을 CMP(Chemical Mechanical Polishing)처리한다.As shown in FIG. 1F, the CMP (Chemical Mechanical Polishing) process of the filling material layer 108, the nitride film 104, and the first oxide film 202 is performed until the semiconductor substrate 100 is exposed.
따라서, 도면에서와 같이, 트렌치(t1) 내부에 잔류된 충전물질층(10)은 소자의 활성영역(Ⅱ)간을 격리시키는 격리영역(Ⅰ)의 격리막(108a)이 된다.Accordingly, as shown in the figure, the filling material layer 10 remaining in the trench t1 becomes the isolation film 108a of the isolation region I that isolates the active region II of the device.
그러나, 종래의 기술에서는 트렌치 코너(corner)가 각져 있기 때문에 이 부분으로 전계가 밀집되어 소자에 악영향을 미치는 문제점이 있었다.However, in the related art, since the trench corners are angled, electric fields are concentrated in this portion, which adversely affects the device.
상기의 문제점을 해결하고자, 본 발명의 목적은 소자활성영역과 비활성영역(격리영역) 간을 격리시키는 격리막 형성 시, 트렌치의 코너 부위에 전계가 밀집되는 현상을 방지할 수 있는 소자격리방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a device isolation method that can prevent the electric field is concentrated in the corner portion of the trench when forming a separator to isolate between the device active region and the inactive region (isolation region). I will.
상기 목적을 달성하고자, 본 발명의 소자격리방법은 반도체기판 상에 산화막 및 질화막을 순차적으로 형성하는 공정과, 질화막 상에 소자격리영역을 덮도록 패터닝된 마스크를 형성하는 공정과, 마스크를 이용하여 질화막의 일부까지 제거함으로써 제 1트렌치를 형성하는 공정과, 마스크를 제거하는 공정과, 질화막을 마스크로 하여 반도체기판의 일부까지 식각하여 제 1트렌치의 하부를 라운드처리하는 공정과, 라운딩처리된 제 1트렌치 측면에 전도층 측벽을 형성하는 공정과, 전도층 측벽을 포함한 질화막을 마스크로 하여 반도체기판을 식각하여 제 2트렌치를 형성하는 공정과, 제 2트렌치 표면를 산화시키는 공정과, 질화막 상에 표면산화된 제 2트렌치를 채우도록 격리막을 형성하는 공정을 구비한 것이 특징이다.In order to achieve the above object, the device isolation method of the present invention comprises the steps of sequentially forming an oxide film and a nitride film on a semiconductor substrate, forming a patterned mask to cover the device isolation region on the nitride film, and using a mask Forming a first trench by removing a portion of the nitride film, removing a mask, etching a portion of the semiconductor substrate using the nitride film as a mask, and rounding the lower portion of the first trench; Forming a sidewall of the conductive layer on one side of the trench, etching a semiconductor substrate using a nitride film including the sidewall of the conductive layer as a mask, forming a second trench, oxidizing the second trench surface, and a surface on the nitride film And a step of forming an isolation film to fill the oxidized second trench.
도 1a 내지 도 1f는 종래기술에 따른 반도체장치의 제조공정도이고,1A to 1F are manufacturing process diagrams of a semiconductor device according to the prior art,
도 2a 내지 도 2h는 본 발명에 따른 반도체장치의 제조공정도이다.2A to 2H are manufacturing process diagrams of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 200. 반도체기판 102, 106, 202, 210. 산화막100, 200. Semiconductor substrate 102, 106, 202, 210. Oxide film
104, 204. 질화막 106, 206. 마스크패턴104, 204. Nitride films 106, 206. Mask pattern.
t1, s1, s2. 트렌치 108, 212. 충전물질층t1, s1, s2. Trench 108, 212. Filler Layer
108a, 212a. 격리막 208. 다결정실리콘 측벽108a, 212a. Separator 208. Polysilicon Sidewalls
Ⅰ, Ⅲ. 소자격리영역 Ⅱ, Ⅳ. 소자활성영역I, III. Device isolation region II, IV. Device active area
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도 2h는 본 발명에 따른 반도체장치의 제조과정을 보인 공정단면도이다.2A through 2H are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the present invention.
도 2a와 같이, 반도체기판(200) 상에 산화실리콘 등을 증착하여 제 1산화막(202)을 형성하고, 그 상부에 질화막(204)을 형성한다.As shown in FIG. 2A, a silicon oxide or the like is deposited on the semiconductor substrate 200 to form a first oxide film 202, and a nitride film 204 is formed thereon.
이어서, 질화막(204) 상에 감광막을 도포한 후, 소자의 격리영역(Ⅲ)을 노출시키도록 패터닝된 감광막패턴(206)을 형성한다. 도면부호 Ⅳ는 소자의 활성영역을 의미한다.Subsequently, after the photoresist film is applied on the nitride film 204, the photoresist pattern 206 patterned to expose the isolation region III of the device is formed. Reference numeral IV denotes an active region of the device.
도 2b와 같이, 감광막패턴(206)을 마스크로 하여 제 1산화막(202)의 일부가 잔류되도록 LOCOS건식식각함으로써 하부가 각진 형상을 갖는 LOCOS 건식식각 프로파일을 얻는다.As shown in FIG. 2B, LOCOS dry etching is performed such that a portion of the first oxide film 202 remains using the photoresist pattern 206 as a mask to obtain a LOCOS dry etching profile having an angular shape at a lower portion thereof.
도 2c와 같이, 감광막패턴을 제거한다.As shown in FIG. 2C, the photoresist pattern is removed.
질화막(204)을 마스크로 이용하여 기판(200)의 소정영역까지 식각함으로써 제 1트렌치(s1)이 형성된다. 제 1트렌치(s1)은 질화막(204)을 기준으로, 질화막(204) 하부의 기판(200)으로 갈수록 측면으로의 식각이 진행되어 라운드(round)형상을 갖는다.The first trench s1 is formed by etching the nitride layer 204 as a mask to a predetermined region of the substrate 200. The first trench s1 has a round shape by etching toward the side toward the substrate 200 under the nitride film 204 based on the nitride film 204.
도 2d와 같이, 질화막(204) 상에 다결정실리콘층을 형성한 후, 질화막(204)이 노출되는 시점까지 에치백(etch back)한다. 이 결과, 제 1트렌치(s1)측면에 다결정실리콘 측벽(208)이 형성된다.As shown in FIG. 2D, the polysilicon layer is formed on the nitride film 204, and then etched back until the nitride film 204 is exposed. As a result, the polysilicon sidewall 208 is formed on the side of the first trench s1.
도 2e와 같이, 다결정실리콘 측벽(208) 및 질화막(204)을 마스크로 하여 반도체기판(200)을 식각하여 소자의 격리영역(Ⅲ)에 제 2트렌치(s2)를 형성한다.As shown in FIG. 2E, the semiconductor substrate 200 is etched using the polysilicon sidewall 208 and the nitride film 204 as a mask to form a second trench s2 in the isolation region III of the device.
도 2f와 같이, 질화막(204)을 마스크로 하여 제 2트렌치(s2) 표면을 산화시키어 제 2산화막(210)을 형성한다.As shown in FIG. 2F, the surface of the second trench s2 is oxidized using the nitride film 204 as a mask to form a second oxide film 210.
도 2g와 같이, 질화막(204) 상에 제 2산화막(210)을 채우도록 충전물질층(212)을 형성한다.As shown in FIG. 2G, a filling material layer 212 is formed on the nitride film 204 to fill the second oxide film 210.
이 충전물질층(212)은 제 2트렌치(s2)와 같이 선폭이 좁은 공간을 채울 수 있도록 스텝커버리지(step coverage)가 우수한 절연물질이 이용된다.As the filling material layer 212, an insulating material having excellent step coverage is used to fill a space having a narrow line width, such as the second trench s2.
충전물질층(212)으로는 SOG(Spin On Glass)방법으로 도포된 절연물질, USG(Undoped Silicate Glass) 등의 절연물질 등이 이용된다.As the filling material layer 212, an insulating material coated by a spin on glass (SOG) method, an insulating material such as USG (Undoped Silicate Glass), or the like is used.
도 2h와 같이, 반도체기판(200)이 노출되는 시점까지 충전물질층(212)과 질화막(204)과 제 1산화막(202)을 제거한다.As shown in FIG. 2H, the filling material layer 212, the nitride layer 204, and the first oxide layer 202 are removed until the semiconductor substrate 200 is exposed.
이 결과, 제 2트렌치(s2) 내부에 충전물질층이 잔류되며, 이 잔류된 충전물질층은 소자 격리영역의 격리막(212a)이 된다.As a result, the filling material layer remains in the second trench s2, and the remaining filling material layer becomes the isolation layer 212a of the device isolation region.
따라서, 본 발명에서는 소자영역의 격리막 형성에 있어서, 트렌치 코너를 라운드처리함에 따라, 전계가 밀집되는 현상을 방지할 수 있다.Therefore, in the present invention, the formation of the isolation layer in the element region can prevent the phenomenon of dense electric field by rounding the trench corners.
상술한 바와 같이, 본 발명에서는 소자의 활성영역과 비활성영역을 구분짓는 PGI 형성 시, 트렌치 코너에 다결정실리콘 측벽을 형성하여 라운드처리시킴에 따라, 트렌치 코너에 미치는 전계밀집현상을 방지할 수 있는 잇점이 있다.As described above, in the present invention, when forming the PGI that separates the active region and the inactive region of the device, the polysilicon sidewalls are formed at the corners of the trench to round the surface, thereby preventing electric field density on the trench corners. There is this.
따라서, 본 발명에서는 소자특성의 안정화할 수 있다.Therefore, in the present invention, device characteristics can be stabilized.
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