KR100341579B1 - Repair device of semiconductor memory device - Google Patents

Abstract

The present invention is to provide a repair device for a semiconductor memory device that can reduce the power of the laser used in the fuse cutting by reducing the width of the conductive material used as the fuse to prevent damage to the device by the laser. The repair apparatus of the invention comprises a signal line; Precharge means for precharging the signal line to a logic high; Inverting / latching means for inverting / latching the signal loaded on the signal line and outputting a control signal for selecting a normal cell or a redundancy cell; A first transistor having a source-drain path connected between any node of the signal line and a ground power supply terminal; A fuse connected between an address signal input terminal and a gate terminal of the first transistor; A second transistor for turning off the first transistor when the fuse is cut and an address signal is activated and input to the address signal input terminal; And floating prevention means for preventing the gate terminal of the first transistor from floating when the fuse is cut and the address signal is inactivated.

Description

Repair device of semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a repair device.

In general, since the cost of a semiconductor device is greatly influenced by its yield, a redundant memory cell is basically added to the normal memory cell in order to improve the yield. Thus, if a few defective memory cells are generated, a method (repair) of replacing them with redundant memory cells has been used. The replacement of the redundant memory cells is to replace the redundant memory cells with redundant memory cells provided in each memory cell block by laser cutting a fuse corresponding to each memory cell address and a failing memory cell. Use a way to do it.

1 is a circuit diagram of a repair apparatus of the prior art.

Referring to FIG. 1, a repair apparatus according to the related art includes a plurality of parallel-connected NMOS transistors 100 having an address input to a gate end, and a source-drain path formed at a fuse and a ground end, and a drain of the NMOS transistor. A plurality of fuses 110 formed between the stage and the first node, the PMOS transistor 120 having a pre-charge signal ctr as a gate terminal, and having a source-drain path formed between the power supply voltage and the first node; An inverter 130 that inverts the signal of one node and outputs the normal cell and the repair cell to a second node that selects a normal cell and a repair cell; The PMOS transistor 140 is formed between the nodes.

Looking at the operation and operation of each configuration for the repair device of the prior art, when the fuse is not cut, the precharge signal (ctr) is applied to the first node as a logic low voltage level of the applied power supply voltage This is maintained as it is and is continuously latched by the inverter 130 and the PMOS transistor 140. When a specific address is applied and the address signal is activated to be logic high, the enMOS transistor 100 is turned on so that the current having the voltage of the power supply voltage level precharged to the first node is grounded. Flow into the stage makes the first node logic low, and is inverted through the inverter 130 to make the second node logic high. The redundancy memory cell is then not accessed and the normal memory cell is accessed.

When the fuse is cut, a path through which the first node, which has been precharged, flows to the ground terminal is opened to maintain the logic high. The first node is then inverted through the inverter 130 such that the second node becomes a logic low to access the redundancy cell.

Through this process, the role of the fuse should be designed to flow the current of the first node to the ground terminal. Therefore, the conductor used as the fuse should have a sufficient width, which means that the power should be high when cutting the laser.

Therefore, the fuse is basically designed to allow a large amount of current flow, so the fuse should be laid out to a certain extent. As a result, when the fuse is cut, the power of the laser must be used high, and as a result, the circuit or insulator near the fuse may be destroyed, which may cause a fatal problem in the long-term reliability of the device.

The present invention has been made to solve the problems of the prior art as described above, it is possible to reduce the width of the conductive material used as a fuse to reduce the power of the laser used for cutting the fuse to prevent damage to the device by the laser It is an object of the present invention to provide a repair apparatus.

1 is a repair apparatus of the prior art,

2 is a repair apparatus of the present invention.

Explanation of symbols on the main parts of the drawings

240: fuse

The repair apparatus of the present invention to achieve the above object is a signal line; Precharge means for precharging the signal line to a logic high; Inverting / latching means for inverting / latching the signal loaded on the signal line and outputting a control signal for selecting a normal cell or a redundancy cell; A first transistor having a source-drain path connected between any node of the signal line and a ground power supply terminal; A fuse connected between an address signal input terminal and a gate terminal of the first transistor; A second transistor for turning off the first transistor when the fuse is cut and an address signal is activated and input to the address signal input terminal; And floating prevention means for preventing the gate terminal of the first transistor from floating when the fuse is cut and the address signal is inactivated.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a circuit diagram of the repair apparatus of the present invention.

Referring to FIG. 2, the repair apparatus of the present invention includes a normal line or redundancy by inverting / latching a signal line, a precharge means 100 for precharging the signal line to logic high, and a signal loaded on the signal line. Inverting / latching means 200 for outputting a control signal for selecting a cell, a first transistor 400 having a source-drain path connected between an arbitrary node of the signal line and a ground power supply terminal, an address signal input end, A fuse 300 connected between the gate terminal of the first transistor and a second transistor 600 for turning off the first transistor when the fuse is cut and an address signal is activated and input to the address signal input terminal; And a floating prevention means 500 for preventing the gate terminal of the first transistor from floating when the fuse is cut and the address signal is inactivated. The.

The floating preventing means 500 is provided with the inverting means for inverting and outputting the address signal inputted to the address signal input terminal and the output of the inverting means as a gate and between the gate terminal of the first transistor and the ground power supply terminal. And a third transistor n1 having a drain path formed therein.

The precharge means 100 includes a PMOS transistor having a drain terminal and a gate terminal connected to a power supply voltage, and a source terminal connected to the signal line to apply a power supply voltage to the signal line.

The inverting / latching means 200 inverts the signal of the signal line to select a normal cell and a redundancy cell, an output of the inverter is input to a gate terminal, and a source-drain path is a power supply voltage and the signal line. It has a morph transistor formed in between.

Referring to the operation of the repair apparatus of the present invention, when the fuse is not cut, the precharge means 100 applies a power supply voltage to a signal line, and the voltage level of the applied power supply voltage is maintained as it is. The latch is continuously latched by the inverter 200 and the PMOS transistor. When a specific address is applied and the address signal is activated to a logic high, the first transistor n3 is turned on so that the current having the voltage of the power supply voltage level precharged to the signal line is grounded. The signal line flows to make the signal line logic low, and is inverted through the inverting / latching means 200 so that the output node becomes logic high. Thereby, the normal cell is accessed. At this time, although the second transistor n2 is turned on, the direct current path transmitted through the fuse is stronger than the current flowing through the second transistor n2, so that the first transistor n3 The first transistor n3 is turned on by the address signal without turning the gate to a logic low. Therefore, the redundancy memory cell is not accessed, but the normal memory cell is accessed.

When the fuse is cut, the gate of the first transistor n3 is logic low by the second transistor n2 and the first transistor n3 is turned off. The signal line then remains at a logic high state and the output signal is at a logic low so that the redundancy cell is accessed. The floating preventing means 500 is provided to prevent the gate of the first transistor n3 from floating when the fuse is cut and the other address is accessed.

In the above circuit, when the floating prevention means and the second transistors n1 and n2 are made to have a sufficiently small width, even if the resistance of the fuse is large, the voltage control of the gate terminal of the nMOS transistor n3 is sufficient. It is possible to lay out the fuse narrowly so that it is possible. Therefore, damage to the device due to laser power can be reduced during fuse cutting.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, since the fuse controls the gate stage of the NMOS transistor, the fuse can be laid out smaller than the conventional width, so that the laser power can be reduced during the laser repair. Can reduce damage.

Claims (7)

Signal lines; Precharge means for precharging the signal line to a logic high; Inverting / latching means for inverting / latching the signal loaded on the signal line and outputting a control signal for selecting a normal cell or a redundancy cell; A first transistor having a source-drain path connected between any node of the signal line and a ground power supply terminal; A fuse connected between an address signal input terminal and a gate terminal of the first transistor; A second transistor for turning off the first transistor when the fuse is cut and an address signal is activated and input to the address signal input terminal; And Floating prevention means for preventing the gate terminal of the first transistor from floating when the fuse is cut and the address signal is inactivated. Repair device comprising a. The method of claim 1, The floating prevention means, Inverting means for inverting and outputting the address signal inputted to said address signal input terminal; A third transistor in which an output of the inverting means is applied to a gate and a source-drain path is formed between the gate terminal of the first transistor and the ground power supply terminal; Repair device comprising a. The method of claim 1, And the second transistor has a channel resistance greater than that of the fuse. The method of claim 1, And the address signal is a signal that is activated at a logic high level, and wherein the first, second, and third transistors are en-mo transistors, respectively. The method of claim 1, Wherein the fuse is a conductive film, and the fuse has a width controlling the gate voltage of the first transistor by the fuse faster than the second transistor when the address signal is input. The method of claim 1, The precharge means is a repair device, characterized in that the drain terminal and the gate terminal is connected to the power supply voltage and the source terminal is connected to the signal line to apply a power supply voltage to the signal line. The method of claim 1, The inversion / latch means, An inverter for selecting a normal cell and a redundancy cell by inverting a signal of the signal line; And A PMOS transistor having an output of the inverter input to a gate terminal and a source-drain path formed between a power voltage and the signal line Repair device comprising a.