KR100341518B1 - Lead frame for manufacturing semiconductor package - Google Patents
Lead frame for manufacturing semiconductor package Download PDFInfo
- Publication number
- KR100341518B1 KR100341518B1 KR1019990037198A KR19990037198A KR100341518B1 KR 100341518 B1 KR100341518 B1 KR 100341518B1 KR 1019990037198 A KR1019990037198 A KR 1019990037198A KR 19990037198 A KR19990037198 A KR 19990037198A KR 100341518 B1 KR100341518 B1 KR 100341518B1
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- KR
- South Korea
- Prior art keywords
- lead frame
- semiconductor package
- heat sink
- manufacturing
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 239000002390 adhesive tape Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000000465 moulding Methods 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 14
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 패키지 제조용 리드 프레임에 관한 것으로서, 방열판을 갖는 리드 프레임을 사용한 반도체 패키지 제조에 있어서, 리드 프레임에 일체로 성형되어 있는 타이바를 미연에 제거하여 제작함으로써, 종래에 제조공정중에 하나인 타이바 제거공정을 배제하여 제조공정을 줄일 수 있고, 리드프레임 제조원가를 절감할 수 있으며, 몰딩공정시 수지의 원할한 흐름로의 역할을 할 수 있도록 하여 몰딩 공정이 더욱 용이하게 이루어지도록 한 반도체 패키지 제조용 리드프레임을 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for manufacturing a semiconductor package. In the manufacture of a semiconductor package using a lead frame having a heat sink, a tie bar which is integrally formed on the lead frame is removed and manufactured so that the tie is one of the conventional manufacturing processes. Manufacturing process can be reduced by eliminating the bar removal process, reducing the manufacturing cost of leadframe, and making the molding process easier by making the role of smooth flow of resin during the molding process. To provide a lead frame.
Description
본 발명은 반도체패키지 제조용 리드 프레임에 관한 것으로서, 더욱 상세하게는 리드 프레임의 4곳 구석에 형성되어 있는 타이바를 제거하여, 몰딩 공정시에 수지의 용이한 공급이 이루어지게 하고, 리드 프레임의 타이바 제거공정이 배제되어 제조공정을 줄일 수 있도록 한 반도체패키지 제조용 리드 프레임에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for manufacturing a semiconductor package, and more particularly, to remove tie bars formed at four corners of the lead frame, so that resin can be easily supplied during the molding process, and the tie bars of the lead frame can be made. The present invention relates to a lead frame for manufacturing a semiconductor package in which a removal process is eliminated to reduce a manufacturing process.
통상적으로 반도체 칩으로 부터 발생되는 열을 효과적으로 방열시키기 위한 구조의 패키지가 개발중에 있으며, 그 중에 하나로서 다음과 같은 구조의 반도체 패키지가 있다.Generally, a package having a structure for effectively dissipating heat generated from a semiconductor chip is under development, and one of them is a semiconductor package having the following structure.
즉, 방열판을 갖는 리드 프레임(이하, 리드프레임이라함)을 사용한 종래의 반도체 패키지의 구조는 첨부한 도 4에 도시한 바와 같이, 히크싱트(16)의 상면 중앙부에 에폭시등과 같은 접착수단에 의하여 반도체 칩(20)이 부착되어 있고, 히트싱크(16)의 상면 테두리면에는 양면접착테이프(24)를 사이에 두고 리드(18)가 부착되어 있으며, 또한 상기 반도체 칩(20)의 본딩패드와 리드(18)간에 와이어가 본딩되어 있으며, 상기 히트싱크(16)의 저면을 제외한 칩(20)과 와이어(22)등이 수지(28)로 몰딩되어져 달성된 구조로 되어 있다.That is, the structure of a conventional semiconductor package using a lead frame (hereinafter referred to as a lead frame) having a heat sink is attached to an adhesive means such as epoxy at the center of the upper surface of the heat sink 16 as shown in FIG. The semiconductor chip 20 is attached thereto, and the lid 18 is attached to the upper edge of the heat sink 16 with the double-sided adhesive tape 24 interposed therebetween, and the bonding pad of the semiconductor chip 20 is provided. The wire is bonded between the lead and the lead 18, and the chip 20, the wire 22, and the like except for the bottom surface of the heat sink 16 are molded with the resin 28 to achieve the structure.
또한, 상기와 같은 반도체패키지에 적용된 종래의 리드 프레임(10b)은 첨부한 도 3에 도시한 바와 같이, 안쪽 사방으로 다수의 리드(18)가 일체로 성형되어있고, 각 4곳의 코너에는 타이바(12)가 일체로 성형되어 있으며, 상기 다수의 리드(18)의 흔들림을 방지하기 위하여 리드들의 중앙부위에는 각 리드(18)들이 견고히 고정되도록 한 리드 락 테이프(14)가 부착되어져 있다.In addition, in the conventional lead frame 10b applied to the semiconductor package as described above, as shown in FIG. 3, a plurality of leads 18 are integrally formed in all four directions, and each of four corners has a tie. The bar 12 is integrally molded, and a lead lock tape 14 is attached to the centers of the leads to firmly fix the leads 18 to prevent shaking of the plurality of leads 18.
한편, 상기 타이바(12)는 통상적으로 반도체 칩(20)이 올려지는 다이패드와 일체로 성형되어 다이패드를 견고히 지지해주는 역할을 하는 부분으로서, 상술한 바와 같이 방열판을 갖는 리드프레임을 사용하여 제조된 반도체패키지에는 리드 프레임(10b)에 형성되어 있는 타이바(12)가 쓸모없는 부분이 된다.On the other hand, the tie bar 12 is formed integrally with the die pad on which the semiconductor chip 20 is mounted, which serves to firmly support the die pad, and uses a lead frame having a heat sink as described above. In the manufactured semiconductor package, the tie bar 12 formed in the lead frame 10b becomes a useless part.
그 이유는 첨부한 도 4에 도시한 바와 같이 반도체 칩(20)은 히트싱크(16)상에 접착수단으로 부착되어 고정된 상태이기 때문에 타이바(12)는 오히려 몰딩공정시 수지의 흐름을 차단하고, 리드프레임의 무게 즉, 반도체패키지의 무게를 증가시키는 요인이 되어 쓸모없는 부분이 된다.The reason for this is that the semiconductor chip 20 is attached to the heat sink 16 by an adhesive means and fixed as shown in FIG. 4, so that the tie bar 12 blocks the flow of the resin during the molding process. In addition, the weight of the lead frame, that is, the weight of the semiconductor package is increased and becomes a useless part.
따라서, 상기 방열판을 갖는 리드프레임을 사용한 반도체 패키지 제조 공정중에 상기 타이바(12)를 툴링펀치(Tooling Punch)로 제거하는 공정이 추가되어 작업성 및 제조원가의 상승요인이 되는 점이 있었다.Therefore, during the semiconductor package manufacturing process using the lead frame having the heat sink, a step of removing the tie bar 12 with a tooling punch was added, thereby increasing workability and manufacturing cost.
따라서, 본 발명은 상기와 같은 점을 해결하기 위하여 안출한 것으로서, 방열판을 갖는 리드 프레임을 사용한 반도체 패키지 제조에 있어서, 리드 프레임에 일체로 성형되어 있는 타이바를 미연에 제거하여 제작함으로써, 종래에 제조공정중에 하나인 타이바 제거공정을 배제하여 제조공정을 줄일 수 있고, 리드프레임 제조원가를 절감할 수 있으며, 몰딩공정시 수지의 원할한 흐름로의 역할을 할 수 있도록 하여 몰딩 공정이 더욱 용이하게 이루어지도록 한 반도체 패키지 제조용 리드프레임을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made in order to solve the above problems, and in the manufacture of a semiconductor package using a lead frame having a heat sink, the present invention is conventionally manufactured by removing a tie bar formed integrally with the lead frame in advance. By eliminating the tie bar removal process, one of the processes, the manufacturing process can be reduced, the lead frame manufacturing cost can be reduced, and the molding process can be made more easily by allowing the resin to flow smoothly during the molding process. It is an object of the present invention to provide a lead frame for manufacturing a semiconductor package.
도 1은 본 발명에 따른 리드 프레임을 나타내는 평면도,1 is a plan view showing a lead frame according to the present invention,
도 2는 본 발명에 따른 리드 프레임을 이용하여 제조된 반도체 패키지를 나타내는 도 1의 B-B선 단면도,2 is a cross-sectional view taken along line B-B of FIG. 1 showing a semiconductor package manufactured using a lead frame according to the present invention;
도 3은 종래의 리드 프레임을 나타내는 평면도,3 is a plan view showing a conventional lead frame,
도 4는 종래의 리드프레임을 이용하여 제조된 반도체 패키지를 나타내는 도 3의 A-A선 단면도.4 is a cross-sectional view taken along the line A-A of FIG. 3 showing a semiconductor package manufactured using a conventional lead frame.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
10a,10b : 리드 프레임 12 : 타이바10a, 10b: lead frame 12: tie bar
14 : 리드 락 테이프 16 : 히트 싱크14: lead lock tape 16: heat sink
18 : 리드 20 : 칩18: Lead 20: Chip
22 : 와이어 24 : 양면접착테이프22: wire 24: double sided adhesive tape
28 : 수지28: resin
이하 첨부도면을 참조로 더욱 상세하게 설명하면 다음과 같다.Hereinafter, described in more detail with reference to the accompanying drawings.
본 발명은 히트싱크(16)와, 히크싱크(16) 상면 중앙부에 접착수단으로 부착되는 칩(20)과, 상기 히트싱크(16)의 상면 테두리면에 양면접착테이프(24)를 사이에 두고 부착되는 리드프레임(10a)의 리드(18)와, 상기 칩(20)의 본딩패드와 리드(18)를 연결하는 와이어(22)와, 상기 히트싱크(16)의 저면을 제외하고 상기 칩(20)과 와이어(22)와 리드(18)를 커버하며 몰딩되는 수지(28)로 이루어진 구조의 반도체 패키지 제조용 리드 프레임에 있어서,According to the present invention, the heat sink 16, the chip 20 attached to the center of the upper surface of the heat sink 16 by adhesive means, and the double-sided adhesive tape 24 are disposed on the upper edge of the heat sink 16. The lead 18 of the lead frame 10a to be attached, the wire 22 connecting the bonding pad and the lead 18 of the chip 20 to each other, and the bottom surface of the heat sink 16 are removed. In the lead frame for manufacturing a semiconductor package having a structure composed of a resin 28 which is molded while covering the wire 20 and the lead 22 and the lead 18,
상기 리드프레임(10a)은 안쪽 네 코너에 형성되는 동시에 사방 안쪽으로 형성된 다수의 리드(18) 사이에 위치하게 되는 타이바(12)를 제거하여서 제작된 것을 특징으로 한다.The lead frame 10a is formed by removing the tie bars 12 formed at four inner corners and located between the plurality of leads 18 formed in all directions inward.
여기서 본 발명을 실시예로서, 첨부한 도 1 내지 도 2를 참조로 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention will be described in more detail with reference to the attached drawings 1 to 2 as examples.
첨부한 도 1은 본 발명에 따른 리드프레임(10a)을 나타내는 평면도로서, 상기 리드 프레임(10a)은 대략 사각을 이루는 형상으로 되어 있고, 외곽을 이루는 사이드 레일에서 사방 안쪽으로 다수의 리드(18)가 등간격을 이루며 일체로 성형되어있다.1 is a plan view illustrating a lead frame 10a according to the present invention, wherein the lead frame 10a has a substantially quadrangular shape and has a plurality of leads 18 inward and outward from an outer side rail. It is molded integrally at equal intervals.
또한, 상기 다수의 리드(18) 중간 부위에는 리드 락 테이프(14)가 부착되어, 다수의 리드(18)가 흔들리지 않으며 서로 수평상태를 유지하여 견고히 고정되어진 상태가 된다.In addition, the lead lock tape 14 is attached to the middle portion of the plurality of leads 18 so that the plurality of leads 18 do not shake and remain horizontally fixed to each other.
물론, 상술한 바와 같은 종래의 리드 프레임(10b)으로부터 타이바(12)가 제거된 상태로 제작된 것이므로, 타이바(12)가 제거된 부분은 빈 공간으로 남아 있는 상태가 된다.Of course, since the tie bar 12 is manufactured in a state where the tie bar 12 is removed from the conventional lead frame 10b as described above, the portion where the tie bar 12 is removed is left in an empty space.
여기서, 본 발명의 리드프레임(10a)을 이용하여 반도체 패키지를 제조하는 상태를 첨부한 도 4를 참조로 설명하면 다음과 같다.Herein, a state in which a semiconductor package is manufactured using the lead frame 10a of the present invention will be described with reference to FIG. 4.
상기 반도체패키지는 칩(20)에서 발생하는 열의 방출 효과를 최대로 얻기 위하여 금속재의 히트싱크(16) 저면이 노출되는 패키지로서, 상기 히트싱크(16)의 상면 중앙부에 반도체 칩(20)을 접착수단으로 부착하는 단계와, 상기 히트싱크(16)의 상면 테두리면과 상기 다수의 리드(18)를 양면접착테이프(24)를 중간에 위치시켜 부착하는 단계와, 상기 칩(20)의 본딩패드와 리드(18)간을 와이어(22)로 본딩하는 단계와, 상기 히트싱크(16)의 저면을 제외하고 칩(20)과 와이어(22)와 리드(18)등을 수지(28)로 몰딩하는 단계등으로 이루어진 패키지이며, 종래에는 상기 반도체 패키지의 제조공정 전에 또 하나의 공정으로서 타이바를 인위적으로 툴링펀치로 제거하는 공정이 진행되어왔다.The semiconductor package is a package in which the bottom surface of the heat sink 16 of the metal material is exposed in order to maximize the heat dissipation effect generated by the chip 20, and the semiconductor chip 20 is adhered to the center of the upper surface of the heat sink 16. Attaching by means, attaching the upper edge of the heat sink 16 and the plurality of leads 18 by placing the double-sided adhesive tape 24 in the middle, and bonding pads of the chip 20. Bonding the wires 22 and the leads 18 to the wires 22 and molding the chip 20, the wires 22, the leads 18, etc., with the resin 28 except for the bottom surface of the heat sink 16. It is a package consisting of the steps, etc. In the past, a step of artificially removing the tie bar with a tooling punch as another step before the manufacturing process of the semiconductor package has been in progress.
여기서, 상기 반도체 칩(20)은 히트싱크(16) 위에 접착수단으로 부착되어 고정되어진 상태이기 때문에, 상기와 같은 반도체패키지에는 반도체 칩이 실장되는다이패드를 잡아주는 타이바(12)가 필요없게 되며, 따라서 상기 반도체패기지에는 본 발명에 따른 리드 프레임(10a)의 적용이 바람직하다.Here, since the semiconductor chip 20 is fixed to the heat sink 16 by being attached to the heat sink 16, the semiconductor package 20 does not need the tie bar 12 for holding the die pad on which the semiconductor chip is mounted. Therefore, the application of the lead frame 10a according to the present invention is preferable to the semiconductor package.
특히, 본 발명의 리드프레임(10a)을 적용하여 상기 반도체 패키지를 제조시에, 몰딩공정에서 상기 타이바(12)가 제거된 부분은 몰딩 컴파운드 수지(28)의 흐름 경로가 되어 수지의 흐름이 원할하게 이루어지게 되고, 따라서 몰딩공정이 더욱 원할히 진행됨에 따라 몰딩상태가 좋아지게 된다.In particular, when manufacturing the semiconductor package by applying the lead frame 10a of the present invention, the portion from which the tie bar 12 is removed in the molding process becomes a flow path of the molding compound resin 28 so that the flow of the resin It is made smoothly, and thus the molding state is improved as the molding process proceeds more smoothly.
이상에서 본 바와 같이 본 발명에 따른 반도체 패키지 제조용 리드프레임에 의하면, 종래의 리드프레임으로부터 타이바를 제거하여 제작함으로써, 몰딩공정시 타이바의 제거부분으로 몰딩 컴파운드 수지의 원할한 흐름이 유도되어, 몰딩공정의 원할한 진행과 그 몰딩상태의 품질향상을 제공할 수 있고, 또한 종래에 타이바를 제거하는 공정이 배제되어 반도체 패키지의 제조공정이 줄어들고 그에따른 제조비용을 절감할 수 있는 장점이 있다.As described above, according to the lead frame for manufacturing a semiconductor package according to the present invention, by removing a tie bar from a conventional lead frame, a smooth flow of the molding compound resin is induced to the removal portion of the tie bar during the molding process, thereby molding It is possible to provide a smooth progress of the process and to improve the quality of the molding state, and also to eliminate the tie bar in the prior art has the advantage of reducing the manufacturing process of the semiconductor package and thereby reduce the manufacturing cost.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990037198A KR100341518B1 (en) | 1999-09-02 | 1999-09-02 | Lead frame for manufacturing semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990037198A KR100341518B1 (en) | 1999-09-02 | 1999-09-02 | Lead frame for manufacturing semiconductor package |
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| KR100698247B1 (en) * | 2005-03-17 | 2007-03-21 | 엘지마이크론 주식회사 | Lead frame |
| JP2008532267A (en) | 2005-02-23 | 2008-08-14 | エルジーマイクロン リミテッド | Lead frame |
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