KR100338949B1 - Structure of metal line in semiconductor package - Google Patents
Structure of metal line in semiconductor package Download PDFInfo
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- KR100338949B1 KR100338949B1 KR1019990057501A KR19990057501A KR100338949B1 KR 100338949 B1 KR100338949 B1 KR 100338949B1 KR 1019990057501 A KR1019990057501 A KR 1019990057501A KR 19990057501 A KR19990057501 A KR 19990057501A KR 100338949 B1 KR100338949 B1 KR 100338949B1
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0235—Shape of the redistribution layers
- H01L2224/02351—Shape of the redistribution layers comprising interlocking features
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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Abstract
본 발명은 반도체 패키지의 배선 구조에 관한 것으로서, 본 발명은 웨이퍼(51)의 칩패드(53)와 솔더볼(61)이 금속배선(57)에 의해 전기적으로 연결되고, 상기 금속배선(57)에는 열응력 및 이로 인한 변형을 흡수하여 완충 역할을 수행하도록 수평 상의 같은 층 상에서 절곡되는 요철부(58a)(58b)(58c)가 적어도 하나 이상 형성되도록 구성됨으로써 상기 금속배선(57)에 발생되는 열응력 및 이로 인한 변형이 금속배선(57)에 의해 자체 흡수되므로 상기 금속배선(57)의 파괴가 방지되어 금속배선(57)에 대한 신뢰성이 확보되고, 이에 따라 패키지 전체의 신뢰성이 향상되도록 한 것이다.The present invention relates to a wiring structure of a semiconductor package. The present invention relates to a chip pad 53 of a wafer 51 and a solder ball 61 electrically connected to each other by a metal wiring 57. Heat generated in the metallization 57 by forming at least one uneven portion 58a, 58b, 58c which is bent on the same layer in the horizontal to absorb the thermal stress and the resulting deformation to play a buffer role. Since the stress and the deformation thereof are self-absorbed by the metal wiring 57, the breakage of the metal wiring 57 is prevented to ensure the reliability of the metal wiring 57, thereby improving the reliability of the entire package. .
Description
본 발명은 반도체 패키지의 배선 구조에 관한 것으로서, 특히 웨이퍼의 칩패드와 솔더볼을 전기적으로 연결하는 금속배선에 요철부가 형성된 반도체 패키지의 배선 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor package, and more particularly to a wiring structure of a semiconductor package in which an uneven portion is formed in a metal wiring electrically connecting a chip pad and a solder ball of a wafer.
도 1은 종래 기술에 따른 반도체 패키지의 배선 구조가 도시된 단면도이고, 도 2는 종래 기술에 따른 배선 구조가 도시된 요부 평면도이다.1 is a cross-sectional view illustrating a wiring structure of a semiconductor package according to the prior art, and FIG. 2 is a plan view of a main part of the wiring structure according to the prior art.
상기한 도 1 및 도 2를 참조하여 종래 기술에 따른 반도체 패키지의 배선 구조에 대해 설명하면 다음과 같다.A wiring structure of a semiconductor package according to the prior art will be described with reference to FIGS. 1 and 2 as follows.
먼저, 웨이퍼(1)의 상면에 복수개의 칩패드(3)가 형성되고, 상기 웨이퍼(1)의 상측에는 상기 칩패드(3)의 상면이 노출되도록 절연유전층(5)이 형성된다.First, a plurality of chip pads 3 are formed on an upper surface of the wafer 1, and an insulating dielectric layer 5 is formed on the upper side of the wafer 1 so that the upper surface of the chip pads 3 is exposed.
또한, 상기 절연유전층(5)의 상측에는 상기 칩패드(3)에 일단이 연결되도록 금속배선(7)이 형성되고, 이렇게 형성된 금속배선(7)은 대부분 단순한 직선 형상을 갖게 되거나 상호간의 거리 유지를 위해 특정 부분이 일정 각도로 꺾인 형상을 갖게 된다.In addition, a metal wiring 7 is formed at an upper side of the insulating dielectric layer 5 so that one end is connected to the chip pad 3, and the metal wiring 7 thus formed has a simple straight line shape or maintains a mutual distance. For this purpose, a certain part is bent at an angle.
또한, 상기 절연유전층(5) 및 금속배선(7)의 상측에는 상기 금속배선(7)의 타단 상면이 노출되도록 솔더마스크층(9)이 형성되고, 상기 금속배선(7)의 타단 상면에는 외부단자로서의 역할을 수행하는 솔더볼(11)이 접합된다.In addition, a solder mask layer 9 is formed on the insulating dielectric layer 5 and the metal wiring 7 so that the other end surface of the metal wiring 7 is exposed, and an external surface is formed on the other end of the metal wiring 7. The solder ball 11 which serves as a terminal is joined.
그런데, 상기와 같은 종래의 반도체 패키지의 배선 구조에서는 패키지에 열을 가하는 신뢰성 시험을 할 경우 웨이퍼(1)와 금속배선(7) 사이, 그리고 웨이퍼(1)와 솔더볼(11) 사이에 형성된 절연유전층(5)과 솔더마스크(9)의 열팽창 특성의 차이로 인해 웨이퍼(1), 금속배선(7), 솔더볼(11)에 큰 열응력이 발생되고, 이러한 열응력에 의해 상기 웨이퍼(1), 금속배선(7), 솔더볼(11)이 변형되기도 한다.However, in the wiring structure of the conventional semiconductor package as described above, the insulation dielectric layer formed between the wafer 1 and the metal wiring 7 and between the wafer 1 and the solder ball 11 when a reliability test is applied to heat the package. Due to the difference in thermal expansion characteristics of the solder mask 9 and the solder mask 9, a large thermal stress is generated in the wafer 1, the metal wiring 7, and the solder ball 11, and the thermal stress causes the wafer 1, The metal wiring 7 and the solder ball 11 may be deformed.
그러나, 상기한 종래의 배선 구조는 금속배선(7)에 열응력에 의한 변형을 완충시킬만한 구조를 구비하고 있지 않기 때문에 상기 금속배선(7)이 열응력에 의해 변형 및 파괴되는 문제점이 있었다.However, the above-described conventional wiring structure has a problem that the metal wiring 7 is deformed and destroyed by thermal stress because the metal wiring 7 does not have a structure that can buffer deformation due to thermal stress.
특히, 상기한 종래의 배선 구조는 웨이퍼 레벨 패키지 및 플립칩과 같이 박막 필름 공정을 사용하여 패드 재배치를 수행하는 패키지에 적용될 경우 상기한 패키지의 금속배선(7) 두께가 수 ㎛이하로 통상적인 패키지에 비해 매우 얇기 때문에 상기 금속배선(7)의 파괴 현상이 심화되는 문제점이 있었다.In particular, when the conventional wiring structure is applied to a package for pad repositioning using a thin film process, such as a wafer level package and a flip chip, the thickness of the metal wiring 7 of the above-described package is several micrometers or less. Since it is very thin compared to the problem that the fracture phenomenon of the metal wiring 7 is intensified.
상기한 바와 같은 문제점을 감안하여 안출한 본 발명의 목적은, 웨이퍼의 칩패드와 솔더볼을 전기적으로 연결하기 위한 금속배선의 형상을 변경하여 상기 금속배선에 의해 금속배선에 발생되는 열응력 및 변형이 자체 흡수되고, 이로써 상기 금속배선의 파괴가 방지되어 금속배선에 대한 신뢰성이 확보되도록 하는 반도체 패키지의 배선 구조를 제공함에 있다.The object of the present invention devised in view of the above problems is to change the shape of the metal wiring for electrically connecting the chip pad and the solder ball of the wafer, thereby reducing the thermal stress and deformation generated in the metal wiring by the metal wiring. The present invention provides a wiring structure of a semiconductor package that is self-absorbed and thereby prevents destruction of the metal wiring to ensure reliability of the metal wiring.
도 1은 종래 기술에 따른 반도체 패키지의 배선 구조가 도시된 단면도,1 is a cross-sectional view showing a wiring structure of a semiconductor package according to the prior art;
도 2는 종래 기술에 따른 배선 구조가 도시된 요부 평면도,2 is a plan view showing main parts of a wiring structure according to the prior art;
도 3은 본 발명의 제 1실시 예에 따른 반도체 패키지의 배선 구조가 도시된 단면도,3 is a cross-sectional view showing a wiring structure of a semiconductor package according to a first embodiment of the present invention;
도 4는 본 발명의 제 2실시 예에 따른 반도체 패키지의 배선 구조가 도시된 요부 평면도이다.4 is a plan view illustrating main parts of the wiring structure of the semiconductor package according to the second exemplary embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
51 : 웨이퍼 53 : 칩패드51: wafer 53: chip pad
55 : 절연유전층 57 : 금속배선55 dielectric insulating layer 57 metal wiring
58a, 58b, 58c : 요철부 59 : 솔더마스크층58a, 58b, 58c: Uneven portion 59: Solder mask layer
61 : 솔더볼61: solder ball
상기한 바와 같은 본 발명의 목적을 달성하기 위하여, 웨이퍼의 칩패드와 솔더볼이 금속배선에 의해 전기적으로 연결된 반도체 패키지의 배선 구조에 있어서, 상기 금속배선에는 열응력 및 이로 인한 변형을 흡수하여 완충 역할을 수행하도록 수평 상의 같은 층 상에서 절곡되는 요철부가 적어도 하나 이상 형성된 것을 특징으로 하는 반도체 패키지의 배선 구조가 제공된다.In order to achieve the object of the present invention as described above, in the wiring structure of the semiconductor package in which the chip pad and the solder ball of the wafer are electrically connected by the metal wiring, the metal wiring absorbs the thermal stress and the resulting deformation to act as a buffer. The wiring structure of the semiconductor package is provided, characterized in that at least one uneven portion bent on the same layer on the horizontal to form a.
이하, 본 발명의 실시 예를 첨부한 도면을 참조하여 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명의 제 1실시 예에 따른 반도체 패키지의 배선 구조가 도시된 단면도이고, 도 4는 본 발명의 제 2실시 예에 따른 반도체 패키지의 배선 구조가 도시된 요부 평면도이다.3 is a cross-sectional view illustrating a wiring structure of a semiconductor package according to a first embodiment of the present invention, and FIG. 4 is a plan view of a main part of the wiring structure of a semiconductor package according to a second embodiment of the present invention.
상기한 도 3 및 도 4를 참조하면, 본 발명에 따른 반도체 패키지의 배선 구조는 복수개의 칩패드(53)가 형성된 웨이퍼(51)와, 상기 칩패드(53)의 상면이 노출되도록 웨이퍼(51) 상측에 형성된 절연유전층(55)과, 상기 칩패드(53)에 일단이 연결되는 동시에 중간에 요철부(58a)(58b)(58c)가 형성되도록 상기 절연유전층(55)의 상측에 형성된 금속배선(57)과, 상기 금속배선(57)의 타단 상면이 노출되도록 상기 절연유전층(55) 및 금속배선(57)의 상측에 형성된 솔더마스크층(59)과, 상기 금속배선(57)의 타단 상면에 접합되어 외부단자 역할을 하는 솔더볼(61)로 구성된다.3 and 4, the wiring structure of the semiconductor package according to the present invention includes a wafer 51 having a plurality of chip pads 53 formed thereon, and a wafer 51 so as to expose an upper surface of the chip pads 53. A metal formed on the dielectric dielectric layer 55 so that one end is connected to the chip pad 53 and an uneven portion 58a, 58b, 58c is formed in the middle thereof. A solder mask layer 59 formed on the insulating dielectric layer 55 and the metal wiring 57 so as to expose the wiring 57, the other end surface of the metal wiring 57, and the other end of the metal wiring 57. It is composed of a solder ball 61 bonded to the upper surface to serve as an external terminal.
여기서, 상기 요철부(58a)(58b)(58c)는 도 3에 도시된 바와 같이 절연유전층(55)의 높이를 이용하여 수직 방향으로 형성될 수도 있고, 도 4에 도시된 바와 같이 절연유전층(55)의 상면에서 수평 방향으로 형성될 수도 있다.즉, 상기 요철부(58a)(58b)(58c)는 수평 상의 같은 층 상에서 절곡 형성되는 것이다.Here, the uneven parts 58a, 58b, 58c may be formed in a vertical direction by using the height of the insulating dielectric layer 55 as shown in FIG. 3, and as shown in FIG. 4, the insulating dielectric layer ( It may be formed in the horizontal direction on the upper surface of 55. That is, the uneven parts 58a, 58b, 58c are bent on the same layer on the horizontal.
또한, 상기 요철부(58a)(58b)(58c)는 'ㄷ' 또는 'ㄱ' 형태로서, 상기 금속배선(57)과 만나는 이음면이 경사지게 형성되는 것이 바람직하다.In addition, the uneven parts 58a, 58b, 58c may have a 'c' or 'a' shape, and the joint surface that meets the metal wiring 57 may be inclined.
상기와 같이 구성된 본 발명에 의한 반도체 패키지의 배선 구조 중 금속배선(57)의 요철부(58a)(58b)(58c)가 수직 방향으로 형성된 구조를 만들기 위해서는, 웨이퍼(51)의 상면에 절연유전층(55)을 형성한 후 칩패드(53)의 상면이 노출되도록 에칭을 통해 상기 절연유전층(55)을 제거할 때 상기 금속배선(57)의 요철부(58a)가 형성될 부분도 함께 제거한다.In order to make a structure in which the uneven parts 58a, 58b, 58c of the metal wiring 57 are formed in the vertical direction among the wiring structures of the semiconductor package according to the present invention configured as described above, an insulating dielectric layer is formed on the upper surface of the wafer 51. When the insulating dielectric layer 55 is removed by etching so that the top surface of the chip pad 53 is formed after the formation of the 55, the portion where the uneven portion 58a of the metal wiring 57 is to be formed is also removed. .
상기와 같이 절연유전층(55)을 형성한 후 그 위에 금속을 도금 또는 코팅하여 금속배선(57)을 형성하면 상기 절연유전층(55)의 제거된 부분에 의해 중간 부분에 수직 방향의 요철부(58a)가 형성된 금속배선(57)을 얻을 수 있게 된다.After the insulating dielectric layer 55 is formed as described above, when the metal wiring 57 is formed by plating or coating the metal thereon, the uneven portion 58a in the vertical direction is perpendicular to the middle portion by the removed portion of the dielectric dielectric layer 55. Can be obtained.
한편, 본 발명에 의한 반도체 패키지의 배선 구조 중 금속배선(57)의 요철부(58b)(58c)가 수평 방향으로 형성된 구조를 만들기 위해서는, 웨이퍼(51)의 상면에 칩패드(53)의 상면이 노출되도록 절연유전층(55)을 형성한 후 상기 절연유전층(55)에 금속막을 도금 또는 코팅하고 상기 금속배선(57)의 패턴에 따라 금속막을 에칭할 때 금속배선(57)의 중간 부분에 수평 방향의 요철부(58a)(58c)가 형성되도록 에칭하면 된다.On the other hand, in order to make the structure in which the uneven parts 58b and 58c of the metal wiring 57 are formed in the horizontal direction among the wiring structures of the semiconductor package according to the present invention, the upper surface of the chip pad 53 is formed on the upper surface of the wafer 51. After forming the dielectric dielectric layer 55 so as to be exposed, the metal film is plated or coated on the dielectric dielectric layer 55, and when the metal layer is etched according to the pattern of the metallic wiring 57, it is horizontal to the middle portion of the metal wiring 57. The etching may be performed such that the uneven portions 58a and 58c in the direction are formed.
상기한 바와 같이 금속배선(57)의 중간 부분에 수직 또는 수평 방향으로의 요철부(58a)(58b)(58c)가 형성되면 열팽창 특성의 차이로 인한 열응력에 의해 웨이퍼(51)의 칩패드(53)와 솔더볼(61) 사이에서 발생된 변형이 상기 요철부(58a)(58b)(58c)에 의해 흡수될 수 있게 되어 요철부(58a)(58b)(58c)가 열응력 및 변형에 대한 완충역할을 하게 된다.As described above, when the uneven parts 58a, 58b, 58c are formed in the middle portion of the metal wiring 57 in the vertical or horizontal direction, the chip pad of the wafer 51 is caused by thermal stress due to a difference in thermal expansion characteristics. Deformation generated between the 53 and the solder ball 61 can be absorbed by the uneven portions 58a, 58b, 58c so that the uneven portions 58a, 58b, 58c are affected by thermal stress and deformation. It acts as a buffer for
이상에서 설명한 바와 같이 본 발명에 따른 반도체 패키지의 배선 구조는, 금속배선(57)에 형성된 요철부(58a)(58b)(58c)가 완충역할을 수행하여 상기 금속배선(57)에 발생되는 열응력 및 이로 인한 변형이 자체 흡수되므로 금속배선(57)의 파괴가 방지되어 상기 금속배선(57)에 대한 신뢰성이 확보되고, 이에 따라 패키지 전체의 신뢰성이 향상되는 이점이 있다.As described above, in the wiring structure of the semiconductor package according to the present invention, heat generated in the metal wiring 57 by the uneven parts 58a, 58b, 58c formed in the metal wiring 57 performs a buffering role. Since the stress and the deformation thereof are absorbed by itself, the destruction of the metal wiring 57 is prevented, so that the reliability of the metal wiring 57 is secured, thereby improving the reliability of the entire package.
특히, 본 발명은 웨이퍼 레벨 패키지 및 플립칩, 멀티칩 모듈과 같이 박막 필름을 이용해 패드 재배치를 수행하여 금속배선(57)의 두께 수 ㎛이하로 매우 얇은 차세대 패키지에 매우 유용하게 적용될 수 있는 이점이 있다.In particular, the present invention has the advantage that it can be very usefully applied to a very thin next-generation package with a thickness of several micrometers or less of the metallization 57 by performing pad repositioning using a thin film such as a wafer level package, a flip chip, and a multichip module. have.
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| US9275925B2 (en) | 2013-03-12 | 2016-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for an improved interconnect structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH08203942A (en) * | 1995-01-27 | 1996-08-09 | Nec Corp | Semiconductor device and manufacturing method thereof |
| JPH0945691A (en) * | 1995-07-27 | 1997-02-14 | Oki Electric Ind Co Ltd | Solder bump for chip component and its manufacture |
| JPH10135270A (en) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | Semiconductor device and manufacturing method thereof |
| US5977641A (en) * | 1997-05-14 | 1999-11-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH08203942A (en) * | 1995-01-27 | 1996-08-09 | Nec Corp | Semiconductor device and manufacturing method thereof |
| JPH0945691A (en) * | 1995-07-27 | 1997-02-14 | Oki Electric Ind Co Ltd | Solder bump for chip component and its manufacture |
| JPH10135270A (en) * | 1996-10-31 | 1998-05-22 | Casio Comput Co Ltd | Semiconductor device and manufacturing method thereof |
| US5977641A (en) * | 1997-05-14 | 1999-11-02 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
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