KR100334391B1 - Capacitor Formation Method of Semiconductor Device - Google Patents
Capacitor Formation Method of Semiconductor Device Download PDFInfo
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- KR100334391B1 KR100334391B1 KR1019980061908A KR19980061908A KR100334391B1 KR 100334391 B1 KR100334391 B1 KR 100334391B1 KR 1019980061908 A KR1019980061908 A KR 1019980061908A KR 19980061908 A KR19980061908 A KR 19980061908A KR 100334391 B1 KR100334391 B1 KR 100334391B1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 title claims abstract description 25
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000010408 film Substances 0.000 claims description 76
- 238000010438 heat treatment Methods 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 1
- 150000003608 titanium Chemical class 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 25
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로, 하부전극 상부에 고유전체막을 저온에서 증착가능한 PVD방법을 사용하여 증착한 다음, 전면식각공정을 실시하여 상기 고유전체막의 단차피복성을 우수하게 형성함으로써 캐패시터의 특성을 향상시키고, 그에 따른 소자의 특성 및 수율을 향상시키는 기술에 관한 것이다.The present invention relates to a method for forming a capacitor of a semiconductor device, by depositing a high dielectric film on the lower electrode by using a PVD method capable of depositing at a low temperature, and then performing an entire surface etching process to form an excellent step coverage of the high dielectric film The present invention relates to a technique for improving the characteristics of a capacitor and thereby improving the characteristics and yield of a device.
Description
본 발명은 반도체소자의 캐패시터 형성방법에 관한 것으로서, 특히 고유전체막을 저온에서 물리기상증착(physical vapor deposition, 이하 PVD 라 함)방법으로 증착한 다음, 전면식각공정을 실시하여 단차피복성이 우수한 유전체막을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device. In particular, a dielectric film having high step coverage is formed by depositing a high-k dielectric film by physical vapor deposition (PVD) at a low temperature, and then performing an entire surface etching process. A method of forming a film.
일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the high integration of semiconductor devices increases, a fixed capacitance of a capacitor is required. In order to solve this problem, a method of using a material having a high dielectric constant of a capacitor, reducing the thickness of a dielectric film, or increasing the surface area of a charge storage electrode has emerged. In order to solve this problem, attempts have been made to apply a material having a high dielectric constant.
또한, 상기와 같은 강유전체막들은 상온에서 유전상수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로 박막화하여 전원이 꺼진 상태에서도 데이타를 기억하는 비휘발성(nonvolatile)메모리인 FeRAM 소자 개발에도 적용되고 있다.In addition, such ferroelectric films are nonvolatile memories that store data even when the power is turned off by thinning them into ferroelectrics having dielectric constants of several hundreds to thousands at room temperature and having two stable polarization states. It is also applied to the development of FeRAM devices.
최근 반도체 메모리 소자의 고용량화 요구가 높아짐에 보다 작은 면적에 많은 정보를 저장하는 소자의 개발이 진행되어 오고 있다. 따라서 지금까지는 정보 저장소 역할을 하는 메모리 셀의 캐패시터 물질은 산화막 또는 질화막을 사용해 왔으나 이들 물질은 유전율이 낮아 보다 고집적의 메모리 소자의 캐패시터 재료로는 BST((Ba1-xSrx)TiO3)와 같은 고유전 물질을 채용해야 한다. 그런데, BST와 같은 새로운 물질 역시 평면상으로는 기가급 이상의 고집적 소자의 캐패시턴스를 충분히 확보할 수 없기 때문에 일반적으로 스택 구조와 같은 스토리지 노드위에 입체적으로 증착해야 한다.Recently, as the demand for higher capacity of semiconductor memory devices increases, development of devices for storing a large amount of information in a smaller area has been in progress. Thus, until now, capacitor materials of memory cells, which serve as information repositories, have used oxide films or nitride films. However, these materials have low dielectric constants, and thus, BST ((Ba 1-x Sr x ) TiO 3 ) and The same high dielectric material should be employed. However, new materials such as BST also need to be deposited three-dimensionally on storage nodes, such as stack structures, because they cannot secure enough capacitance in gigascale or higher integrated devices.
이하, 첨부된 도면을 참고로 하여 종래기술에 따른 반도체소자의 캐패시터 형성방법을 설명하기로 한다.Hereinafter, a method of forming a capacitor of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1 은 종래기술에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of forming a capacitor of a semiconductor device according to the prior art.
먼저, 소정의 하부구조물이 형성되어 있는 반도체기판(11) 상부에 저장전극 콘택으로 예정되는 접합영역(12)을 노출시키는 저장전극 콘택홀(도시안됨)이 구비되는 층간절연막(13)을 형성한다.First, an interlayer insulating layer 13 having a storage electrode contact hole (not shown) that exposes a junction region 12, which is intended as a storage electrode contact, is formed on the semiconductor substrate 11 on which a predetermined substructure is formed. .
다음, 상기 층간절연막(13) 상부에 상기 저장전극 콘택홀을 매립하는 다결정실리콘층을 형성한다.Next, a polysilicon layer is formed on the interlayer insulating layer 13 to fill the storage electrode contact hole.
그 다음, 상기 다결정실리콘층을 전면식각 또는 화학적 기계적 연마 (chemical mechanical polishing, 이하 CMP 라 함)공정으로 제거하여 상기 저장전극 콘택홀을 통하여 상기 접합영역(12)과 접속되는 저장전극 콘택플러그(14)를 형성한다.Next, the polysilicon layer is removed by a full surface etching or chemical mechanical polishing (CMP) process to connect the storage electrode contact plug 14 to the junction region 12 through the storage electrode contact hole. ).
다음, 전체표면 상부에 티타늄막(15)과 질화티타늄막(16) 적층구조의 확산방지막을 형성한다.Next, a diffusion barrier film having a stacked structure of the titanium film 15 and the titanium nitride film 16 is formed on the entire surface.
그 다음, 상기 질화티타늄막(16) 상부에 하부전극용 도전층을 형성한다. 상기 하부전극용 도전층은 Pt막으로 형성한다.Next, a conductive layer for a lower electrode is formed on the titanium nitride film 16. The lower electrode conductive layer is formed of a Pt film.
다음, 상기 하부전극용 도전층과 확산방지막을 하부전극 마스크를 식각마스크로 식각하여 하부전극(17) 및 확산방지막 패턴을 형성한다.Next, the lower electrode conductive layer and the diffusion barrier layer are etched with the lower electrode mask as an etch mask to form the lower electrode 17 and the diffusion barrier pattern.
그 다음, 전체표면 상부에 실리콘 질화막을 증착한 후, 상기 실리콘 질화막을 전면식각하여 상기 하부전극 및 확산방지막 패턴의 식각면에 실리콘 질화막 스페이서(18)를 형성한다.Next, after the silicon nitride film is deposited on the entire surface, the silicon nitride film is etched to form a silicon nitride film spacer 18 on the etching surface of the lower electrode and the diffusion barrier pattern.
다음, 전체표면 상부에 유전체막(19)과 상부전극(도시안됨)을 형성한다. 상기 유전체막(19)은 500 ∼ 700℃의 온도에서 BST((Ba1-xSrx)TiO3)막을 사용하여 형성하고, 상기 상부전극을 형성한 후에는 600 ∼ 900℃의 질소 또는 산소분위기에서 열처리공정을 실시한다.Next, a dielectric film 19 and an upper electrode (not shown) are formed over the entire surface. The dielectric film 19 is formed using a BST ((Ba 1-x Sr x ) TiO 3 ) film at a temperature of 500 to 700 ° C., and after forming the upper electrode, nitrogen or oxygen atmosphere of 600 to 900 ° C. The heat treatment process is performed at.
상기와 같이 종래기술에 따른 반도체소자의 캐패시터 형성방법은, 유전체막의 두께에 의해 캐패시턴스가 결정되기 때문에 가능한한 상기 유전체막을 얇은 두께로 형성해야 하고, 그러기 위해서 상기 유전체막은 단차피복성(step coverage)이 우수하여 하부전극의 상부 및 측벽에 일정한 두께로 형성되어야 하지만, 상기 하부전극의 상부와 측벽에서 1 : 0.3의 두께비를 갖는다. 따라서, 유전체막을 일정한 두께로 형성하기 위해서는 고온에서 화학기상증착(chemical vapor deposition, 이하 CVD 라 함)방법으로 형성해야 한다. 그러나, BST막과 같은 고유전물질을 증착하기 위한 원료물질의 분해 특성상 600℃ 이상의 온도에서 유전특성이 우수한 박막 증착이 가능하지만, 하부전극 구조가 열안정성을 지니지 못해 캐패시터의 특성을 열화시키는 문제점이 있다.As described above, in the method of forming a capacitor of a semiconductor device according to the prior art, since the capacitance is determined by the thickness of the dielectric film, the dielectric film should be formed as thin as possible. In order to achieve this, the dielectric film has a step coverage. It should be formed to have a constant thickness on the top and sidewalls of the lower electrode, but has a thickness ratio of 1: 0.3 at the top and sidewalls of the bottom electrode. Therefore, in order to form the dielectric film at a constant thickness, it must be formed by chemical vapor deposition (hereinafter referred to as CVD) at a high temperature. However, due to the decomposition of raw materials for depositing high-k dielectric materials such as BST films, thin film deposition with excellent dielectric properties is possible at temperatures higher than 600 ° C. However, the lower electrode structure does not have thermal stability, which deteriorates the characteristics of the capacitor. have.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 하부전극 상부에 저온공정이 가능한 PVD방법으로 유전체막인 BST막을 형성한 다음, 전면식각공정을 실시하여 상기 하부전극의 측벽에 형성된 유전체막과 하부전극의 상부에 형성된 유전체막의 두께를 일정하게 형성함으로써 캐패시터의 전기적 특성을 향상시키고, 그에 따른 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 캐패시터 형성방법을 제공하는데 그 목적이 있다.The present invention provides a dielectric film formed on the sidewall of the lower electrode by forming a BST film, which is a dielectric film, by a PVD method capable of a low temperature process on the lower electrode, and then performing an entire surface etching process. It is an object of the present invention to provide a method for forming a capacitor of a semiconductor device by improving the electrical characteristics of the capacitor and thereby improving the characteristics and reliability of the capacitor by forming a thickness of the dielectric film formed on the lower electrode.
도 1 은 종래기술에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도.1 is a cross-sectional view showing a capacitor forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도.2A to 2E are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
〈도면의 주요부분에 대한 부호 설명〉<Explanation of symbols on main parts of the drawing>
11, 21 : 반도체기판 12, 22 : 접합영역11, 21: semiconductor substrate 12, 22: junction region
13, 23 : 층간절연막 14, 24 : 저장전극 콘택플러그13, 23: interlayer insulating film 14, 24: storage electrode contact plug
15, 25 : 티타늄층 16, 26 : 질화티타늄층15, 25: titanium layer 16, 26: titanium nitride layer
17, 27 : 하부전극 18, 28 : 실리콘 질화막 스페이서17, 27: lower electrode 18, 28: silicon nitride film spacer
19, 29 : 유전체막 30 : 상부전극19, 29: dielectric film 30: upper electrode
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 캐패시터 형성방법은,In order to achieve the above object, a method of forming a capacitor of a semiconductor device according to the present invention,
a. 소정의 하부구조물이 형성되어 있는 반도체기판 상부에 저장전극 콘택플러그가 구비된 층간절연막을 형성하는 공정과,a. Forming an interlayer insulating film having a storage electrode contact plug on the semiconductor substrate having a predetermined lower structure formed thereon;
b. 상기 층간절연막 상부에 확산방지막 및 하부전극용 박막의 적층구조를 형성하는 공정과,b. Forming a stacked structure of a diffusion barrier and a lower electrode thin film on the interlayer insulating film;
c. 상기 적층구조를 하부전극 마스크를 이용하여 식각하는 공정과,c. Etching the stacked structure using a lower electrode mask;
d. 상기 적층구조 측벽에 절연막 스페이서를 형성하는 공정과,d. Forming an insulating film spacer on the sidewalls of the laminated structure;
e. 전체표면 상부에 저온 PVD 증착 공정으로 유전체막을 형성하는 공정과,e. Forming a dielectric film on the entire surface by low temperature PVD deposition;
f. 상기 유전체막을 전면식각하여 상기 유전체막을 균일한 두께를 형성하는 공정과,f. Forming a uniform thickness on the dielectric film by etching the entire surface of the dielectric film;
g. 상기 유전체막을 열처리하는 제1열처리공정과,g. A first heat treatment step of heat treating the dielectric film;
h. 상기 유전체막 상부에 상부전극을 형성한 다음, 제2열처리공정을 실시하는 것을 특징으로 한다.h. An upper electrode is formed on the dielectric layer, and then a second heat treatment process is performed.
또한, 본 발명은 PVD방법으로 박막을 증착하면 측벽피복성(sidewall coverage)이 30%정도에 불과하고, 전면식각공정은 측벽에 형성된 박막은 거의 식각하지 못한다는 원리를 이용하여 단차피복성이 우수한 유전체막을 형성한다.In the present invention, when the thin film is deposited by the PVD method, the sidewall coverage is only about 30%, and the front side etching process has excellent step coverage by using the principle that the thin film formed on the sidewall is hardly etched. A dielectric film is formed.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명에 따른 반도체소자의 캐패시터 형성방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
먼저, 소정의 하부구조물이 형성되어 있는 반도체기판(21) 상부에 저장전극 콘택으로 예정되는 접합영역(22)을 노출시키는 저장전극 콘택홀(도시안됨)이 구비되는 층간절연막(23)을 형성한다.First, an interlayer insulating layer 23 having a storage electrode contact hole (not shown) that exposes a junction region 22 that is intended as a storage electrode contact is formed on the semiconductor substrate 21 on which a predetermined substructure is formed. .
다음, 상기 층간절연막(23) 상부에 상기 저장전극 콘택홀을 매립하는 다결정실리콘층을 저압화학기상증착(low presure chemical vapor deposition, 이하 LPCVD 라 함)방법으로 형성한다.Next, a polysilicon layer filling the storage electrode contact hole is formed on the interlayer insulating layer 23 by a low presure chemical vapor deposition (LPCVD) method.
그 다음, 상기 다결정실리콘층을 플라즈마를 이용한 전면식각 또는 CMP공정으로 제거하여 상기 저장전극 콘택홀을 통하여 상기 접합영역(22)과 접속되는 저장전극 콘택플러그(24)를 형성한다.Next, the polysilicon layer is removed by a front surface etching using a plasma or a CMP process to form a storage electrode contact plug 24 connected to the junction region 22 through the storage electrode contact hole.
다음, 전체표면 상부에 확산방지막인 티타늄막(25)과 질화티타늄막(26) 적층구조를 직류스퍼터방법으로 형성한다. 상기 티타늄막(25)은 150 ∼ 250Å 두께로 형성하고, 상기 질화티타늄막(26)은 450 ∼ 550Å 두께로 형성한 후, 상기 확산방지막을 400 ∼ 500℃의 질소분위기에서 20 ∼ 40분간 열처리한다.Next, a stacked structure of the titanium film 25 and the titanium nitride film 26, which are diffusion preventing films, is formed on the entire surface by a direct current sputtering method. The titanium film 25 is formed to a thickness of 150 to 250 kPa, the titanium nitride film 26 is formed to be 450 to 550 kPa thick, and then the diffusion barrier is heat-treated for 20 to 40 minutes in a nitrogen atmosphere at 400 to 500 ° C. .
그 다음, 상기 질화티타늄막(26) 상부에 Pt막을 이용하여 하부전극용 도전층을 형성한다.Next, a conductive layer for a lower electrode is formed on the titanium nitride film 26 by using a Pt film.
다음, 상기 하부전극용 도전층과 확산방지막을 하부전극으로 예정되는 부분을 보호하는 하부전극 마스크를 사용하여 식각함으로써 하부전극(27) 및 확산방지막 패턴을 형성한다.Next, the lower electrode 27 and the diffusion barrier layer pattern are formed by etching the lower electrode conductive layer and the diffusion barrier layer using a lower electrode mask that protects a portion intended as the lower electrode.
그 다음, 전체표면 상부에 실리콘 질화막을 증착한 후, 상기 실리콘 질화막을 전면식각하여 상기 하부전극(27) 및 확산방지막 패턴의 식각면에 실리콘 질화막 스페이서(28)를 형성한다. (도 2a참조)Next, after the silicon nitride film is deposited on the entire surface, the silicon nitride film is etched entirely to form the silicon nitride film spacer 28 on the etching surface of the lower electrode 27 and the diffusion barrier pattern. (See Figure 2A)
다음, 전체표면 상부에 PVD방법으로 고유전물질인 BST막을 유전체막(29)으로 형성하되, 상기 하부전극(27) 및 확산방지막 패턴의 측벽에 증착되는 유전체막(29)의 두께를 기준으로 하여 상기 하부전극(27) 상부에 원하는 두께의 100 ∼ 300%가 증착될 때까지 유전체막(29)을 증착한다.(도 2b참조)Next, a BST film, which is a high dielectric material, is formed on the entire surface of the dielectric film 29 by a PVD method, based on the thickness of the dielectric film 29 deposited on the sidewalls of the lower electrode 27 and the diffusion barrier pattern. The dielectric film 29 is deposited on the lower electrode 27 until 100 to 300% of the desired thickness is deposited (see FIG. 2B).
그 다음, 상기 유전체막(29)을 플라즈마를 이용한 건식식각방법으로 전면식각한다. 이때, 상기 하부전극(27) 및 확산방지막 패턴의 측벽에 증착된 유전체막(29)의 두께를 기준으로 하여 상기 하부전극(27) 상부에 증착된 유전체막(29)을 제거함으로써 상기 유전체막(29)의 두께가 전체적으로 동일하게 형성되도록한다. (도 2c참조)Next, the dielectric film 29 is etched entirely by a dry etching method using plasma. In this case, the dielectric layer may be removed by removing the dielectric layer 29 deposited on the lower electrode 27 based on the thickness of the dielectric layer 29 deposited on the sidewalls of the lower electrode 27 and the diffusion barrier layer pattern. 29) so that the overall thickness is formed the same. (See FIG. 2C)
그 후, 상기 유전체막(29)을 400 ∼ 700℃의 온도의 산소 또는 질소분위기에서 10 ∼ 60분간 열처리공정을 실시하거나, 500 ∼ 700℃의 온도의 산소 또는 질소분위기에서 30 ∼ 600초간 급속열처리공정을 실시하여 유전체막의 특성을 향상시킨다. 이때, 상기 열처리공정으로 상기 유전체막(29)서 부족한 산소를 보충하여 결정화시킨다. (도 2d참조)Thereafter, the dielectric film 29 is subjected to a heat treatment process for 10 to 60 minutes in an oxygen or nitrogen atmosphere at a temperature of 400 to 700 ° C, or rapid heat treatment for 30 to 600 seconds in an oxygen or nitrogen atmosphere at a temperature of 500 to 700 ° C. The process is performed to improve the characteristics of the dielectric film. At this time, oxygen insufficient in the dielectric film 29 is supplemented and crystallized by the heat treatment process. (See FIG. 2D)
그리고, 상기 유전체막(29) 상부에 Pt막을 사용하여 상부전극(30)을 형성한다.The upper electrode 30 is formed on the dielectric layer 29 by using a Pt layer.
그 다음, 전체표면 상부를 400 ∼ 700℃의 온도의 산소 또는 질소분위기에서 10 ∼ 60분간 열처리공정을 실시하거나, 500 ∼ 700℃의 온도의 산소 또는 질소분위기에서 30 ∼ 600초간 급속열처리공정을 실시한다. (도 2e참조)Then, the entire surface is subjected to a heat treatment process for 10 to 60 minutes in an oxygen or nitrogen atmosphere at a temperature of 400 to 700 ° C or a rapid heat treatment process for 30 to 600 seconds in an oxygen or nitrogen atmosphere at a temperature of 500 to 700 ° C. do. (See Figure 2E)
한편, 상기 유전체막을 전면식각한 후 열처리공정을 실시하지 않고 바로 상부전극(30)을 형성한 다음, 열처리공정을 실시할 수도 있다.Meanwhile, after the entire surface of the dielectric film is etched, the upper electrode 30 may be formed immediately without performing a heat treatment process, and then a heat treatment process may be performed.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 캐패시터 형성방법은, 하부전극 상부에 고유전체막을 저온에서 증착가능한 PVD방법을 사용하여 증착한 다음, 전면식각공정을 실시하여 상기 하부전극의 측벽 및 상부에 형성된 고유전체막의 두께를 동일하게 형성함으로써 반도체소자가 고집적화되어 감에 따라 요구되는 정전용량을 확보할 수 있도록 유전체막을 형성하여 반도체소자의 고집적화를 가능하게 하고 그에 따른 소자의 특성 및 수율을 향상시키는 이점이 있다.As described above, in the method of forming a capacitor of a semiconductor device according to the present invention, a high dielectric film is deposited on the lower electrode by using a PVD method capable of depositing at a low temperature, and then subjected to an entire surface etching process to perform side etching and top of the lower electrode. By forming the same thickness of the high-k dielectric film formed in the semiconductor device, the dielectric film is formed to secure the required capacitance as the semiconductor device becomes highly integrated, thereby enabling high integration of the semiconductor device and thereby improving the characteristics and yield of the device. There is an advantage.
Claims (8)
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| JPH08316430A (en) * | 1995-05-15 | 1996-11-29 | Mitsubishi Electric Corp | Semiconductor memory, manufacturing method thereof, and stacked capacitor |
| KR970030833A (en) * | 1995-11-29 | 1997-06-26 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| JPH1041478A (en) * | 1996-04-23 | 1998-02-13 | Internatl Business Mach Corp <Ibm> | Method for producing electric device and composite stack electrode |
| KR19980026823A (en) * | 1996-10-11 | 1998-07-15 | 김광호 | Capacitor of Semiconductor Device and Manufacturing Method Thereof |
| KR19980086199A (en) * | 1997-05-31 | 1998-12-05 | 윤종용 | Capacitor Formation Method of Semiconductor Memory Using Ferroelectric |
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| JPH08316430A (en) * | 1995-05-15 | 1996-11-29 | Mitsubishi Electric Corp | Semiconductor memory, manufacturing method thereof, and stacked capacitor |
| KR970030833A (en) * | 1995-11-29 | 1997-06-26 | 김광호 | Capacitor Manufacturing Method of Semiconductor Device |
| JPH1041478A (en) * | 1996-04-23 | 1998-02-13 | Internatl Business Mach Corp <Ibm> | Method for producing electric device and composite stack electrode |
| KR19980026823A (en) * | 1996-10-11 | 1998-07-15 | 김광호 | Capacitor of Semiconductor Device and Manufacturing Method Thereof |
| KR19980086199A (en) * | 1997-05-31 | 1998-12-05 | 윤종용 | Capacitor Formation Method of Semiconductor Memory Using Ferroelectric |
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