KR100333549B1 - Forming method for bit line of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a bit line of a semiconductor device, wherein a bit line having a different structure is formed in a cell region and a peripheral circuit region, wherein a bit line of a polysilicon layer / metal layer stacked structure is formed in the cell region. In the peripheral circuit region, a bit line formed of a metal layer is formed. In the cell region, the junction characteristic is improved, thereby reducing the bit line resistance while maintaining the refresh characteristic. As a result, the number of transistors hanging on one bit line in the cell region is increased. It improves cell efficiency and improves device integration speed by increasing bit density by forming only a polysilicon layer in the peripheral circuit area and applying only limited NMOS to both NMOS and PMOS. It is a technology that improves the performance and thereby high integration of semiconductor devices.

Description

Forming method for bit line of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device. In particular, a bit line having a different structure is formed in a cell region and a peripheral circuit region of a semiconductor substrate so that the resistance is low and the semiconductor can be applied without distinguishing between NMOS and PMOS transistors. It relates to a method for forming a bit line of a device.

As semiconductor devices become more integrated, the gate electrode of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET) is decreasing in width, but when the width of the gate electrode is reduced by N times, the electrical resistance of the gate electrode is decreased. There is a problem that the N times increased to decrease the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, polyside, which is a laminated structure of the polysilicon layer and the silicide, is used as the low resistance gate by using the property of the polysilicon layer / oxide film interface exhibiting the most stable MOSFET characteristics.

In general, the most important function of the transistor constituting the semiconductor circuit is the current driving capability, and the channel width of the MOS FET is adjusted in consideration of this. The most widely used MOS FET uses a polysilicon layer doped with impurities as a gate electrode, and a diffusion region doped with impurities on a semiconductor substrate is used as a source / drain region. Here, the sheet resistance of the gate electrode is about 30 to 70? /? The sheet resistance of the source / drain regions is about 70 to 150 Ω /? For N + and about 100 to 250 Ω /? For P +. In the case of a contact formed on a gate electrode or a source / drain region, the contact resistance is about 30 to 70? /? It is enough.

In order to reduce the high sheet resistance and contact resistance of the gate electrode and the source / drain regions, a metal silicide layer may be formed only on the gate electrode and the source / drain regions by a salicide (self-aligned silicide) method or a selective metal layer deposition method. The current driving capability of the MOS FET was increased.

In addition, the bit line currently used in the semiconductor device fabrication technology is formed by depositing a polysilicon layer about 1000 후에 after forming the bit line contact, forming a nitride film with a tungsten silicide layer and an anti-reflection film, and then using a bit line mask. The peripheral circuit region was formed by etching simultaneously. In this case, the bit line may be subjected to a subsequent thermal process, and since the silicide layer is used, the resistance of the bit line may be reduced.

However, since the resistance of the bit line is greater than a certain amount and the bit line capacitance applied to the bit line is large, there is no margin for having more than 512 cells per bit in one bit line, thereby affecting cell efficiency. In addition, since the bit line was manufactured by using the bit line contact at the same time in the cell region and the peripheral circuit region, the bit line contact was not used for the PMOS in the peripheral circuit region, and only limited to the NMOS, there was a significant loss in terms of integration. .

The present invention is to solve the above problems, to form a bit line formed of a laminated structure of a polysilicon layer / metal layer in the cell region, and to form a bit line formed of a metal layer in the peripheral circuit region to reduce the resistance of the bit line A method of forming a bit line of a semiconductor device is provided.

1 to 4 are cross-sectional views showing a bit line forming method of a semiconductor device according to the present invention.

<Description of the code | symbol about the principal part of drawing>

11 semiconductor substrate 13 gate electrode

15 mask insulating film 17 insulating film spacer

19: interlayer insulating film 21: bit line conductive layer

23: second bit line contact hole 25: diffusion barrier

27: metal layer

A bit line forming method of a semiconductor device according to the present invention for achieving the above object,

Forming a MOS field effect transistor comprising a gate electrode having a mask insulating film laminated on the semiconductor substrate including a cell region and a peripheral circuit region, and a source / drain region of an LDD structure;

Forming an interlayer insulating film over the entire surface;

Forming a first bit line contact hole by etching the interlayer insulating layer using a first bit line contact mask that exposes a portion of the cell region to be a bit line contact as an etch mask;

Forming a conductive layer for bit lines so that the bit line contact holes are not buried in the entire surface;

The bit line conductive layer, the interlayer insulating film, and the mask insulating film are etched by using, as an etching mask, a second bit line contact mask that exposes an upper portion of the gate electrode, which is intended as a bit line contact, in the peripheral circuit region and an active region of the semiconductor substrate. Forming a second bit line contact hole;

And forming a stacked structure of a diffusion barrier, a metal layer, and an antireflective coating on the entire surface, and then etching the stacked structure using a bit line mask to form a bit line.

Hereinafter, a method of forming a bit line of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 4 are cross-sectional views showing a bit line forming method of a semiconductor device according to the present invention.

First, a desired type of impurity is implanted into a desired portion of the semiconductor substrate 11 composed of the cell region (I) and the peripheral circuit region (II) to form a desired shape in the channel portion of the well and the transistor and the lower portion of the device isolation region. After the impurity is present, a device isolation insulating film (not shown) is formed on the portion of the semiconductor substrate 11 which is intended as the device isolation region.

Next, a gate insulating film (not shown) is formed on the semiconductor substrate 11, and a gate electrode 13 is formed on the semiconductor substrate 11. The mask insulating layer 15 is stacked on the gate electrode 13.

Next, low concentration impurities are implanted into both semiconductor substrates 11 of the gate electrode 13 to form an LDD region (not shown).

An insulating film spacer 17 is formed on the sidewalls of the gate electrode 13 and the mask insulating film 15, and then ion implantation of high concentrations of impurities into both semiconductor substrates 11 of the insulating film spacer 17 is performed. A drain region (not shown) is formed.

Next, an interlayer insulating film 19 is formed over the entire surface, such as a BPSG film.

Next, the interlayer insulating film 19 is etched by a flow process, an entire surface etching or a CMP process to remove the step formed between the cell region I and the peripheral circuit region II of the semiconductor substrate 11.

Thereafter, although not shown, a thin oxide film is formed on the interlayer insulating film 19 to prevent impurities such as boron and phosphorus contained in the interlayer insulating film 19 from being automatically doped into the conductor formed in a subsequent process. do. (See Figure 1)

Next, the interlayer insulating layer 19 is etched using a first bit line contact mask (not shown) that exposes a portion intended to be a bit line contact in the cell region I as an etch mask, thereby etching the first bit line contact hole. (Not shown).

Next, a bit thickness conductive layer 21 is formed on the entire surface of the bit line, and the first bit line contact hole is not buried. The bit line conductive layer 21 is formed of a laminated structure of a polycrystalline silicon layer or a doped polycrystalline silicon / undoped polycrystalline silicon layer. (See Figure 2)

Next, in the peripheral circuit region II, a second bit line contact mask that exposes a portion intended as a bit line contact on the gate electrode 13 and a portion intended as a bit line contact on the semiconductor substrate 11 is etched. The bit line conductive layer 21, the interlayer insulating film 19, and the mask insulating film 15 are etched using a mask to form a second bit line contact hole 23. (See Figure 3)

Next, a diffusion barrier 25 is formed on the entire surface, and a metal layer 27 is formed on the diffusion barrier 25. The diffusion barrier 25 may be formed of a Ti / TiN film, and the metal layer 27 may be formed of an Al film or another metal material. (See Fig. 4)

Thereafter, although not shown, an anti-reflection film is formed on the metal layer 27 by Ti / TiN film or the like in a subsequent process, and then the anti-reflection film, the metal layer 27 and the bit line are formed using a bit line mask as an etching mask. The conductive layer 21 is etched to form a bit line.

Unlike the method of forming the gate electrode and the bit line as described above, after forming the gate electrode, the capacitor may be formed, and then the bit line may be formed. In this case, a spacer is formed on the sidewall of the storage electrode contact hole by using an oxide film or a nitride film to insulate the bit line during the capacitor formation process.

As described above, in the method of forming a bit line of a semiconductor device according to the present invention, a bit line having a different structure is formed in a cell region and a peripheral circuit region, and a bit line of a polysilicon layer / metal layer stacked structure is formed in the cell region. And forming a bit line formed of a metal layer in the peripheral circuit region to improve the junction characteristics in the cell region, thereby lowering the bit line resistance while maintaining the refresh characteristics. Increasing the number of cells improves cell efficiency, and in the peripheral circuit area, the bit line is formed only of polycrystalline silicon layer, and the limited use of NMOS is applied to both NMOS and PMOS to improve device integration. To improve the performance of the semiconductor device and to thereby enable high integration of semiconductor devices. There.

Claims (6)

Forming a MOS field effect transistor comprising a gate electrode having a mask insulating film laminated on the semiconductor substrate including a cell region and a peripheral circuit region, and a source / drain region of an LDD structure; Forming an interlayer insulating film over the entire surface; Forming a first bit line contact hole by etching the interlayer insulating layer using a first bit line contact mask that exposes a portion of the cell region to be a bit line contact as an etch mask; Forming a conductive layer for bit lines so that the bit line contact holes are not buried in the entire surface; The bit line conductive layer, the interlayer insulating film, and the mask insulating film are etched by using, as an etching mask, a second bit line contact mask that exposes an upper portion of the gate electrode, which is intended as a bit line contact, in the peripheral circuit region and an active region of the semiconductor substrate. Forming a second bit line contact hole; Forming a bit line by forming a stacked structure of a diffusion barrier, a metal layer, and an antireflective layer on the entire surface, and then etching the stacked structure using a bit line mask to form a bit line. Way. The method of claim 1, And the bit line conductive layer is formed of a stacked structure of a polysilicon layer or a doped polysilicon layer / undoped polysilicon layer. The method of claim 1, And the diffusion barrier layer is formed of a Ti / TiN layer. The method of claim 1, The metal layer is a bit line forming method of a semiconductor device, characterized in that formed of an Al layer or other metal material. The method of claim 1, And wherein the anti-reflection film is formed of a Ti / TiN film. The method of claim 1, The bit line of the bit line conductive layer / diffusion barrier / metal layer stacked structure is formed in the cell region, the bit line formed of the diffusion barrier / metal layer is formed in the peripheral circuit region. .