KR100331466B1 - Inter Processor Communication Control Method - Google Patents

Abstract

In the case of interprocessor communication in a system where a large number of counterparts communicate with each other at the same time, such as a switching system, it informs the counterpart system of resource change state information in the system so that the amount of information transfer between processors can be controlled.

The present invention includes the steps of detecting the state information of the OS part in the own system in real time and transmitting to the IPC control part; Analyzing, by the IPC control part, state information of an OS part to determine whether adjustment of the communication rate between processors is required; If the inter-processor communication rate needs to be adjusted, the method may include determining a transmission rate that can be processed by the OS part, and requesting the counterpart system to adjust the transmission rate.

Thus, the loss of messages is eliminated in interprocessor communication, and the stability of the self and the counterpart system processor is kept stable in interprocessor communication, thereby eliminating the load on the processor, thereby providing stability in operation.

Description

Inter Processor Communication Control Method

The present invention relates to interprocessor communication, and more particularly, in a system having many partners to communicate with each other at the same time, such as an exchange system, to inform the counterpart system of resource change state information in the system so that the amount of information transmission can be controlled during interprocessor communication. It relates to a method for controlling communication between processors.

In general, many systems that communicate with each other simultaneously, such as switching systems, exchange status and processing information of the partner systems in a CROS (Concurrent Real Time Operating System) method to perform appropriate call processing and resource management for them. It is performed through interprocessor communication (IPC) between a main processor provided in a master system and a peripheral processor provided in a slave system.

As shown in FIG. 1, the main processor board provided in the master system for inter-processor communication as described above is configured with an OS part (Operating System Part; 10) that performs various overall operations of the system. It consists of an IPC control part 20 that performs interprocessor communication according to an algorithm.

In the OS part 10, the controller 11 generates a corresponding process according to the detected event and performs various operations on the operation of the system, and in the interprocessor communication performed through the IPC control part 20. RAM 12 for temporarily storing general data is provided, and the IPC control part 20 includes a control unit 21 for controlling the communication operation between the processor of the counterpart system and the processor according to a set algorithm, and the processor from the counterpart system. RAM 22 which temporarily stores general information received through communication and temporarily stores information transmitted from the OS part 10 to the processor side of the counterpart system, and a processor that matches the counterpart system and is performed between itself and the counterpart system. It consists of a system matching unit 23 for serial interface of the communication information between.

In addition, the main processor board stores data received by the IPC control part 20 through inter-processor communication with the counterpart system so that the OS part 10 can access it, and the OS part 10 controls system operation. A dual port RAM (DPRAM) 30, which is a bidirectional read / write RAM that stores data for accessing and accesses the IPC control part 20 and then transmits interprocessor communication to the counterpart system through a serial interface, is provided.

An operation of transmitting and receiving communication data between processors between the OS part 10 and the IPC control part 20 in the main processor board having the above configuration is as follows.

According to the occurrence of the event, a process generated by the control unit 11 of the OS part 10 is provided with its own parts according to the system clock to process the corresponding data for inter-processor communication for processing the corresponding event. After writing to the DPRAM 30 through the RAM 12, the corresponding operation is performed without burdening the inter-processor communication with respect to other events.

As described above, when data for interprocessor communication is stored in the DPRAM 30, the IPC control part 20 accesses the data stored in the DPRAM 30 at a set period, stores the data in the RAM 22, and then synchronizes the system clock. By performing the serial interface to the counterpart system through the matching unit 23 to perform the corresponding function or resource management and call processing.

In addition, the interprocessor communication data received by the matching unit 23 of the IPC control part 20 from the counterpart system via the serial interface is stored in the RAM 22 and then controlled by the control unit 21 that manages the IPC control part 20. The control unit 11 of the OS part 10 accesses the received data stored in the DPRAM 30 at a set period and transfers the received data to an application processor that manages the corresponding data for a corresponding function. Allow processing and control to be performed.

As described above, the communication between the processor and the counterpart system through the serial interface generally uses a sliding window flow control method. An operation thereof will be described with reference to FIG. 2.

In the case of a switching system, communication between multiple counterpart systems and processors must be performed at the same time. Therefore, a window is created for each counterpart system performing interprocessor communication, and a sequence number to be transmitted and a sequence number to be received are stored for each window.

That is, if the number of transmissions is completed, after confirming whether the data transmitted to the counterpart system is normally received, if there is a response, the next interprocessor communication data is transmitted to the corresponding system. If there is no response from the counterpart system, and if there is no response from the counterpart system, the next interprocessor communication data is not transmitted, thereby controlling the flow of interprocessor communication data.

As shown in FIG. 2, when system A is called a queue queue of its own system and system B is a queue queue of a counterpart system, the window slides of the system queues of system A and system B are initialized in the system initialization state. 0-7 'remains empty because no interprocessor communication is performed (a) (b).

In this case, when transmitting '3' interprocessor communication data from system A to system B, the queue queue of system A, the sender, stores and stores the transmitted data '3', so the window slide is '0-2'. The data is recorded and remains empty until '3-7', and the queue queue of system B that receives data 'F0, F1, F2' through inter-processor communication receives the received data 'F0, F1, F2'. Since the data is stored in the window slide, data is recorded up to '0-2' and remains empty until '3-7' (c) (d).

In this case, the system B receiving the data of 'F0, F1, F2' through inter-processor communication, according to the data reception status query requested by the system A side, the response signal corresponding thereto, that is, the information specifying the first empty window slide When the 'ACK3' is transmitted to the system A side, the slides in the queue queues of the system A and the system B become empty until '3-10', so that data transmitted and received through inter-processor communication can be stored (e) (f).

Subsequently, when the system A transmits data 'F3, F4, F5, F6' through inter-processor communication to the system B side according to the response signal 'ACK3' received from the system B, the queue queue of the system A transmits the data information. As the Windows slide records data up to '0-6', the empty slide becomes '7-11' and the system B side that received the data of 'F3, F4, F5, F6' through inter-processor communication. The window slide of the queue queue is also recorded with data up to '0-6', and the empty slide becomes '7-11'.

As described above, the data 'F0, F1, F2, F3, F4, F5, F6' transmitted and received to the queue queue slide '0-6' of system A and system B are recorded, and the window slide is blank. If the system B sends a response signal 'ACK' to the system A in response to an inquiry about the data transmission required by the system A, the queue queue window slides of the system A and the system B become empty until '7-14'. The operation as described above is repeated continuously in the process of the inter-processor communication.

If the transmitted data is not normally received in the state of transmitting and receiving data by the processor-to-processor communication as described above, the system B requests retransmission of the corresponding data to the system A side, and the system A window of the queue queue according to the retransmission request. Retransmit only the requested data stored in the system B side.

As described above, since the interprocessor communication performed through the slide window control method is the communication control between the system IPC control parts, the transmission control is independent of the load of the OS part that processes the data received through the interprocessor communication from the counterpart system. Is performed.

That is, the OS part in the system that receives the message data does not have the resources to process the received message data due to the load of the control means and the load of the queue queue, but the IPC control part has sufficient resources to receive and process the data. In this case, the IPC control part cannot recognize the state information of the OS part, thereby performing interprocessor communication control using normal parameters, causing a problem of loss of message data transmitted and received between the OS and the IPC control part in the system.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described general problems, and an object thereof is to provide status information between an OS part and an IPC control part in a system so that message data transmitted and received in inter-processor communication with multiple counterpart systems does not occur at the same time. If the normal inter-processor communication cannot be performed due to one of the loads, the request is made to adjust the data rate to the counterpart system so that message data is not lost in the inter-processor communication.

1 is a schematic diagram showing a configuration of a general main processor board.

2 is a flow diagram illustrating operation of a sliding window protocol in interprocessor communication.

3 is a flow diagram of an embodiment of performing interprocessor communication control in accordance with the present invention.

<Explanation of symbols for main parts of the drawings>

10: OS part 20: IPC control part

In accordance with another aspect of the present invention, there is provided a method of controlling an interprocessor communication, the method comprising: detecting real-time state information of an OS part in a self-system and transmitting the same to an IPC control part; Analyzing, by the IPC control part, state information of an OS part to determine whether adjustment of the communication rate between processors is required; If the inter-processor communication rate needs to be adjusted, the method may include determining a transmission rate that can be processed by the OS part, and requesting the counterpart system to adjust the transmission rate.

The state information of the OS part includes load information of data analysis processing means and usage information of a queue queue, and the state information of the OS part transmitted to the IPC control part indicates that a current value and an average value of a predetermined step are simultaneously transmitted. It features.

In addition, when the IPC control part requests the other system to adjust the transmission rate, information on requesting the adjustment of the slide range and the packet counter is transmitted to the response signal for acknowledgment of the message received by the other system in sliding window flow control. Request for adjustment of the transmission rate.

When the transmission rate is adjusted by adjusting the packet counter, a message to be transmitted to a counterpart system of the same destination is packed in a packet and transmitted, but a plurality of messages are packed in one packet and transmitted according to the packet counter value. It features.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, when the inter-processor communication is performed for a plurality of counterpart processors simultaneously using the CROS method, the operation of controlling the transmission rate of the inter-processor communication message data is performed based on the attached FIG. The description of the structure of the processor board is omitted.

As shown in FIG. 3, in a state in which a main processor performs communication between processors using a plurality of counterpart processors and a CROS method, an operation process in an OS part may determine load information and utilization rates of queue queues of its own control unit 11. Measured in real time (approximately 40 sec intervals) (S101), the information of the current value and the average value for each unit time of a predetermined step is processed in a predetermined state, and then DPRAM (30) with message data to be transmitted to the counterpart system. ) In step S102.

The load information of the control unit 11 and the information on the utilization rate of the queue queue are transmitted by assigning, for example, the current information measured at an interval of 40 ms and the average value between 200 ms and the average value between 1 sec and the average value between 5 sec. do.

At this time, the load information of the controller 11 in the OS part 10 and the information on the utilization rate of the queue queue are recorded in the DPRAM 30 through the following algorithm.

default value: Slide_count = 8, Pack_count = 5

static const FlowInfo_t CPUData [] = {

{700,8,5}, / * reported_value, Slide_count, Pack_count * /

{750,7,5}.

{800,6,4}

{850,5,4},

{900,5,3}

{950,4,3}

{1000,3,2} / * ALERT * /

};

#defin C_INFO_NUM (sizeof (CPUData) / sizeof (FlowInfo_t)

static const FlowInfo_t IPCData [] = {

{400,0,5},

{500,0,4}

{600,0,3}

{700,0.2}

{800,0,1}

{900,0.1}

{1000,0,1}

};

levelize = (load-700) / 50;

real_level = realize-(3-i); / * Weighted: the average value takes precedence over the current value. * /

In the above algorithm, each step composed of {xxx, y, z} means a level value, xxx is load information of a control unit, y is a slide counter, and z is a packet counter.

When the load information of the control unit 11 in the OS part and the information on the utilization rate of the queue queue are recorded in the DPRAM 30 through the algorithm as described above, the control unit 21 in the IPC control part 20 processes the processor with the counterpart system. In the process of accessing the inter-communication message data from the DPRAM 30, the state information of the OS part 10 is simultaneously accessed, so that the control unit 21 of the IPC control part 20 controls the OS part 10 through the set algorithm. After analyzing the load information and the utilization rate of the standby queue (S103), it is determined whether the transmission rate needs to be adjusted in interprocessor communication with the counterpart system (S104).

In the above determination, if it is determined that the OS part 10 is able to stably process the inter-processor communication message data by maintaining the current transmission rate, the IPC control part 20 adjusts the inter-processor communication transmission rate with the current parameter value. If it is determined that the state information of the OS part 10 cannot perform interprocessor communication with the current parameter value and adjusts the transmission amount of the interprocessor communication that can be substantially processed, the matching unit 23 is maintained. By transmitting to the counterpart system through the serial interface through the request to adjust the transmission rate (S106).

Thereafter, transmission and reception of communication message data between processors with the counterpart system is maintained according to the transmission rate adjusted according to the counterpart system's response (S107), and such an operation is continuously repeated in an infinite loop.

In the above case, when the IPC control part 20 requests the counterpart system to adjust the transmission rate of the transmission and reception of the communication message between the processors according to the state of the OS part 10, the counterpart may not use a separate message, but the sliding window flow control. The response signal 'ACK' for the message acknowledgment information to be queried is transmitted with information requesting adjustment of a slide range and a packet counter.

When the slide range is adjusted, the message data is transmitted to the counterpart system until N message data is transmitted to the counterpart system in the slide window flow control, but the response signal 'ACK' is received from the counterpart system. If the slide range is reduced, the transmission rate of the interprocessor communication is lowered.

Also, when adjusting the packet counter, for the same destination counterpart system, a message packed by the OS part of the counterpart system is packed by transmitting several message data into one packet corresponding to the value of the packet counter during the transmission delay. Since the data is divided into several message data and the queue is used, the processor that transmits the message data reduces the number of packets to be transmitted, thereby minimizing the utilization of the queue queue of the OS part, thereby reducing the transmission rate in interprocessor communication.

For example, the IPC control part 20 accesses the information of the OS part 10 recorded in the DPRAM 30 to analyze the load information on the OS part 10 side and the utilization rate for the wait rate queue. As follows.

If the load of the control unit 11 of the OS part 10 accessed from the DPRAM 30 in the IPC control part 20 current and each step load is 980,840,810,780 (40 sec, 200 sec, 1 sec, 5 sec), the value of each level. Becomes 5,2,2,1, and if you apply weights, it becomes 2 (5-3), 0 (2-2), 1 (2-1). It becomes the load level of the control unit.

If the interprocessor communication message data maintains a higher level, the packet counter applies this value when the rate adjustment request is made.

Therefore, the degree to which the OS part 10 can process the interprocessor communication message data is maintained at level 2, that is, {800,6,4}. Therefore, the corresponding slide counter and packet counter are provided to the counterpart. Transmits and requests transmission and reception of communication message data between processors at a corresponding transmission rate.

At this time, the counterpart system maintains the requested transmission rate, that is, the control unit load degree '800' of the OS part, the slide counter '6', and the packet counter '4' to perform inter-processor communication.

As described above, the present invention analyzes the state information of OS parts in its own system in interprocessor communication simultaneously communicating with multiple counterpart systems, and requests the partner system to adjust the transfer rate of interprocessor communication message data. Loss of power is eliminated to provide reliability.

In addition, stability of operation is provided because the performance of the self and the counterpart system processor is kept stable in interprocessor communication, thereby eliminating the load on the processor.

Claims (6)

In the inter-processor communication control method, Detecting the state information of the OS part in the own system in real time and transmitting the same to the IPC control part; Analyzing, by the IPC control part, state information of an OS part to determine whether adjustment of the communication rate between processors is required; And determining a transmission rate that can be processed by the OS part when the adjustment of the transmission rate between the processors is required, and requesting an adjustment of the transmission rate from a counterpart system. The method according to claim 1, And the state information of the OS part includes load information of data analysis processing means and usage information of a queue queue. The method according to claim 1, The state information of the OS part transmitted to the IPC control part, the current value and the average value of each step is transmitted simultaneously, characterized in that the inter-processor communication control method. The method according to claim 1, When the IPC control part requests the other system to adjust the transmission rate, the information on requesting the adjustment of the slide range and the packet counter is transmitted in response to the message acknowledgment that the other system inquires in the sliding window flow control. A method for controlling inter-processor communication, comprising requesting adjustment of a data rate. delete The method according to claim 4, When the transmission rate is adjusted by adjusting the packet counter, a message to be transmitted to a counterpart system of the same destination is packed in a packet and transmitted, but a plurality of messages are packed in one packet and transmitted according to the packet counter value. Inter-processor communication control method characterized in that.