KR100324018B1 - Semiconductor memory and its multibit test method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory for performing a multi-bit test, wherein the semiconductor memory in which the multi-bit test is performed comprises: a data input buffer for inputting data and outputting a write data signal and a multi-bit test data signal, respectively; A write multiplexer for selectively inputting the write data signal or the multi-bit test data signal in response to an input of a multi-bit test enable signal and outputting the write data signal to a data input / output line and one cell having four adjacent column addresses; Equipped with four DQ pins that allow data to be written by matching 1: 1, allowing direct control by matching DQ 1: 1 with cells corresponding to adjacent columns, enabling efficient multi-cell leakage current and fault Test time with bit testing and improved fault coverage There is an effect that can implement a memory device that is multi-bit test to reduce the time.

Description

Semiconductor memory and its multibit test method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory for performing a multi-bit test, and more particularly, to a semiconductor memory and a multi-bit test in which an efficient multi-bit test is performed against cell to cell leakage and disturbance. It is about a method.

In the case of a semiconductor memory device such as a dynamic RAM, data read and write operations must be precisely performed. For this purpose, a single fail on a chip must not exist. . However, as the number of cells integrated in a single chip increases to more than tens of millions due to the trend of ultra high integration, the possibility of the failing is relatively higher despite the development of the manufacturing process. If such a fail is not accurately tested, reliability as a semiconductor memory device cannot be secured.

Therefore, device test technology has advanced a lot. In particular, device test technology is important to reliably test, but it must be able to test tens of millions of cells at high speed. In particular, shortening the development time of semiconductor memory devices and shortening of test time until shipment of the product directly affects the cost of the product. Therefore, shortening the test time is a very important issue in production efficiency and competition among manufacturers. Doing. Therefore, parallel test technology has been proposed to reduce test time, and multi-bit test is possible from this.

If you look at this in detail as follows.

The accompanying Figure 1 shows a block diagram of a 64M dynamic RAM. In FIG. 1, eight blocks consisting of 512 rows and 256 columns are combined to form a 1M block, and 16 of these 1M blocks are combined to form a 16M block, and the four 16M blocks are combined to form 64M. Shows.

FIG. 2 illustrates a global I / O line method of 64M dynamic RAM, in which the left 32M blocks are divided by 8M blocks by block addresses AY11 and 12. The 8M block is divided into 4M blocks by the AX12 and the 4M blocks by the AY7. In addition, data for four adjacent cells bound to one column by AY89 is divided. In the 16M block, there are 32 GDB S / A, global data bus sense amplifiers, and 32 write driver pairs. In the left 32M block, 64 are connected to 16 I / O lines (rwd lines). . Although 64 GDB lines are grouped four by one in 16 I / O, in each case, they are controlled by the block address so that no data collision occurs. rwd0-ll and rwd0-lr are data from each of the 8M blocks divided by AY10, and this pair corresponds to DQ0. The left 16 rwd lines go to the Read MUX of each of the eight DQs, creating eight RDO lines, and the eight RDO lines are connected to eight DQs. Similarly, the right 32M block has the same structure as the left.

On the other hand, the structure is complicated by normal 8K refresh, 4K refresh cycle, 4K x8, x16 mode and parallel test mode 8K refresh, 4K refresh. This is because the combination of x4, x8, and x16 modes must be satisfied according to the cycle. The left 16 rwd lines are connected to the read multiplexer READ MUX and the light multiplexer WRITE MUX of each of the DQs on the left 0,1,2,3,4,5,6,7 of the 16 DQ pads, and are connected to x4, x8, x16. Data input buffer compressed by DC signal x16, x8, x4 and data output buffer are used to branch all the data, so all 16 DQs are used at x16 and DQ 0,2,4 at x8. If 8,6,9,11,13,15 is x4, data can be inserted and subtracted into 4 of DQ 0, 4, 11, 15.

Fig. 3 shows the I / O MUX structure of DQ0 to 3 of 64M DRAM. In FIG. 3, 16 DQs are grouped into 4 units to form a MUX structure. Four pairs of rwd0-3 are connected to four MUXs (WMUX), eight Read MUXs (RMUX), and four XORs (for parallel test). Therefore, when writing, it is decoded according to x16, x8 and x4 through the compressed data input buffer Din0 ~ 3 and input into WMUX and selected according to block address gax12, gay89, gayab and loaded on the rwd line. Again, according to the global I / O scheme of FIG. 2, each cell block is written to a cell by a write driver (WD-Driver). (The output of the WMUX is divided into two blocks, AY10 and AY10B. Data from each cell block is loaded on the rwd line according to the global I / O scheme and entered through the RMUX input and read through the data output buffer selected and compressed at the block addresses gax12, gay89, and gayab. Parallel test, on the other hand, runs in x32 mode, with all the data on the 32 left and right rwd lines. A pair of rwd lines are compared in XOR with data from AY10 and AY10B blocks. As shown in FIG. 3, when four XORs are bundled and x16, a pair of rwd lines are compared in each XOR to output a logic "low" if failing (if data is different) and pass (passing each other). Output the logic "high". And at x8, the paired data from xOR3 to rwd3 is entered into nand-in of XOR2 through nor2-out, and compared again with the data from rwd of XOR2, and loaded into line rdo2 via rdo-test2 to data output buffer 2. Exit and compare the paired data of rwd1 from XOR1 to nor-in of XOR0 through nor1-out and compare the data from rwd0 of XOR0 to be loaded on line rdo0 through rdo-test0 to the data output buffer Dout0. At x4, on the other hand, a pair of compared data from XOR3 to rwd3 enters nand-in of XOR2 via nor2-out, back to nand-in of XOR0, and goes back to nand-in of XOR0, and a pair of rwd1 at XOR1. The compared data comes into nor-in of XOR0 via nor2-out. Therefore, XOR0 compares the paired data of rwd0 and the paired data of rwd1 and compares the data of rwd2 and rwd3 again and outputs logic "high" for pass and logic "low" for fail. -test0 is loaded on the rdo0 line and exits to the data output buffer Dout0.

FIG. 4 is a pair of rwd lines (rwd-) by forming an exclusive-OR circuit, that is, an XOR circuit, using two NOR gates (2, 4), one NAND gate (6), and one inverter (8) as an XOR circuit. 10b, rwd-10) shows a comparison of each other. At this time, if the pair of rwd lines (rwd-10b, rwd-10) are the same, logic "low" is outputted, and if different, logic "high" is outputted. However, in DQ0, nor-in = "low" and nand-in = "high" are fixed. Finally, outgoing rd0 outputs "high" if it passes and "low" if it fails. This maintains the same phase when output to the data output buffer. In addition, a pt (parallel test) signal is input to the XOR circuit when the parallel test is performed.

In FIG. 3, the RMUX and the RDO are connected to the same line in the lead path, but in the normal read operation, the XOR circuit is disabled and only the RMUX is enabled, so that data from the RMUX is rdo. In parallel testing, RMUX is disabled and XOR is enabled for parallel testing so that the compared data is loaded on the rdo line.

Conventional multibit tests represent this parallel test.

5 is a layout view of I / O in all cell blocks of a semiconductor memory device. Adjacent columns are arranged in the form of I / O <0: 3>, <4: 7>, <8:11>, and <12:15> for one Yi. When testing 8 dies at a time using Octal card (Probe card), the number of DQ that can take one die is limited to 4 so if you test with parallel test x4 The data of four adjacent columns for one Yi, which can identify the shape of a cell or the fault between cells even if the data is loaded on 32 rwd (I / O) lines by operating as x32, is one of four DQ0, 4, 11, 15 Since only one DQ comes out (refer to FIG. 3 above, 8 pairs of rwd0, rwd1, rwd2, rwd3 at read time are compared in four XORs of DQ0,1,2,3 and come out as DQ0). You won't be able to see the liver's risk or disorder.

As a result, the conventional multi-bit test method decodes two lower column address bits and selects four columns therefrom. Therefore, since four columns selected in this way are tied to the same input / output PIN DQ, the leakage current and disturbance between cells in the four columns cannot be tested. there was. In addition, the fault coverage is relatively low, which makes it difficult to apply the multi-bit test method directly to production test.

Accordingly, an object of the present invention is to provide a semiconductor memory and a multi-bit test method thereof in which an efficient multi-bit test is performed on leakage current and inter-cell leakage between cells.

It is another object of the present invention to provide a semiconductor memory and a multi-bit test method thereof in which a multi-bit test is performed to reduce test time while improving fault coverage.

1 is a block diagram of a typical 64M dynamic ram,

FIG. 2 is a diagram illustrating a global I / O structure in FIG. 1;

3 is a view showing an I / O MUX structure in FIG.

4 is a view showing the XOR circuit structure in FIG.

5 is a view showing an I / O arrangement in a cell block;

6 illustrates a multibit test write and lead path,

7 is an embodiment of a data input buffer according to the present invention;

8 is an embodiment of a light multiplexer according to the present invention;

9 is an embodiment of a multiplex multiplexer according to the present invention;

10 is a simulation waveform diagram of FIG. 9;

11 is an embodiment of rdo-mux in accordance with the present invention.

The semiconductor memory subjected to the multi-bit test according to the present invention for achieving the above object is a data input buffer for inputting data and outputting the write data signal and the multi-bit test data signal, respectively, and the input of the multi-bit test enable signal In response, the write multiplexer selectively inputs the write data signal or the multi-bit test data signal and outputs the data signal to the data input / output line and the cells having four column addresses adjacent to each other in a 1: 1 manner. It is characterized by a semiconductor memory having four DQ pins to enable, directly matching the cells corresponding to the adjacent columns with DQ 1: 1.

In the above configuration, it is characterized by further comprising four input comparators for determining the pass and fail of the data on the data input and output lines.

In the above arrangement, the output data of the parallel test and the output of the multi-bit test are prevented from colliding, and further comprising means for adjusting the phase of the data.

The present invention also provides a data input buffer for inputting data to output a write data signal and a multi-bit test data signal, and in response to the input of the multi-bit test enable signal, the write data signal or Multi-bit test data signal is selectively inputted by the multiplexer for data transmission to the data input / output line, and the four DQ pins match 1: 1 with cells having four column addresses adjacent to each other to enable writing of data. The method may be a multi-bit test method of a semiconductor memory, characterized in that a cell is directly controlled by matching a cell corresponding to an adjacent column with a DQ in a 1: 1 ratio.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

The structural principle of the present invention is explained.

During the test, 8 dies are tested at a time by using an octal card or an probe card. Since the number of DQs that can take one die is limited to four, four DQs are adjacent to all 64M blocks. You should be able to control four columns directly. Since the match between the cell block of the 64M dynamic ram and the I / O is the same as in FIG. 1 described above, in the present invention, if the DQ 0, 4, 11, and 15 are used, the remaining I / O is DQ 0, 4, 11, 15 and 1, respectively. : 1 Must match. This allows data to be written to DQ 0, 4, 11, and 15 so that each cell block (4M) can be written and data is written to 32 rwd lines (I / O lines) when reading the written data. 32 rwds are divided into 4 comparators and compared by XOR logic. When the same data is read, the logic 'high' or '1' is passed. If any other data is read, the logic 'low', Failed to '0' and exported to DQ 0, 4, 11, 15.

I'll look at it in detail.

In the present invention, it is possible to directly control the I / Os between adjacent columns by separating them with four DQs 1: 1. Since the DQ of the probe card is limited to four, we will use DQ0, 4, 11, and 15, which are used at normal x4.

Referring to FIG. 5, the cell block is expressed in units of 4M blocks, and four I / Os are included in one block, that is, <0: 3>, <4: 7>, <8:11>, and <12:15>. DQ0, 4, 11, 15 are used to match DQ0, 1, 2, 3 with DQ0, 4, 15, 11, and <4: 7>, <8:11>, and <12:15> Match DQ0, 4, 15, 11 The order of DQ0, 4, 15, 11 is pad in order from top to bottom of the full chip, and the rwd line in the left 32M block and the rwd line in the right 32M block are symmetrical. The I / Os in each block are selected from GDB S / A (Global Data Bus Sense Amp.) By gay89 and displayed on the rwd line. These data are adjacent columns that can be simultaneously released by a single Yi. I / O per 4M block is matched to DQ0, 4, 15, and 11 in total 64M, so they can be tested at the same time, and each adjacent cell can be controlled by a different DQ to prevent leakage current or fault between cells. You can check it.

To this end, the semiconductor memory subjected to the multi-bit test according to the present invention includes a data input buffer for inputting data and outputting a write data signal and a multi-bit test data signal, and in response to the input of the multi-bit test enable signal. A write multiplexer that selectively inputs a write data signal or a multi-bit test data signal and outputs the data signal to a data input / output line, and 4 to enable data writing by matching 1: 1 with cells having four column addresses adjacent to each other. It is characterized in that it is a semiconductor memory having DQ pins and allowing direct control by matching a cell corresponding to an adjacent column with DQ 1: 1.

And four input comparators for determining the pass and fail of the data carried on the data input / output lines, and means for preventing the output data of the parallel test from colliding with the output of the multi-bit test and adjusting the phase of the data.

FIG. 6 shows a write path and a read path in a multi-bit test. In the light path, the data from DQ0, 4, 15, 11 should go to 16 WMUX, and if 4 DQs each become I / O of 4M block, the data for DQ0 enters DQ0's data input buffer and DQ0, 4 , Go to 15, 11, DQ4 data to DQ1, 5, 14, 10, DQ15 data to DQ2, 6, 13, 9, DQ11 data to DQ3, 7, 12, 8. Therefore, the data of DQ0, 4, 15, 11 is written to each cell block.

7 shows an embodiment of a data input buffer (din buffer). In FIG. 7, wdi is a data line for a normal light path, and multibit test uses mwdi, which is not used separately from the existing normal path. Mwdi added one more inverter to reverse the phase of wdi.

8 is selected by the MBT signal in the write multiplexer WMUX to distinguish normal data from multi-bit test data.

The lead path compares the data on 32 rwd lines by creating four mr-mux comparators separate from the normal lead path or the lead path for parallel testing. Since 32 rwd lines must be compared to each other and exported as DQ4, mr-mux is 4 and goes to data output buffers Dout0, 4, 11, and 15, respectively. The first mr-mux contains 4 pairs of rwd 0, 15, 4, and 11, compared to XOR, and exported as mrdo0. Similarly, there are four pairs of rwd2, 13, 6, and 9 for the input of the second mr-mux, four pairs of rwd1, 14, 5, and 10 for the third mr-mux, and rwd3, 12, 7, 8 for the input of the fourth mr-mux. 4 pairs come in. This is a rwd line which is divided into DQ0, 15, 4, and 11 each of write data and contains rwd lines carrying the same data.

FIG. 9 is a configuration in which four XOR circuits used in parallel testing are combined with the mr-mux circuit as a means for preventing the output data of the parallel test and the output of the multi-bit test from colliding with each other. In the drawing, since the solid block represents one XOR circuit and the pair of rwd lines going out to WMUX at the time of writing should be the same data, the pairs of rwd lines are compared and the logic "low" is different and the logic "high" is different. Thus, a comparison of a pair of rwd3 (com1) is performed by comparing the data of a pair of rwd2 (com2) and Noah (NOR), and a comparison of a pair of rwd1 (com3) and a pair of rwd0. compare (com4) to make com6, which again compares to com5 to make com7. In com1, the logic is "low" if they are the same, the logic is "high", but the final output mrd0 changes its phase through the gates of NOR, NAND, inverter, etc. Export logic "low". mr-mux is preferably arranged separately in consideration of the layout area.

FIG. 10 shows that mrd0 is "low" (fail) when data is different from logic "high" or logic "low" in any pair of rwd as a result of simulating mr-mux. Data output buffers 0, 4, 11, and 15 also have rdo-mux, which goes into parallel test (wcbr mode) and enters multi-bit test after 128μsec delay due to the circuit configuration. Because it is enabled and uses the same rdo line, it is to break the data path of parallel test and to export multi-bit test data to avoid data collision.

FIG. 11 selects rdo-mux as normal transmission data rdob and multibit test data mrdo as transmission gates by the multi-bit test enable signal stst2b. NOR gates were used to match the stst2b and mrdo phases.

As described above, in the conventional multi-bit test (parallel test), data of I / O lines corresponding to adjacent columns in one Yi are compared through a comparator and output as only one DQ. . Therefore, despite the benefits of operating in x32 mode, we were not satisfied with the test results. However, the present invention is much more efficient than the conventional method because it directly controls by matching the cell corresponding to the adjacent column with DQ 1: 1.

Although the foregoing has been described with respect to embodiments of the present invention, those skilled in the art will appreciate that various implementations are possible within the scope of the technical idea of the present invention.

As described above, the present invention has the effect of implementing a multi-bit test that is efficient in the inter-cell leakage current and failure, and the multi-bit test to shorten the test time while the fault coverage is improved.

Claims (6)

In a semiconductor memory, A data input buffer for inputting data and outputting a write data signal and a data signal for multi-bit test, respectively; A write multiplexer for selectively inputting the write data signal or the multi-bit test data signal in response to an input of a multi-bit test enable signal and outputting the write data signal to a data input / output line; With four DQ pins that allow 1: 1 writes of cells with four column addresses adjacent to each other, enabling the writing of data, A semiconductor memory in which a multi-bit test is performed, in which a cell corresponding to an adjacent column and a DQ are matched 1: 1 to be directly controlled. The method of claim 1, And a four input comparators for determining a pass and a fail of the data loaded on the data input / output lines. The method of claim 2, And a means for preventing the output data of the parallel test from colliding with the output of the multi-bit test and for adjusting the phase of the data. In a semiconductor memory, The data input buffer for inputting data outputs the write data signal and the data signal for multi-bit test, respectively. In response to the input of the multi-bit test enable signal, the write multiplexer selectively inputs the write data signal or the multi-bit test data signal to a data input / output line, Four DQ pins match 1: 1 with cells with four column addresses adjacent to each other, enabling writing of data, A method of testing a multi-bit semiconductor memory according to claim 1, wherein the cell corresponds to an adjacent column and the DQ is 1: 1. The method of claim 4, wherein A multi-bit test method of a semiconductor memory for determining the pass and fail of the data on the data input and output lines through four input comparators. The method of claim 5, And a means for aligning the phases of the data to prevent the output data of the parallel test from colliding with the output of the multi-bit test.