KR100320450B1 - Receiver operation status detection device of high-definition active receiver - Google Patents

Abstract

The present invention detects an error in the current reception state at the receiving unit of the receiver (HDTV), and informs the HDTV decoder at a later stage of the error by preventing the malfunction of the decoder stage and appropriately adjusting the screen state. The present invention relates to a receiver operation state detection apparatus of a high definition TV receiver (HDTV).

Since the conventional HDTV receiver only processes the received signal and supplies it to the HDTV decoder 10, it does not detect an error on the state of the received signal or transmits the detected information to the HDTV decoder 10. In this process, data received incorrectly on the screen is displayed as it is without filtration, thereby degrading the picture quality and quality.In addition, the receiver continues processing the signal even when the wrong TV signal is received due to severe noise during HDTV reception. Since the HDTV decoder that received this data is operated and displayed on the screen, it causes an error, a deterioration in image quality, and a deterioration in the quality of the receiver that operate the receiver without verification of the HDTV reception status.

The present invention detects the presence of a received HDTV signal in the HDTV receiver and informs the HDTV decoder when the HDTV signal is not received so that the HDTV decoder displays a specific screen stored in the memory, or on the processing path of the received HDTV signal. If the wrong TV signal is detected by the noise, the HDTV decoder can notify the HDTV decoder so that the HDTV decoder can display a clear screen without previous errors. to provide.

Description

Receiver operation status detection device of high definition TV receiver (HDTV)

The present invention detects an error in a current reception state in a receiver of a high definition TV receiver (HDTV) and informs an HDTV decoder at a later stage of the error, thereby preventing malfunction of the decoder stage and appropriately adjusting the screen state. The present invention relates to a receiver operation state detection apparatus of a high definition TV receiver (HDTV).

G A. (Grand Allience) As shown in FIG. 1, the configuration of the HDTV receiver according to the HDTV specification includes a tuner 1 that performs channel tuning of a broadcast signal and a channel tuned by the tuner 1. Presence of adjacent channel interference by receiving the outputs of the FPLL and analog digital converter 2 and the FPLL and analog digital converter 2 which are in charge of frequency and phase locked loop processing and analog / digital conversion processing of a broadcast signal. Comb filter (3) for determining and combing or passing through the filter, and outputting the output of the comb filter (3) to the ghost signal and the transmission channel by multipath. TCM of the transmitting end by receiving the output of the phase corrector 5 for compensating for distortion, the phase corrector 5 for correcting a phase error by receiving the output of the imager 4, and the output of the phase corrector 5. Viterbi algorithm, the reverse of the Trellis Coded Modulation process Of the decoder 6 for restoring symbol data, the deinterleave circuit 7 for receiving a block de-interleave output from the decoder 6, and the deinterleave circuit 7. An RS decoder 8 which receives the output and performs Reed-Solomon decoding, a derandomizer 9 which de-randomizes the output of the RS decoder 8, The HDTV decoder 10 which receives the output of the de-randomizer 9 and decodes it into a video signal displayed on the screen, receives the outputs of the FPLL and the analog digital converter 2 and receives a system clock and various synchronization signals. It consists of the clock generation part 11 which finds and supplies to each part of a circuit.

The HDTV receiver receives and processes video data, audio data, and other data of a TV at a transmission rate of 10.76M symbol / sec through a 6MHz channel using an 8VSB method.

The tuner 1 performs channel tuning to demodulate the HDTV reception signal to an intermediate frequency of 94 MHz, which is VSB filtered by the SAW filter, and then input to the FPLL and the analog digital converter 2, and the FPLL and analog digital. The converting unit 2 performs FLL and PLL operations that follow a frequency and follow a phase to recover a VSB carrier, and convert the TV signal converted to a base band into a digital signal by this operation. Will print.

Using the output signal, the clock generator 11 finds various synchronization signals and system clock clk and supplies them to the digital signal processing part after the analog digital converter 2 and the comb filter 3.

The comb filter 3 determines whether there is an adjacent channel NTSC interference by using a training sequence of data field sync, and when there is no interference between adjacent channels, an input signal is detected. Is passed through as it is, and supplied to the moving unit 4, and when there is interference from adjacent channels, the input signal is com-filtered and supplied to the moving unit 4.

The equalizer 4 compensates the distortion of the ghost signal and the transmission channel by the multipath with respect to the input signal and supplies it to the phase correction unit 5, and the phase correction unit 5 supplies the FPLL and The phase error (Phase error) that the analog digital conversion unit 2 cannot correct is corrected and output, and the output signal is input to a decoder Deleter 6 at a later stage.

The decoder 6 decodes the input data by the Viterbi algorithm, which is a reverse process of the Trellis Coded Modulation process, and recovers 2 bits of symbol data per symbol, and converts the symbol data into a symbol: byte ( Symbol to Byte) and a block deinterleave circuit 7, a (208,188) RS decoder 8 and a de-randomizer 9 having t = 10, to supply the HDTV decoder 10 to receive the HDTV signal. In conclusion, the HDTV decoder 10 decodes the input data to be displayed on the screen and outputs the decoded data.

However, the HDTV receiver only processes the received signal and supplies the signal to the HDTV decoder 10, and detects an error of the state of the received signal, or sends the detected information to the HDTV decoder 10. I can't.

In other words, from the standpoint of the HDTV decoder 10, all the input data is received as the TV data without being recognized whether the TV data being received is the correct data or not and decompressed and displayed on the screen. Data received incorrectly is displayed as it is without filtration, which degrades image quality and quality.

For example, when the user turns on the TV during a time when no broadcasting station is broadcasting, or when the broadcasting is terminated while watching TV, the signal of the receiver is set even when the user sets a channel that is not broadcasting while searching for a TV channel. Processing continues and the HDTV decoder that accepts this data is activated and displayed on the screen.

In addition, even if a wrong TV signal is received due to severe noise during HDTV reception, the receiver continues processing the signal, and the HDTV decoder receiving this data is operated and displayed on the screen, thus verifying the HDTV reception status. This will cause the receiver to operate without error, degrading the picture quality and degrading the product quality.

The present invention detects the presence of a received HDTV signal in the HDTV receiver and informs the HDTV decoder when the HDTV signal is not received so that the HDTV decoder displays a specific screen stored in the memory, or on the processing path of the received HDTV signal. If the wrong TV signal is detected by the noise, the HDTV decoder can notify the HDTV decoder so that the HDTV decoder can display a clear screen without previous errors. For the purpose of providing it.

FIG. 2 illustrates a circuit diagram of a receiver operation state of a high definition TV receiver (HDTV) of the present invention and an HDTV receiver according to the present invention, which achieves the above object. The same partial-tuner (1) as shown in FIG. Regarding the receiving unit A, including the same, the same reference numerals will be used and the description thereof will be omitted.

As shown in FIG. 2, the present invention receives an HDTV broadcast channel signal from the tuner 1, the FPLL, and the FPLL unit of the analog digital conversion unit 2, detects the presence or absence thereof, and detects the presence or absence of the HDTV decoder. 10) and a channel signal for supplying or blocking control of the clock clk of the clock generator 11 to the system clock CLK of each part of the circuit of the receiver A according to the presence or absence of a signal of the HDTV broadcasting channel. Detection means (12).

That is, the channel signal detecting unit 12 receives the VSB filtered signal through the output-SAW filter of the tuner 1, and when there is an HDTV channel signal, the channel signal detecting unit 12 detects the energy of the input signal and thus the clock generator 11. By passing through the clock clk, the system clock CLK is supplied to the circuits of the receiver A so that the HDTV channel signal reception processing can be performed.

However, when there is no HDTV channel signal when passing through the output-SAW filter of the tuner 1 and receiving the VSB filtered signal, energy of the input signal is not detected. By shutting off the clock of (clk) and terminating the system clock (CLK) supply, the circuits of the receiver (A) are not operated, and the detection signal that there is no TV signal is input to the HDTV decoder (10). The HDTV decoder 10 receiving the detection signal causes a specific screen stored in memory to be displayed in advance.

As another embodiment of the 1HDTV broadcast detection method, the channel signal detecting means 12 receives the AFC low pass filtering output signal of the FPLL routine, and detects the input signal when the HDTV channel signal is present. By passing the clock (clk) of the () as it is to supply the system clock (CLK) to each circuit of the receiving unit (A) to receive the processing of the HDTV channel signal.

However, when there is no HDTV channel signal when the AFC low pass filtered signal of the FPLL routine is input, energy detection of the input signal is not performed. At this time, the channel signal detecting means 12 blocks the clock of the clock generator clk. By stopping the system clock (CLK) supply, the circuits of the receiving unit (A) do not operate, and the detection signal that there is no TV signal is input to the HDTV decoder 10 as described above, and the HDTV decoder receives the detection signal. The display 10 displays a specific screen stored in memory in the initial screen.

FIG. 3 shows a circuit configuration of an embodiment of the channel signal detecting means 12 of the present invention as described above, and a configuration of a tuner and a peripheral circuit of the FPLL unit to which the same is applied.

That is, as shown in FIG. 3, the signal tuned by the tuner 1 is VSB filtered by the SAW filter 1a and amplified by the IF amplifier 1b to detect the energy of the IF signal to detect the presence or absence of an HDTV signal. Low-pass to detect the presence or absence of an HDTV signal by low-pass filtering the output of the amplification / limiter 2f that amplifies and level-limits the signal filtered by the IF detector 12a to detect and the AFC low pass filter 2e of the FPLL routine. A logic circuit 12c for receiving the output of the pass filter 12b, the IF detector 12a and the low pass filter 12b, and supplying the HDTV decoder 10 with a result of determining whether the HDTV signal is present or not; The switching unit 12a is turned on or off in accordance with the output of the circuit 12c to supply the clock clk of the clock generator 11 to the system clock CLK or to cut off the control.

The logic circuit 12c includes an AND gate, and the switching unit 12a includes a switching element that is on when the output of the AND gate is high and off when the output of the AND gate is high.

In FIG. 3, AGC is an automatic gain control signal, 1c is a frequency synthesizer for synthesizing channel tuning data and supplying a first local oscillation signal (1ST LO) to the tuner 1, 2a is an existing oscillator, and 2b is A shifter for phase shifting the output of the reference oscillator 2a by 90 degrees, 2c is a mixer that outputs an I signal by mixing the output of the phase shifter 2b and the output of the IF amplifier 1b, and 2d is a reference oscillator ( A mixer which outputs a Q signal by mixing the output of 2a) and the output of IF amplifier 1b, and 2g is an error signal for applying a PLL by mixing the output of amplification / limiter 2f and the output of mixer 2d. Is an APC low pass filter for low pass filtering the output of the mixer 2g for APC, and 2i generates a second local oscillation signal 2ND LO according to the output value of the low pass filter 2h. Is a voltage controlled oscillator input to the tuner 1.

The operation of the channel signal detecting means 12 configured as described above is as follows.

First, the operation of the tuner and the FPLL routine will be briefly described. The frequency synthesizer 1c receiving the channel tuning data generates an appropriate local oscillation frequency signal to the tuner 1 and receives the local oscillation signal. 1) performs channel tuning to down convert the received signal to a signal in the 44 MHz band.

The broadcast signal of the tuned channel down-converted by the tuner 1 is inputted to the SAW filter 1a and VSB filtered and output as an intermediate frequency (IF) signal. Since the IF signal is weak, the IF amplifier 1b of the rear stage is weak. Amplified).

The signal amplified by the IF amplifier 1b is output as an I signal from the mixer 2c together with a signal having a 90 degree phase shifted through the phase shifter 2b in the reference generator 2a, and this I signal is an AFC low pass filter. Filtered at 2e and then amplified and level-limited at amplification / limiter 2f and output as a waveform shaped signal.

The AFC low pass filter 2e is composed of a resistor R and a capacitor C as shown in FIG. 4 so that vo / vi = 1 / [1 + jωRC], phase (θ) = tan-1 [( -[omega] RC) / 1] has the frequency characteristics as shown in (a) of FIG. 5 and the phase characteristics as shown in (b) of FIG.

The signal output from the amplification / limiter 2f is inputted to the mixer 29 together with the Q signal obtained through the mixer 2d and the output of the reference oscillator 2a and the output of the IF amplifier 1b to provide automatic phase control ( The APC error signal is low-pass converted by the APC low pass filter 2h to control the oscillation frequency of the voltage controlled oscillator 2i to apply the APC to the tuner 1.

Therefore, if there is an HDTV channel signal, there is an output of the IF amplifier 1b. Therefore, the output of the IF detector 12a that receives the output of the IF amplifier 1b becomes high, and if there is no HDTV channel signal, the IF is output. Since there is no output of the amplifier 1b, the output of the IF detector 12a goes low.

That is, when the HBTV viewer turns on the TV, the broadcasting station is not broadcasting the HDTV, or when the viewer is watching one TV channel and another channel is in the middle, or when the broadcast is terminated, the broadcast is terminated. There is no HDTV signal at the output of the IF amplifier 1b.

Therefore, when there is no HDTV signal, the output of the IF detector 12a-IF Power Detctor-becomes low to detect the presence or absence of the HDTV broadcast signal.

The presence or absence of the HDTV broadcast signal is detected by the low pass filter 12b using the output of the AFC amplification / liter 2f together with the above-described IF detector 12a, and the IF detector 12a and the low pass filter l2b. By multiplying the two outputs by the logic circuit 12c to detect the presence or absence of the HDTV signal, more reliable signal detection is possible.

That is, the output of the AFC low pass filter 2e and the output of the amplification / reamer 21 are 90 degrees out of phase with the signal I and phase shifter 2b input to the FPLL rope as shown in FIG. When the frequency difference with the signal of the changed reference oscillator 2a is large (that is, when there is no HDTV broadcasting signal, or ), When the output of the low pass filter 12b receiving this signal becomes '0' (low) and the frequency difference disappears (that is, when there is an HDTV broadcasting signal, ), The output of the low pass filter 12b receiving this signal becomes high to a value other than '0', thereby detecting the presence or absence of an HDTV signal.

As described above, when the outputs of the IF detector 12a and the low pass filter 12b are logically multiplied by the logic circuit 12c, the output of the logic circuit 12c becomes high when there is an HDTV broadcast signal, and when there is no output. The output of the logic circuit 12c goes low.

The output of the logic circuit 12c is transmitted to the HDTV decoder 10 and used as an operation signal such as displaying an initial screen of a pre-stored HDTV on the screen, and the output of the logic circuit 12c is a switching unit 12a. If the HDTV broadcast signal is also input, the switching unit 12a is turned on to supply the output clk of the clock generator 11 to the receiver A as the system clock CLK, and the HBTV broadcast signal is If not, the switching unit 12a is turned off to stop the operation of the various digital processing units of the baseband and the HDTV decoder except the IF processing unit of the HDTV receiver.

In this way, the receiver or HDTV decoder can be operated without a broadcast signal, eliminating the problem that the system may fall into an error state and reducing power consumption.

When the output of the IF amplifier 12a in FIG. 3 is directly supplied to the HDTV decoder 10 and supplied as a switching control signal to the switching unit 12a-the IF detector 12a and the switching unit 12a The embodiment constituting the channel signal detecting means 12 alone, or the case where the output of the low pass filter 12b is directly supplied to the HDTV decoder 10 and is supplied as a switching control signal to the switching unit 12a- An embodiment in which the channel signal detecting means 12 is constituted only by the pass filter 12b and the switching unit 12a may be implemented. In this case, since the operation is performed in accordance with the above description, redundant description thereof will be omitted.

On the other hand, Figure 7 shows another embodiment of the circuit configuration of the receiver operation condition detection apparatus of the high-definition TV receiver (HDTV) of the present invention according to the error signal output from the HDTV receiver (A) to the HDTV decoder 10, The second description and the same components are denoted by the same reference numerals and redundant description thereof will be omitted.

In the embodiment of FIG. 7, the LMS error is transmitted to the HDTV decoder 10 by performing an algorithm for searching the LMS error in the equalizer 4 together with the channel signal detecting unit 12. And a search section 4a.

In addition, the R-S decoder 8 transmits an error correction signal output when the error correction is performed to the HDTV decoder 10 so as to detect an operation state of the receiver.

In addition, if the data value input from the RS decoder 8 to the de-randomizer 9 is zero (0), it is determined that an error has occurred and the zero detection unit transmits the operation state of the receiver to the HDTV decoder 10. (13).

And a logic circuit 14 for transmitting the output of the LMS error search unit 4a, the error correction signal of the RS decoder 8, and the output of the zero detector 13 to the HDTV decoder 10, This logic circuit 14 is composed of an OR gate.

The operation according to the receiver error of the receiver operation state detection apparatus of the high definition TV receiver (HDTV) of the present invention configured as described above is as follows.

First, the equalizer 4 measures the degree of error from the signal before and after equalization by the LMS algorithm. At this point, the equalizer 4 has a large error in the signal of the baseband so that the divergence-stable state is In other words, it is a wrong operation, and it is possible to determine whether most of the data in this case corresponds to an error.

That is, the LMS error search unit 4a determines that the LMS error value is divergent when the threshold value is exceeded and the LMS error search unit 4a sends the information to the HDTV decoder 10 through the gate-logic circuit 14. By supplying, the HDTV decoder 10 displays the screen data without previous errors in an error situation.

At this time, this information is passed through the phase correction unit 5, the decoder 6, the deinterleave circuit 7 and the RS decoder 8 in order to match the signal output to the HDTV decoder 10 and its corresponding position. Delay by the signal delay during the transfer to the HDTV decoder 10 through the OR gate (14).

On the other hand, the RS decoder 8 corrects an error generated during the forward error collection (FEC) technique within a range of t = 10 due to parity of 20 bytes, which can be corrected by this technique. If an error condition that is too large (an error of 10 bytes or more out of 208 bytes) occurs, the error correction signal is not activated.

Therefore, when the error correction signal is transmitted to the HDTV decoder 10 through the logic circuit 14, the HDTV decoder 10 can determine whether the received data is in error and display the screen data before the error.

In addition, when no signal is received at all or when there is no data to be processed by the RS decoder 8 due to abnormalities in the baseband processing unit (disruption in the circuit, element disturbance, etc.) (output data value = 0), Since the zero detection unit 13 detects this and transfers the result to the HDTV decoder 10 through the logic circuit 14, the HDTV decoder 10 determines whether the received data is in error. You can display previous screen data.

That is, if the error is detected only by the error correction signals from the LMS error search unit 4a and the RS decoder 8 of the equalizer 4, the two error detection results are outputted as no error. To do this, the zero detector 13 detects the output of the RS decoder 8 at the front end of the derandomizer 9, searches whether the data in this part is all '0', and if it is '0' continuously for one frame, an error occurs. The signal is generated and transferred to the HDTV decoder 10 through the logic circuit 14.

As described above, the receiver operation state detection apparatus of the high definition TV receiver (HDTV) of the present invention can display the initial screen stored in advance in the HDTV decoder 10 when there is no broadcast signal, If an error is found in the process, the HDTV decoder 10 continues to display a screen without a previous error.

Therefore, according to the present invention, when the HDTV is turned on when the HDTV broadcasting station is not broadcasted or when a channel not used for broadcasting is selected while searching for a TV channel, a specific screen stored in the HDTV decker is displayed. At this time, the operation of circuits other than the tuner and IF processing unit of the HDTV receiver can be prevented from being performed. If an error occurs while watching TV broadcast, the HDTV receiver repeats the exact screen before the error again. By showing, it is possible to stabilize the operation of the entire HDTV, to smooth the video without interruption, and to save power consumption.

1 shows a conventional G.A. Block diagram showing circuit configuration of HDTV receiver

2 is a block diagram showing a circuit configuration of an HDTV receiver having a detection device according to the present invention.

3 is a block diagram showing a circuit configuration of an embodiment of the detection apparatus of the present invention.

4 is a circuit diagram of an AFC low pass filter in the present invention.

Figure 5 (a) is the frequency characteristic curve of the AFC low pass filter in the present invention

(B) is a phase characteristic curve of the AFC low pass filter in the present invention

6 is an AFC low pass filter and amplification / limiter output waveform diagram according to frequency deviation in the present invention.

7 is a block diagram showing a circuit configuration of another embodiment of the detection apparatus of the present invention.

Explanation of symbols for main parts of the drawings

One ; Tuner 2; FPLL and analog digital converter

3; Comb filter 4; Fairy tale

4a; LMS error search unit 5; Phase correction unit

6; Trellis decoder 7; Block deinterleave circuit

8 ; R-S decoder 9; Delander

10: HDTV decoder 11; Clock generator

12; Channel signal detecting means 12a: IF detector

12b; Low pass filter 12c; Logic Circuit (End Gate)

12d; Switching unit 13: zero search unit

14: logic circuit (or gate)

Claims (5)

A tuner (1) which newly outputs an HDTV broadcasting signal and outputs an IF signal, and receives the output of the tuner (1), FPLL and digital conversion, comb filtering according to interference of adjacent channels, equalization processing, phase correction, trellis decoding, A receiving unit A which transmits a received HBTV signal to the HDTV decoder 10 by performing block deinterleave processing, RS decoding, derandomizing processing, and clock generation, an output signal of the tuner 1, and the receiving unit ( The HDTV broadcast channel signal output from the FPLL of the A) and the FPLL routine of the analog digital converter 2 is detected, the presence of the signal is supplied to the HDTV decoder 10, and the signal of the HDTV broadcast channel is supplied. Channel signal detecting means 12 for supplying or blocking control of the clock clk of the clock generator 11 of the receiver A to the circuits of the receiver A by the system clock CLK according to the presence or absence of HD television receiver, characterized in that configured to include (HD TV receiver operation status detection device. The channel signal detecting unit 12 detects the presence of an HDTV signal by detecting the energy of the IF signal by receiving a signal tuned by the tuner 1, VSB filtered by the SAW filter, and amplified by an IF amplifier. A low pass filter 12b for low frequency filtering the output of the amplification / limiter that amplifies and level-limits the signal filtered by the AFC low pass filter of the FPLL routine, and detects the presence or absence of an HDTV signal; A logic circuit 12c which receives the outputs of the IF detector 12a and the low pass filter 12b and determines the presence or absence of an HDTV signal to the HDTV decoder 10, and to an output of the logic circuit 12c. Therefore, the apparatus for detecting a receiver operation state of a high definition TV receiver (HDTV), which is configured as a switching unit (12a) which is turned on or off to supply or cut off the system clock (CLK). The method of claim 1, wherein the equalizer of the receiver A includes an LMS error search unit 4a which performs an algorithm for searching for an LMS error and delivers the result of searching for the LMS error to the HDTV decoder 10. Receiver operation state detection device of a high-definition TV receiver (HDTV) characterized in that. The high definition signal according to claim 1, characterized in that an error correction signal output when an error correction is performed in the RS decoder of the receiver A is transmitted to the HDTV decoder 10 so as to detect an operation state of the receiver. Receiver operation state detection device of a TV receiver (HDTV). The method of claim 1, wherein if the data value input from the RS decoder of the receiver A to the de-randomizer is zero (0), it is determined that an error occurs and the operation state of the receiver is transmitted to the HDTV decoder 10. Receiver operation state detection apparatus of a high-definition TV receiver (HDTV), characterized in that it comprises a zero detection unit (13).