KR100318929B1 - Clock automatic switching circuit in key phone system - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Clock Automatic Switching Circuit in Key Phone System

2. The technical problem to be solved by the invention

Implement clock automatic switching circuit with simple logic

3. Summary of Solution to Invention

A first logic gate unit configured to output a magnetic error check signal of a magnetic board as a first trunk interface card as an output error signal, and to output the output error signal as an input error signal of a taboid which is the second trunk interface card. A first switch unit for switching to output, a second switch unit for switching to a predetermined first and second logic state in accordance with the magnetic board and the bobbin, the output of the second switch unit and the input error signal A second logic gate portion for logic gating, a first buffer portion for buffering and outputting an output of the second logic gate in response to a predetermined state of the magnetic error check signal, and a predetermined value of the magnetic error check signal for the first buffer portion The second buffer unit buffers the error detection state in response to the output.

4. Important uses of the invention

All systems requiring a clock automatic switching circuit

Description

Clock Automatic Switching Circuit in Keyphone System

The present invention relates to a key phone system, and more particularly, to a clock automatic switching circuit for switching the board clock so that the mother board is automatically synchronized with the click of the T1 slave board when the click of the T1 master board is cut off.

The T1 board in the slot of the keyphone system main unit is a digital trunk interface card for interfacing with the host station. The T1 board performs clock synchronization control when the mother board of the key phone system, which is a lower system, synchronizes with a clock provided from an exchange station, which is a higher station. That is, since T1 boards are generally mounted in two or more keyphone system main units, the T1 boards are divided into master boards and slave boards, and the clock boards are synchronized with the master boards. Therefore, in case of master board failure in two or more T1 boards, a clock automatic switching circuit is provided inside the T1 board so that the clock is automatically synchronized with the slave board.

1 is a conventional clock automatic switching circuit, in which a key phone system is implemented so that a clock due to a failure of one board is automatically switched when three T1 boards BD are mounted. The clock automatic switching circuit is composed of three boards, respectively, and FIG. 1 shows the clock automatic switching circuit included in one of them.

First, the connection state between the dip switches 24, 26, and 28 and the corresponding boards BD1, BD2, and BD3 will be described. In the first board BB1, only the first dip switch 24 is connected to pins 1 and 2. The remaining second and third dip switches 26 and 28 are connected to pins 2 and 3. In the second board BD2, only the second dip switch 26 is connected to pins 1 and 2, and the remaining first and third dip switches 24 and 28 are connected to pins 2 and 3. The third board BD3 is also connected to the dip switch in this manner.

If the automatic switching circuit shown in FIG. 1 is included in the first board BD1 and the first board BB1 is set as the master board, the clock switching control operation will be described below.

In FIG. 1, only the first dip switch 24 is connected to pins 1 and 2, and the remaining second and second switches 26 and 28 are connected to pins 2 and 3. At this time, if the first board BD1 is normal, the interface card processor T1 applies the first error signal ERR1 to the first NAND gate 10 in the "H" state, and thus the first NAND gate 10 is "L". The level is applied to the input 10 of the priority encoder 16. Priority encoder 16 outputs "0" through outputs A1, A2 and A3, respectively, when "L" is applied to input 10, regardless of other signal level values applied to other inputs 11 and 12. At this time, if the signals applied to the input terminals of the priority encoder 16 are not all at the same level, it is determined that the signal is not a glitch and outputs an "H" state through the GS stage. The decoder 18 is enabled in response to the " H " state output from the GS stage, decodes the output signal level " 000 " of the priority encoder 16 through the input stages A0, A1, A2, The first board BD1 becomes the master board because the state L is output to the first switch 24.

However, when an error occurs in the first board BD1, the processor of the second board BD2 disables the buffer of the first board BD1 and then outputs the second error signal ERR2 in the normal state to the second NAND gate 12. The second board BD2 becomes the master board by outputting the "L" state through the priority encoder 16, the decoder 18, and the conducting second switch 26. If the second board fails, the third board becomes the master board in the above manner.

However, in the conventional clock automatic switching circuit described above, the number of boards supports three clicks, so that the number of logics, the types of complexities, and the number of transfer signals between the two boards must be increased. This connector connection causes a problem of saturating the signal line of the mother board.

Accordingly, an object of the present invention is to provide a clock automatic switching circuit which implements clock switching support of a key phone system with simple logic.

Another object of the present invention is to provide a clock automatic switching circuit which automatically transfers priorities of clicks in two T1 interface boards.

According to the present invention for achieving the above object, in a clock automatic switching circuit of a key phone system for mounting a first and second trunk interface card, a magnetic error check signal of a magnetic board which is the first trunk interface card is determined. A first logic gate unit for gating to output an output error signal, a first switch unit for switching the output error signal to be output as an input error signal of a bobbin of the second trunk interface card, the magnetic board and the other A second switch unit for switching to predetermined first and second logic states according to the board, a second logic unit for predetermined logic gating between the output of the second switch unit and the input error signal, and the second logic gate A first buffer unit configured to buffer an output in response to a predetermined state of the magnetic error check signal, and a predetermined output of the magnetic error check signal to the first buffer unit And a second buffer portion which buffers and outputs an error detection state in response to the output.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a clock automatic switching circuit applied to the present invention. The clock automatic switching circuit is composed of two boards, respectively, and FIG. 1 shows the clock automatic switching circuit included in one of them. One of the dip switches 24, 26 and 28 of the first board BB1 is connected to pins 2 and 3, and the dip switches 24, 26 and 28 of the second board BD2 are the other. ) Is connected to pins 1 and 2.

The first board BB1 is a board having priority and the operation of the first board BD1 will be described with reference to FIG. If the mother board normally synchronizes with the clock of the switching center, the processor of the first board BD1 applies the magnetic error check signal TIORDER as "H". Thus, the inverter 32 enables the three state non-inverting buffer 34 with the signal of the "L" state. Since the dip switches 24, 26, and 28 of the first board BB1 are connected to pins 2 and 3, the AND gate 30 is a signal of the type force terminal by pin 3 of the grounded third dip switch 28. It always outputs "L" state regardless. The " L " output of the AND gate 30 enables the tri-state inversion buffer 36 through the enabled three-state inversion buffer 34. Therefore, the magnetic error check signal TIORDER applied to the enabled three-state inversion buffer 36 is the detection signal TIDET as it is in the "H" state. Since the detection signal TIDET is output to the mother board, the mother board recognizes that the first board BB1 is operating normally.

However, when the first board BD1 operates abnormally, the magnetic array check signal TIORDER is applied in the "L" state. The magnetic array check signal TIORDER in the " L " state is inverted to the " H " state in the inverter 32, thereby disabling the three-state non-inverting buffer 34. The " L " At this time, since the three-state inverting buffer 36 is disabled by the voltage Vcc connected to the output line of the three-state inverting buffer 34, the magnetic error check signal TIORDER applied to the three-state inverting buffer 36 is " L "state is not provided to the motherboard. Therefore, the mother board controls to click-shift from the first board BD1 to the second board BD2.

On the other hand, the magnetic output error signal ERROR in the "L" state in the first board BD1 outputs the output error signal ERROUT in the "L" state by the AND gate 22. The output error signal ERROUT is output to the first end 40 of the connector via the third and second ends of the dip switch 24 and is also applied as the input error signal ERRIN of the second board BD2.

Hereinafter, an operation of the second board BB2 when the first board is broken and the second board BD2 is normal will be described. In the second board BD2, the dip switches 24, 26, and 28 are connected with pins 1 and 2. At this time, since the magnetic error check signal TIORDER of the second board BD2 is normal, it is in the "H" state, and the output error signal ERROUT of the first board BD1 is in the "L" state. The output error signal ERROUT in the "L" state is applied to one input terminal of the AND gate 30 as an input error signal ERRIN of the second board BD2. Therefore, the output of the AND gate 30 is in the "L" state.

On the other hand, the magnetic error check signal TIORDER "H" state of the second board BD2 becomes the "H" state through the inverter 32 to enable the three-state non-inverting buffer 34. Accordingly, the three state non-inverting buffer 34 enables the three state non-inverting buffer 36 to the "L" state, which is the output of the AND gate 30. Therefore, the magnetic error check signal TIORDER of the second board BD2 applied to the enabled three-state inverting buffer 36 is the detection signal TIDET as it is in the "H" state. Since the detection signal TIDET is output to the mother board, the mother board It is recognized that the second board BD2 is operating normally.

On the other hand, in the second board BD2, the magnetic output error signal ERROR outputs an output error signal ERROUT through the AND gate 22, and the output error signal ERROUT passes through the second and first stages of the dip switch 26. It is output to the second stage 42 and is also applied as an input error signal ERRIN of the first board BD1.

As described above, the present invention gives priority to a click when two T1 interface boards are mounted in the keyphone system, and automatically switches the clock source to the slave board when one of the two lines, that is, the master board, is disconnected. This is done by implementing simple logic to prevent saturation of the mother board signal lines.

1 is a conventional clock automatic switching circuit diagram

2 is a clock automatic switching circuit diagram according to the present invention.

Claims (7)

In the clock automatic switching circuit of a key phone system for mounting the first and second trunk interface card, A first logic gate unit configured to perform a predetermined logic gating on the magnetic error check signal of the magnetic board which is the first trunk interface card, and output the output error signal; A first switch unit configured to switch the output error signal to be output as an input error signal of a bobbin, which is the second trunk interface card; A second switch unit configured to switch to first and second logic states predetermined according to the magnetic board and the bobbin; A second logic gate part configured to logically gate the output of the second switch part and the input error signal; A first buffer unit configured to buffer the output of the second logic gate in response to a predetermined state of the magnetic error check signal; And a second buffer unit configured to buffer the magnetic error check signal in an error detection state in response to a predetermined output of the first buffer unit. The clock automatic switching circuit of claim 1, wherein the first switch unit comprises first and second dip switches connected to connectors connected to the bobbin, respectively. 2. The dip switch of claim 1, wherein the second switch unit is a dip switch having a first end connected to the first logic state, a second end connected to the second logic state, and a first end connected to the second logic gate part. Clock automatic switching circuit characterized in. The clock automatic switching circuit of claim 1, wherein the first buffer unit is a tri-state buffer. The clock automatic switching circuit of claim 1, wherein the second buffer unit is a tri-state buffer. In the clock automatic switching circuit of a key phone system for mounting the first and second trunk interface card, A first and gate for outputting an output error signal by end-gating a magnetic error check signal of the magnetic board of the first trunk interface card; A first dip switch configured to switch the output error signal to be output as an input error signal of a bobbin of the second trunk interface card; A second dip switch for switching to predetermined first and second logic states according to the magnetic board and the bobbin; A second and gate for ANDing the output of the second dip switch and the input error signal; A first third state buffer configured to buffer the output of the second and gate in response to a predetermined state of the magnetic error check signal; And a second third state buffer configured to buffer the magnetic error check signal in an error detection state in response to an output of the first third state buffer. The clock automatic switching circuit of claim 6, wherein the first and second dip switches are complementarily switched to each other based on the magnetic board and the tavo board.