KR100317610B1 - semiconductor device - Google Patents

Abstract

The present invention discloses a semiconductor device. According to this, in the integrated injection logic (I ² L), a pnp transistor is used as an inverter, an npn transistor is used for current injection, and these are formed by a general bipolar process. In addition, p-type diffusion layers corresponding to independent collectors of the pnp transistors are formed on the n− epitaxial layers so as to be spaced apart from the p-type diffusion layer for the base of the npn transistor.

Therefore, the present invention operates both the npn transistor and the pnp transistor in the forward direction and is formed in the same structure as that of the general bipolar process, so that a high h _fe can be obtained without increasing chip size or process difficulty. You can increase the fan out.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of increasing fanout while increasing reverse current gain of integrated injection logic (I ² L).

In general, integrated injection logic (I ² L) is a logic circuit introduced in 1972 that attempted to optimize the gate structure in terms of integration by replacing the load resistance with a pnp transistor and eliminating the need for isolation. The basic focus of I ² L is to functionally integrate the npn transistor and pnp transistor so that current is supplied from the pnp transistor directly to the base of the switching transistor. The peculiarity of I ² L is that the npn transistor is used in opposition to the normal operating state, i.e., as shown in Figure 1, where the subcollector is used as the operational emitter and the original emitter is used as the operational collector.

That is, in the conventional I ² L, as shown in FIG. 1, the n- epi layer 11 is grown on the p-type silicon substrate 10, and the substrate 10 and the pnp and npn transistors are grown. The n + buried layer 13 is formed in the region between the n− epilayers 11, and the n + diffusion layer 15 is connected to the n + buried layer 13 in the n− epilayer 11 of the region for the npn transistor. Diffused, and the p-type diffusion layer 17 is diffused to a depth such that the p-type diffusion layer 17 is not connected to the n + buried layer 13 in the region for the pnp transistor and the n- epi of the region for the npn transistor. The p-type diffusion layer 18 is diffused to a depth such that the p-type diffusion layer 18 is not connected to the n + buried layer 13 in the layer 11, and the n-epitaxial layer 11 has several n + diffusion layers 19 in the diffusion layer 18. It has a structure that spreads to a depth that is not connected.

Here, the diffusion layer 17 is an emitter of the current injection pnp transistor, and the n- epi layer 11 is used together as the base of the pnp transistor and the emitter of the npn transistor. The outer contact is used as the contact of the diffusion layer 15.

In addition, an equivalent circuit for the cross-sectional structure of FIG. 1 may be represented, as shown in FIG. 2. That is, the reference voltage Vref is applied to the emitter of the pnp transistor Q1 via the injection resistor Rinj, the collector of the pnp transistor Q1 is connected to the base of the npn transistor Q2, and the pnp transistor Q1 And the emitter of npn transistor Q2 are grounded together. In addition, an input terminal IN is connected to a node between the collector of the pnp transistor Q1 and the base of the npn transistor Q2, and each of the output terminals OUT1 and OUT2 is connected to several collectors of the npn transistor Q2. ), (OUT3) are connected.

In the conventional I ² L configured as described above, when the transistor is operated in the reverse direction, the pnp transistor Q1 and the npn transistor Q2 can be mixed together. Moreover, since the buried layer 13 is shared to all transistors and is in the ground state, no isolation diffusion layer is required between the gate and the gate. In other words, I ² L is the most versatile logic gate that requires neither resistance nor isolation.

In the conventional I ² L, the magnitude of the current supplied to the gate is determined according to the magnitude of the voltage applied between the emitter and the base of the pnp transistor Q1. That is, the current emitted from the pnp transistor Q1 is supplied to the base current of the adjacent npn transistor Q2 or the collector of the npn transistor Q2 in the on state. Thus, the emitter of the pnp transistor Q1 is called an injector after its function. At I ² L the current is supplied through the pnp transistor Q1, or the collector current of the pnp transistor Q1 varies exponentially with the base-emitter voltage, which is very wide to meet the requirements of the circuit operation. It is possible to change the current supply level in the range.

However, in the conventional I ² L, the npn transistor has a big difference that the emitter and the collector are structurally inverted compared to the npn transistor in the general bipolar process. For this reason, a large problem has arisen that the reverse current gain of the npn transistor is very small. In addition, the input terminal IN is connected to the output terminal OUT of the front end and operates as one inverter. Therefore, the pnp transistor Q1 operates as a current source of the output npn transistor of the preceding stage of the same structure. The base of the npn transistor Q2 and the collector of the pnp transistor Q1 are formed at the same potential of the input terminal IN. Under the condition that the npn transistor Q2 is on, the voltage of the input terminal IN is expressed as V _{BE (ON), npn} and also as V _{BE (ON), pnp} -V _{EC (SAT), pnp} . Can be. At this time, V _{EC (SAT), pnp} is defined as a difference between the turn-on voltages of the npn transistor Q2 and the pnp transistor Q1 and is represented by a very small value of less than 100 mV. Therefore, as shown in FIG. 3, as the value of V _{EC (SAT)} of the pnp transistor decreases, the absolute value of the collector current I _C , ?? I _C ?? decreases for a constant base current I _B. H _fe becomes low. This increases the portion of the current loss flowing to the base during the current injected into the emitter of the pnp transistor. This corresponds to the difference between the base current when the npn transistor is turned on and the collector current to be supplied in the same way at the rear stage. To overcome this difference, the h _fe of the npn transistor must be high enough. Gives severe constraints.

In the conventional I ² L, the npn transistor is used in the reverse mode, and in the general bipolar IC process, since the reverse current gain of the npn transistor shows a very low value near 1, an n + diffusion layer is formed to surround the active region to increase the reverse current gain. Therefore, various methods have been used, such as reducing leakage current, adjusting the diffusion time of the n + buried layer, adjusting the collector concentration of the npn transistor, adding process steps, and adding and changing layouts. However, all these methods do not provide a fundamental solution to the conventional problem, but remain a little complementary. This meant a limitation of fanout and led to the addition of new current sources, eventually leading to an increase in chip size.

Accordingly, an object of the present invention is to provide a semiconductor device capable of increasing the reverse current gain of an Ipn transistor of I ² L while using the existing bipolar process as it is.

Another object of the present invention is to provide a semiconductor device capable of increasing the fan out without increasing the chip size.

Figure 1 is a sectional view of the semiconductor element for the I ² L (integrated injection logic) according to the prior art.

2 is an equivalent circuit diagram of FIG. 1.

3 is a graph illustrating a relationship between I _C and V _EC of the pnp transistor of FIG. 1.

4 is a cross-sectional view showing a semiconductor device for I ² L according to the present invention.

5 is an equivalent circuit diagram of FIG. 4.

**** Explanation of symbols for the main parts of the drawing ****

10: substrate 11: n- epi layer 13: n + buried layer

15: n + diffusion layer 17, 18, 27, 28: P type diffusion layer 19, 29: n + diffusion layer

The semiconductor device according to the present invention for achieving the above object is

A first conductivity type substrate;

A second conductive epitaxial layer formed on the substrate;

A second conductive buried layer formed between the substrate and the epi layer;

A first conductivity type first diffusion layer formed on a part of the epi layer for the base of the first transistor for current injection;

First conductivity type second diffusion layers for collectors of the output second transistor, the plurality of second diffusion layers being formed on another part of the epi layer;

A second conductivity type third diffusion layer formed on a portion of the first diffusion layer for the emitter of the first transistor; And

And a second conductivity type fourth diffusion layer deeply formed in a part of the epi layer so as to be electrically connected to the buried layer.

Preferably, the second diffusion layers are spaced apart from the first diffusion layer. In addition, an npn transistor for current injection may be used as the first transistor, and an pnp transistor for inverter may be used as the second transistor.

Therefore, in the present invention, both the current injection npn transistor and the inverter pnp transistor are formed by a general bipolar process, and a plurality of collectors of the pnp transistor are formed and operated in the forward direction, thereby obtaining high _hfe and further increasing fanout.

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same function as the conventional part.

Referring to FIG. 4, in the I ² L of the present invention, the n- epi layer 11 of the second conductivity type is grown on the p-type silicon substrate 10 of the first conductivity type, and the substrate 10 and n- are grown. An n + buried layer 13 is formed in the region between the epitaxial layers 11, and an n + type fourth diffusion layer 15 is diffused to a part of the epitaxial layer 11 to a depth connected to the n + buried layer 13. The first diffusion layer 27 of the p-type for the base of the npn transistor, which is the first transistor, is diffused to a depth such that it is not connected to the n + buried layer 13, and the plurality of collectors for the collectors of the pnp transistor, which is the second transistor, are provided. The p-type second diffusion layers 28 are diffused to the same depth as the depth of the first diffusion layer 27, and the n + type diffusion layer 29 for the emitter of the first transistor is the n− epilayer 11 It is made of a structure that is formed in a part of the first diffusion layer 27 to a depth such that it is not connected to).

Here, the npn transistor as the first transistor is used for current injection, and the pnp transistor as the second transistor is used as the inverter. The outer contact is used as the contact of the diffusion layer 15.

In addition, an equivalent circuit for the cross-sectional structure of FIG. 4 may be represented, as shown in FIG. 5. That is, the reference voltage Vref is applied to the emitter of the pnp transistor Q12 and the base of the npn transistor Q11 together, the collector of the npn transistor Q11 is connected to the base of the pnp transistor Q12, and the npn transistor The emitter of Q11 is grounded via the injection resistor Rij. In addition, an input terminal IN is connected to a node between the base of the pnp transistor Q12 and the collector of the npn transistor Q11, and a plurality of output terminals OUT1 and OUT2 are connected to the collector of the pnp transistor Q12. (OUT3) is connected.

In the I ² L configured as described above, the npn transistor Q11 is used for current injection, and independent collectors of the pnp transistor Q12 are used as a plurality of output terminals. Since the npn transistor Q11 and the pnp transistor Q12 are formed in the same structure as the standard device of the general bipolar process, they have a high h _fe and all operate in the forward direction. That is, unlike the conventional structure, the same structure as the npn transistor of reverse operation is not formed.

In addition, the p-type second diffusion layers 28 are formed on the epi layer 11 at regular intervals with the p-type first diffusion layer 27, which is the base of the npn transistor, respectively, and are formed in the epitaxial layer 11. As the output terminal and each of them corresponds to the fan out, it is possible to increase the fan out compared to the prior art.

Accordingly, the present invention utilizes the conventional bipolar process by using the conventional bipolar process as a conventional problem caused by the low reverse current gain of the npn transistor, that is, the current amplification degree and the current loss of the current injection pnp transistor and the resulting fanout limit. All this was solved without the need for increased chip size and additional process steps or design of new process flows.

Meanwhile, in FIG. 5, a method of electrically connecting the emitter of the npn transistor Q11 to a constant voltage source of about Vref −1V instead of the ground potential through the injection resistor Rinj may be adopted.

As described above, according to the present invention, a pnp transistor is used as an inverter and an npn transistor is used for current injection in I ² L and these are formed by a general bipolar process. In addition, p-type diffusion layers corresponding to independent collectors of the pnp transistors are formed on the n− epitaxial layers so as to be spaced apart from the p-type diffusion layer for the base of the npn transistor.

Therefore, the present invention operates both the npn transistor and the pnp transistor in the forward direction and is formed in the same structure as that of the general bipolar process, so that a high h _fe can be obtained without increasing chip size or process difficulty. You can increase out.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (3)

A first conductivity type substrate; A second conductive epitaxial layer formed on the substrate; A second conductive buried layer formed between the substrate and the epi layer; A first conductivity type first diffusion layer formed on a part of the epi layer for the base of the first transistor for current injection; First conductivity type second diffusion layers for collectors of the output second transistor, the plurality of second diffusion layers being formed on another part of the epi layer; A second conductivity type third diffusion layer formed on a portion of the first diffusion layer for the emitter of the first transistor; And And a second conductivity type fourth diffusion layer deeply formed in a part of the epitaxial layer so as to be electrically connected to the buried layer. The semiconductor device of claim 1, wherein the second diffusion layers are spaced apart from each other with the first diffusion layer at a center thereof. The semiconductor device according to claim 1, wherein the first transistor is an npn transistor for current injection, and the second transistor is a pnp transistor for inverter.