KR100316523B1 - Fabricating method of capacitor - Google Patents
Fabricating method of capacitor Download PDFInfo
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- KR100316523B1 KR100316523B1 KR1019990014615A KR19990014615A KR100316523B1 KR 100316523 B1 KR100316523 B1 KR 100316523B1 KR 1019990014615 A KR1019990014615 A KR 1019990014615A KR 19990014615 A KR19990014615 A KR 19990014615A KR 100316523 B1 KR100316523 B1 KR 100316523B1
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- insulating film
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- interlayer insulating
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- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000003990 capacitor Substances 0.000 title abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 57
- 239000011229 interlayer Substances 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 229920005591 polysilicon Polymers 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000013078 crystal Substances 0.000 claims abstract description 7
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 238000003860 storage Methods 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/043—Manufacture or treatment of capacitors having no potential barriers using patterning processes to form electrode extensions, e.g. etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 커패시터 제조방법에 관한 것으로, 종래에는 커패시터의 용량을 증대시키기 위하여 커패시터 스토리지 전극으로 선택적인 반-구체 그레인 폴리실리콘을 형성함에 따라 별도로 고가의 장비가 추가되어 제조비용이 상승하고, 공정이 복잡해지며, 10-6torr 이하의 진공조건 형성이 어려운 문제점이 있었다. 따라서, 본 발명은 필드산화막이 형성된 반도체기판 상에 서로 이격되는 제1∼제4 게이트를 형성한 후, 상부전면에 제1층간절연막을 형성하는 공정과; 상기 제1층간절연막을 선택적으로 식각하고, 도전성물질을 채워 제1,제2플러그를 형성한 후, 상부전면에 제2층간절연막을 형성하는 공정과; 상기 제2층간절연막을 선택적으로 식각하고, 배선물질을 패터닝하여 비트라인을 형성한 후, 상부전면에 제3∼제6층간절연막을 형성하는 공정과; 상기 제1,제2플러그가 노출되도록 제3∼제6층간절연막을 식각하여 콘택홀을 형성한 다음 콘택홀이 채워지도록 제6층간절연막의 상부까지 제1도전체층을 형성하는 공정과; 상기 제1,제2플러그가 형성된 영역 상의 제1도전체층 상부에 절연막 패턴을 형성한 후, 상부전면에 단결정 폴리실리콘 재질의 제2도전체층을 형성한 다음 제2도전체층 상부에 일반적으로 알려진 온도 및 가스조건에서 10-2내지 10-4torr 정도의 진공조건을 적용하여 거친 폴리실리콘막을 형성하는 공정과; 상기 거친 폴리실리콘막의 상부에 고온저압 절연막을 형성하고, 에치-백하여 절연막 측벽을 형성하는 공정과; 상기 거친 폴리실리콘막과 제2도전체층을 에치-백하여 절연막 측벽을 통해 측면의 표면에 형성된 거친 폴리실리콘막이 보호되도록 한 다음 제6층간절연막을 식각하는 공정과; 상기 절연막 패턴, 절연막 측벽 및 제5층간절연막을 제거하고, 제1,제2도전체층의 표면에 유전체막을 형성한 다음 제3도전체층을 형성하는 공정으로 이루어지는 커패시터 제조방법을 제공함으로써, 커패시터의 용량을 증대시키기 위하여 커패시터의 스토리지 전극으로 단결정 폴리실리콘의 상부에 10-2내지 10-6torr 정도의 진공조건에서 거친 폴리실리콘을 형성할 수 있으며, 후속 에치-백에서 거친 폴리실리콘의 손실을 방지하기 위하여 절연막 측벽을 형성함에 따라 종래 기술에서와 같이 10-6이상의 진공조건을 만족시키기 위한 고가의 진공장비를 사용할 필요가 없게 되어 제조비용을 절감할 수 있으며, 진공조건에 따른 공정 단순화에 기여할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor, and in the related art, an additional expensive equipment is additionally added as the optional semi-spherical grain polysilicon is formed as a capacitor storage electrode in order to increase the capacity of the capacitor. Complicated, there was a problem that it is difficult to form a vacuum condition of less than 10 -6 torr. Therefore, the present invention provides a method of forming a first interlayer insulating film on an upper surface of a semiconductor substrate on which a field oxide film is formed, the first to fourth gates being separated from each other; Selectively etching the first interlayer dielectric layer, filling the conductive material to form first and second plugs, and then forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer; Selectively etching the second interlayer insulating film, patterning a wiring material to form a bit line, and then forming third to sixth interlayer insulating films on an upper surface of the second interlayer insulating film; Forming a contact hole by etching the third to sixth interlayer insulating films to expose the first and second plugs, and then forming a first conductive layer to an upper portion of the sixth interlayer insulating film to fill the contact holes; After the insulating film pattern is formed on the first conductive layer on the region where the first and second plugs are formed, a second conductive layer of single crystal polysilicon is formed on the upper surface, and then a temperature generally known on the second conductive layer is formed. And forming a coarse polysilicon film by applying a vacuum condition of about 10 −2 to 10 −4 torr under gas conditions; Forming a high temperature low pressure insulating film on the coarse polysilicon film and etching-back to form an insulating film sidewall; Etching back the rough polysilicon film and the second conductive layer to protect the rough polysilicon film formed on the surface of the side surface through the insulating film sidewalls and then etching the sixth interlayer insulating film; A capacitor manufacturing method comprising removing the insulating film pattern, the insulating film sidewalls, and the fifth interlayer insulating film, forming a dielectric film on the surface of the first and second conductive layers, and then forming a third conductive layer. In order to increase the thickness, coarse polysilicon may be formed on the top of the single crystal polysilicon as a storage electrode of the capacitor under vacuum conditions of about 10 -2 to 10 -6 torr and to prevent the loss of coarse polysilicon in subsequent etch-back. In order to form an insulating film sidewall, it is not necessary to use expensive vacuum equipment for satisfying the vacuum condition of 10 -6 or more as in the prior art, thereby reducing manufacturing cost and contributing to the process simplification according to the vacuum condition. It works.
Description
본 발명은 커패시터 제조방법에 관한 것으로, 특히 커패시터 스토리지 전극의 증착을 위한 진공조건을 개선함과 아울러 표면적을 향상시켜 용량을 증가시키기에 적당하도록 한 커패시터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor, and more particularly, to a method for manufacturing a capacitor, which is suitable for increasing a capacity by improving a surface area while improving vacuum conditions for deposition of a capacitor storage electrode.
일반적으로, 반도체 커패시터소자의 용량을 증가시키기 위해서는 요구되는 칩의 고접적화에 대하여 얼마만큼 표면적을 늘릴 수 있느냐가 중요한 이슈가 되고 있다. 이와같은 종래의 커패시터 제조방법을 첨부한 도1a 내지 도1d에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.In general, in order to increase the capacity of a semiconductor capacitor device, an important issue is how much surface area can be increased for high integration of a required chip. If described in detail with reference to the cross-sectional view shown in Figures 1a to 1d attached to the conventional capacitor manufacturing method as follows.
먼저, 도1a에 도시한 바와같이 반도체기판(1) 상에 필드산화막(2)을 형성하여 액티브영역을 정의하고, 반도체기판(1) 및 필드산화막(2)의 상부에 일정한 거리로 이격되는 게이트(3A∼3D)를 형성한다.First, as shown in FIG. 1A, the field oxide film 2 is formed on the semiconductor substrate 1 to define an active region, and the gate is spaced apart at a predetermined distance from the top of the semiconductor substrate 1 and the field oxide film 2. (3A-3D) are formed.
그리고, 상기 게이트(3A∼3D)가 형성된 구조물의 상부전면에 층간절연막(4)을 형성하고, 액티브영역과 필드산화막(2) 상의 게이트(3A,3B),(3C,3D)간 이격영역을 식각하여 콘택홀을 형성한 후, 도전성물질을 채워 플러그(5A,5B)를 형성한다.Then, an interlayer insulating film 4 is formed on the upper surface of the structure where the gates 3A to 3D are formed, and the spaced apart area between the gates 3A, 3B and 3C, 3D on the active region and the field oxide film 2 is formed. After etching to form contact holes, the conductive materials are filled to form plugs 5A and 5B.
그리고, 상기 플러그(5A,5B)가 형성된 구조물의 상부전면에 층간절연막(6)을 형성하고, 액티브영역 상의 게이트(3B,3C)간 이격영역을 식각하여 콘택홀을 형성한 후, 배선물질을 패터닝하여 비트라인(7)을 형성한다.Then, an interlayer insulating film 6 is formed on the upper surface of the structure where the plugs 5A and 5B are formed, and a contact hole is formed by etching the spaced area between the gates 3B and 3C on the active region, and then forming a wiring material. Patterning to form the bit line (7).
그리고, 상기 비트라인(7)이 형성된 구조물의 상부전면에 복수개의 층간절연막(8∼11)을 형성하고, 상기 플러그(5A,5B)가 형성된 영역을 식각하여 콘택홀을 형성한 다음 그 콘택홀이 채워지도록 층간절연막(11)의 상부까지 제1도전체층(12)을 형성하고, 그 제1도전체층(12)의 상부전면에 절연막(13)을 형성한다.Then, a plurality of interlayer insulating films 8 to 11 are formed on the upper surface of the structure where the bit line 7 is formed, and the contact holes are formed by etching the regions where the plugs 5A and 5B are formed, and then the contact holes. The first conductive layer 12 is formed up to the upper portion of the interlayer insulating film 11 so as to fill the gap, and the insulating film 13 is formed on the entire upper surface of the first conductive layer 12.
그리고, 도1b에 도시한 바와같이 상기 절연막(13)을 패터닝함으로써, 절연막(13)이 상기 플러그(5A,5B)가 형성된 영역 상의 제1도전체층(12) 상부 일정한 영역에만 잔류하도록 한다.As shown in FIG. 1B, the insulating film 13 is patterned so that the insulating film 13 remains only in a predetermined region above the first conductive layer 12 on the areas where the plugs 5A and 5B are formed.
그리고, 도1c에 도시한 바와같이 상기 절연막(13)이 패터닝된 구조물의 상부전면에 제2도전체층(14)을 형성한 다음 제2,제1도전체층(14,12)을 에치-백(etch-back)하여 상기 제1도전층(12)의 상부에 패터닝된 절연막(13) 측면에 제2,제1도전체층(14,12)이 적층되어 잔류하도록 하고, 이를 마스크로 이용하여 상기 층간절연막(11)을 식각한다. 이때, 제2도전체층(14)은 커패시터의 스토리지 전극으로 증착이 용이한 평판형식으로 형성할 수 있으나, 이는 커패시터의 용량증대에 한계가 있기 때문에 최근들어 배리어(barrier) 폴리실리콘을 형성하고, 에치-백(etch-back)한 다음 저진공(10-6torr 이하) 상태에서 SiH4가스를 사용하여 배리어 폴리실리콘 상부에서는 증착 및 재결정의 형성이 잘 이루어지고, 주변 절연막 상부에서는 도전체의 형성이 이루어지지 않으면서, 표면적을 넓힐 수 있는 선택적인(selectivity) 반-구체 그레인(hemi-spherical grain : HSG) 폴리실리콘을 증착하여 형성한다.As shown in FIG. 1C, the second conductive layer 14 is formed on the upper surface of the structure in which the insulating layer 13 is patterned, and then the second and first conductive layers 14 and 12 are etched back. The second and first conductive layers 14 and 12 are stacked on the side of the patterned insulating layer 13 on the upper surface of the first conductive layer 12 by etch-back, and the remaining interlayers are used as a mask. The insulating film 11 is etched. In this case, the second conductive layer 14 may be formed in a flat plate type that is easily deposited as a storage electrode of the capacitor. However, since the capacity of the capacitor is limited, the second conductive layer 14 may form barrier polysilicon in recent years. After etch-back, the SiH 4 gas is used at low vacuum (10 -6 torr or less), and deposition and recrystallization are well formed on the top of the barrier polysilicon. It is formed by depositing selective semi-spherical grain (HSG) polysilicon that can increase the surface area without making it happen.
그리고, 도1d에 도시한 바와같이 상기 층간절연막(11,10)을 제거하고, 유전체막(15)을 형성한 다음 제3도전체층(16)을 형성하여 커패시터 제조를 완료한다.As shown in FIG. 1D, the interlayer insulating films 11 and 10 are removed, the dielectric film 15 is formed, and the third conductive layer 16 is formed to complete the capacitor manufacturing.
그러나, 상기한 바와같은 종래의 커패시터 제조방법은 커패시터의 용량을 증대시키기 위하여 커패시터 스토리지 전극으로 선택적인 반-구체 그레인 폴리실리콘을 형성함에 따라 별도로 고가의 장비가 추가되어 제조비용이 상승하고, 공정이 복잡해지며, 10-6torr 이하의 진공조건 형성이 어려운 문제점이 있었다.However, in the conventional capacitor manufacturing method as described above, as the optional semi-spherical grain polysilicon is formed as the capacitor storage electrode to increase the capacity of the capacitor, additional expensive equipment is added to increase the manufacturing cost, and the process is increased. Complicated, there was a problem that it is difficult to form a vacuum condition of less than 10 -6 torr.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 커패시터 스토리지 전극을 거친(rugged) 폴리실리콘을 사용하여 별도의 장비가 요구되지 않고, 진공조건을 개선함과 아울러 표면적을 향상시켜 용량을 더욱 증대시킬 수 있는 커패시터 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to improve vacuum conditions without requiring additional equipment by using polysilicon rugged capacitor storage electrodes. In addition, to provide a method of manufacturing a capacitor that can further increase the capacity by improving the surface area.
도1a 내지 도1d는 종래의 커패시터 제조방법을 보인 수순단면도.Figure 1a to 1d is a cross-sectional view showing a conventional capacitor manufacturing method.
도2a 내지 도2h는 본 발명의 일 실시예를 보인 수순단면도.2A to 2H are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
21:반도체기판 22:필드산화막21: semiconductor substrate 22: field oxide film
23A∼23D:게이트 24,26,28∼31:층간절연막23A to 23D: gates 24, 26, 28 to 31: interlayer insulating film
25A,25B:플러그 27:비트라인25A, 25B: Plug 27: Bit line
32:제1도전체층 33:절연막32: first conductive layer 33: insulating film
34:제2도전체층 35:거친 폴리실리콘막34: second conductive layer 35: coarse polysilicon film
36:고온저압 산화막 37:절연막 측벽36: high temperature low pressure oxide film 37: insulating film sidewall
38:유전체막 39:제3도전체층38: dielectric film 39: third conductive layer
상기한 바와같은 본 발명의 목적을 달성하기 위한 커패시터 제조방법은 필드산화막이 형성된 반도체기판 상에 서로 이격되는 제1∼제4 게이트를 형성한 후, 상부전면에 제1층간절연막을 형성하는 공정과; 상기 제1층간절연막을 선택적으로 식각하고, 도전성물질을 채워 제1,제2플러그를 형성한 후, 상부전면에 제2층간절연막을 형성하는 공정과; 상기 제2층간절연막을 선택적으로 식각하고, 배선물질을 패터닝하여 비트라인을 형성한 후, 상부전면에 제3∼제6층간절연막을 형성하는 공정과; 상기 제1,제2플러그가 노출되도록 제3∼제6층간절연막을 식각하여 콘택홀을 형성한 다음 콘택홀이 채워지도록 제6층간절연막의 상부까지 제1도전체층을 형성하는 공정과; 상기 제1,제2플러그가 형성된 영역 상의 제1도전체층 상부에 절연막 패턴을 형성한 후, 상부전면에 단결정 폴리실리콘 재질의 제2도전체층을 형성한 다음 제2도전체층 상부에 일반적으로 알려진 온도 및 가스조건에서 10-2내지 10-4torr 정도의 진공조건을 적용하여 거친 폴리실리콘막을 형성하는 공정과; 상기 거친 폴리실리콘막의 상부에 고온저압 절연막을 형성하고, 에치-백하여 절연막 측벽을 형성하는 공정과; 상기 거친 폴리실리콘막과 제2도전체층을 에치-백하여 절연막 측벽을 통해 측면의 표면에 형성된 거친 폴리실리콘막이 보호되도록 한 다음 제6층간절연막을 식각하는 공정과; 상기 절연막 패턴, 절연막 측벽 및 제5층간절연막을 제거하고, 제1,제2도전체층의 표면에 유전체막을 형성한 다음 제3도전체층을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.The capacitor manufacturing method for achieving the object of the present invention as described above is a step of forming a first interlayer insulating film on the upper surface after forming the first to fourth gates spaced apart from each other on the semiconductor substrate on which the field oxide film is formed; ; Selectively etching the first interlayer dielectric layer, filling the conductive material to form first and second plugs, and then forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer; Selectively etching the second interlayer insulating film, patterning a wiring material to form a bit line, and then forming third to sixth interlayer insulating films on an upper surface of the second interlayer insulating film; Forming a contact hole by etching the third to sixth interlayer insulating films to expose the first and second plugs, and then forming a first conductive layer to an upper portion of the sixth interlayer insulating film to fill the contact holes; After the insulating film pattern is formed on the first conductive layer on the region where the first and second plugs are formed, a second conductive layer of single crystal polysilicon is formed on the upper surface, and then a temperature generally known on the second conductive layer is formed. And forming a coarse polysilicon film by applying a vacuum condition of about 10 −2 to 10 −4 torr under gas conditions; Forming a high temperature low pressure insulating film on the coarse polysilicon film and etching-back to form an insulating film sidewall; Etching back the rough polysilicon film and the second conductive layer to protect the rough polysilicon film formed on the surface of the side surface through the insulating film sidewalls and then etching the sixth interlayer insulating film; And removing the insulating film pattern, the insulating film side wall, and the fifth interlayer insulating film, forming a dielectric film on the surfaces of the first and second conductive layers, and then forming a third conductive layer.
상기한 바와같은 본 발명에 의한 커패시터 제조방법을 첨부한 도2a 내지 도2h에 도시한 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view shown in Figure 2a to 2h attached to the capacitor manufacturing method according to the present invention as an embodiment in detail as follows.
먼저, 도2a에 도시한 바와같이 반도체기판(21) 상에 필드산화막(22)을 형성하여 액티브영역을 정의하고, 반도체기판(21) 및 필드산화막(22)의 상부에 일정한 거리로 이격되는 게이트(23A∼23D)를 형성한다.First, as shown in FIG. 2A, the field oxide film 22 is formed on the semiconductor substrate 21 to define an active region, and the gate is spaced apart at a predetermined distance from the top of the semiconductor substrate 21 and the field oxide film 22. 23A to 23D are formed.
그리고, 상기 게이트(23A∼23D)가 형성된 구조물의 상부에 층간절연막(24)을 형성하고, 액티브영역과 필드산화막(22) 상의 게이트(23A,23B),(23C,23D)간 이격영역을 선택적으로 식각하여 콘택홀을 형성한 후, 그 콘택홀에 도전성물질을 채워 플러그(25A,25B)를 형성한다.An interlayer insulating film 24 is formed on the structure where the gates 23A to 23D are formed, and a spaced apart region between the gates 23A, 23B and 23C and 23D on the active region and the field oxide film 22 is selectively selected. After etching to form a contact hole, the contact hole is filled with a conductive material to form plugs 25A and 25B.
그리고, 상기 플러그(25A,25B)가 형성된 구조물의 상부에 층간절연막(26)을 형성하고, 액티브영역 상의 게이트(23B,23C)간 이격영역을 식각하여 콘택홀을 형성한 후, 배선물질을 패터닝하여 비트라인(27)을 형성한다.In addition, an interlayer insulating layer 26 is formed on the structure where the plugs 25A and 25B are formed, and a contact hole is formed by etching the spaced area between the gates 23B and 23C on the active region, and then patterning the wiring material. The bit line 27 is formed.
그리고, 상기 비트라인(27)이 형성된 구조물의 상부전면에 복수개의 층간절연막(28∼31)을 형성하고, 상기 플러그(25A,25B)가 형성된 영역을 식각하여 콘택홀을 형성한 다음 콘택홀이 채워지도록 층간절연막(31)의 상부까지 제1도전체층(32)을 형성하고, 그 제1도전체층(32)의 상부전면에 절연막(33)을 형성한다.A plurality of interlayer insulating films 28 to 31 are formed on the upper surface of the structure where the bit lines 27 are formed, and the contact holes are formed by etching the regions where the plugs 25A and 25B are formed. The first conductive layer 32 is formed to the upper portion of the interlayer insulating film 31 so as to be filled, and the insulating film 33 is formed on the entire upper surface of the first conductive layer 32.
그리고, 도2b에 도시한 바와같이 상기 절연막(33)을 패터닝함으로써, 절연막(33)이 상기 플러그(25A,25B)가 형성된 영역 상의 제1도전체층(32) 상부 일정한 영역에만 잔류하도록 한 다음 상부전면에 제2도전체층(34)을 형성한다. 이때, 제2도전체층(34)은 단결정 폴리실리콘막으로 형성하는 것이 바람직하다.As shown in FIG. 2B, the insulating film 33 is patterned so that the insulating film 33 remains only in a predetermined region above the first conductive layer 32 on the region where the plugs 25A and 25B are formed. The second conductive layer 34 is formed on the entire surface. In this case, the second conductive layer 34 is preferably formed of a single crystal polysilicon film.
그리고, 도2c에 도시한 바와같이 상기 제2도전체층(34)의 상부에 거친 폴리실리콘막(35)을 저진공 상태에서 형성한다. 이때, 거친 폴리실리콘막(35)은 단결정 폴리실리콘 재질인 상기 제2도전체층(34) 상부에 형성됨에 따라 일반적으로 알려진 온도 및 가스조건에서 10-2내지 10-4torr 정도의 진공조건을 적용하여 형성할 수 있게 된다.As shown in FIG. 2C, a coarse polysilicon film 35 is formed on the second conductive layer 34 in a low vacuum state. At this time, the coarse polysilicon film 35 is formed on the second conductive layer 34 made of a single crystal polysilicon, so that a vacuum condition of about 10 -2 to 10 -4 torr is applied at a known temperature and gas condition. Can be formed.
그리고, 도2d에 도시한 바와같이 상기 거친 폴리실리콘막(35)의 상부에 고온저압 산화막(36)을 형성한다.As shown in FIG. 2D, a high temperature low pressure oxide film 36 is formed on the coarse polysilicon film 35.
그리고, 도2e에 도시한 바와같이 상기 고온저압 산화막(36)을 에치-백하여 절연막 측벽(37)을 형성한다. 이때, 절연막 측벽(37)은 후속 공정의 제2,제1도전체층(34,32) 에치-백이 진행될 때, 거친 폴리실리콘막(35)의 손실을 방지한다.As shown in FIG. 2E, the high temperature low pressure oxide film 36 is etched back to form an insulating film sidewall 37. At this time, the insulating film sidewall 37 prevents the loss of the coarse polysilicon film 35 when the second and first conductive layers 34 and 32 are etched back.
그리고, 도2f에 도시한 바와같이 상기 거친 폴리실리콘막(35)과 제2도전체층(34)을 에치-백한 다음 층간절연막(31)을 식각한다.As shown in FIG. 2F, the coarse polysilicon film 35 and the second conductive layer 34 are etched back, and the interlayer insulating film 31 is etched.
그리고, 도2g에 도시한 바와같이 상기 패터닝된 절연막(33), 절연막 측벽(37) 및 층간절연막(30)을 제거한다.2G, the patterned insulating film 33, the insulating film sidewall 37, and the interlayer insulating film 30 are removed.
그리고, 도2h에 도시한 바와같이 상기 제1,제2도전체층(32,34)의 표면에 유전체막(38)을 형성한 다음 제3도전체층(39)을 형성하여 제조를 완료한다.2H, a dielectric film 38 is formed on the surfaces of the first and second conductive layers 32 and 34, and then a third conductive layer 39 is formed to complete the manufacturing.
상기한 바와같은 본 발명에 의한 커패시터 제조방법은 커패시터의 용량을 증대시키기 위하여 커패시터의 스토리지 전극으로 단결정 폴리실리콘의 상부에 10-2내지 10-6torr 정도의 진공조건에서 거친 폴리실리콘을 형성할 수 있으며, 후속 에치-백에서 거친 폴리실리콘의 손실을 방지하기 위하여 절연막 측벽을 형성함에 따라 종래 기술에서와 같이 10-6이상의 진공조건을 만족시키기 위한 고가의 진공장비를 사용할 필요가 없게 되어 제조비용을 절감할 수 있으며, 진공조건에 따른 공정 단순화에 기여할 수 있는 효과가 있다.Capacitor manufacturing method according to the present invention as described above can form a coarse polysilicon in a vacuum condition of 10 -2 to 10 -6 torr on top of the single crystal polysilicon as a storage electrode of the capacitor in order to increase the capacity of the capacitor In order to prevent loss of coarse polysilicon in subsequent etch-back, the sidewalls of the insulating film are formed, thereby eliminating the need for using expensive vacuum equipment for satisfying vacuum conditions of 10 -6 or more as in the prior art. It can reduce and contribute to the process simplification according to the vacuum conditions.
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