KR100314472B1 - Ferroelectric random access memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, and has a structure in which transistors, which are conventionally provided for each unit cell of a ferroelectric memory, are provided for each line, so that M × N (M, N are integers) capacitors, bit lines, and plate lines. The memory region is formed in the upper portion of the logic circuit region, so that only transistors corresponding to each line can be formed on the silicon substrate, and at the same time, the word lines, which are separately provided separately, are removed for each unit cell. The present invention can increase the degree of integration by reducing the silicon area occupied by the transistor and reducing the area of the memory cell area itself.

Description

Ferroelectric Memory {FERROELECTRIC RANDOM ACCESS MEMORY}

FIELD OF THE INVENTION The present invention relates to ferroelectric random access memory, and more particularly to ferroelectric memory suitable for fabrication with high integration.

As is well known, semiconductor memory can be classified into volatile memory and non-volatile memory according to whether information is lost after a power failure, and is represented by dynamic random access memory (DRAM). The problem is that information is stored only while power is supplied instead of fast operation speed. Non-volatile memory represented by erasable and programmable read only memory (EPROM), electrically EPROM (EPEP), flash memory (flash memory) is a power source. While this block has the advantage that no information is lost, the operation speed is slow and the power consumption is a big problem.

On the other hand, ferroelectric materials having a perovskite structure, for example, PbTiO 3 [BT], (Pb, La) TiO 3 [PLT], Pb (Zr, Ti) O 3 [PZT], (Pb, La) Ferroelectric memory adopting (Zr, Ti) O3 is expected to replace existing semiconductor memory in the future due to its advantages such as low voltage operation, fast data processing speed, and high durability and reliability. The development and research is actively progressing.

Such ferroelectric memories have many advantages as described above, but have difficulty in high integration due to their operating characteristics. That is, in the case of the ferroelectric memory, different voltages are applied to the plate electrode according to the input information, so that each unit cell is basically the same structure as that of the DRAM unit cell as shown in FIGS. Despite having one transistor and one capacitor, in DRAM, the plate electrodes of the entire cell can be integrally formed, while in ferroelectric memory, the plate electrodes between neighboring cells must be electrically separated. do.

As such, the ferroelectric memory must electrically separate the plate electrode line from the bit line of the neighboring cell, so that the area occupied by the separated plate electrode increases, and moreover, the metal used as the electrode of the capacitor is difficult to etch. The spacing also had to be kept constant, making it more difficult to integrate.

In addition, as described above, each unit cell of the ferroelectric memory includes one transistor 10 and one capacitor 20. Since the transistors must be formed on the silicon substrate, the capacitor and the logic circuit region are formed on the silicon substrate. There is a problem in that the plane is formed on the limit to the degree of integration.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an object to provide a ferroelectric memory having a structure in which a formation range of a memory cell is reduced and a memory cell region can be stacked on top of a logic circuit region. .

In order to achieve the above object, in one aspect of the present invention, a ferroelectric memory having unit cells of an M × N (M and N are integers) array, each having M bit lines and M bit lines, respectively. M × N capacitors having N plate electrode lines crossing each other, one electrode connected to the plate electrode line, and the other electrode connected to the bit line at each intersection point of the bit line and the plate electrode line, and the M bit lines. A bit line driving transistor connected one-to-one with each other to selectively drive a specific bit line among the M bit lines, and one-to-one connected with each of the N plate electrode lines to connect a specific plate electrode line among the N plate electrode lines A ferroelectric memory having a plate electrode line driving transistor for selectively driving is provided.

On the other hand, in another aspect of the present invention, a ferroelectric memory having unit cells of an M × N (M and N are integers) array includes M bit lines, M inverse bit lines, M bit lines, and the like. N plate electrode lines crossing each of the reverse bit lines, and one electrode thereof are connected to the plate electrode line, and the other electrode is alternately connected to the bit line and the reverse bit line in a fierce or violent manner. M x N capacitors arranged in the form of a black or white pattern of the N-bit capacitor, a bit line driving transistor connected one-to-one with each of the M bit lines to selectively drive a specific bit line among the M bit lines; M reverse bit lines are connected to the M reverse bit lines in a one-to-one manner so as to pair with the M bit lines, so that when a specific bit line is driven, A reverse bit line driving transistor for simultaneously driving the reverse bit lines, and a plate electrode line driving transistor connected to each of the N plate electrode lines one-to-one and selectively driving a specific plate electrode line among the N plate electrode lines. A ferroelectric memory is provided.

On the other hand, in another aspect of the present invention, a ferroelectric memory having unit cells in an M × N (M and N are integers) array, wherein M bit lines, M inverse bit lines, and M bits N plate electrode lines crossing each of the line and the reverse bit line, 2 M x N capacitors whose one electrode is connected to the plate electrode line, and the other electrode is connected to the bit line or the reverse bit line; A bit line driving transistor connected one-to-one with each of the M bit lines to selectively drive a specific bit line among the M bit lines, and the M bit lines such that the M reverse bit lines are paired with the M bit lines Reverse bit line driving transistors connected one-to-one to a reverse bit line and simultaneously driving a reverse bit line paired with the bit line when a specific bit line is driven. , The N plates are electrode lines connected to the respective one-to-one provides a ferroelectric memory comprising the N number of electrode plate line drive transistor for driving a certain electrode line of the plate as the plate electrode line seontae ever.

1 is a circuit diagram showing a ferroelectric memory (FeRAM) according to the prior art;

FIG. 2 is a cross-sectional structural view showing unit cells of the ferroelectric memory shown in FIG. 1;

3 is a circuit diagram illustrating a ferroelectric memory according to an exemplary embodiment of the present invention;

4 is a circuit diagram showing a ferroelectric memory according to another preferred embodiment of the present invention;

5 is a circuit diagram illustrating a ferroelectric memory according to another preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: transistor 20: capacitor

P0, P1, P2,... : Plate Electrode Line

B0, B1, B2,... Bit line

B0 ', B1', B2 ',... Reverse bit line

TP0, TP1, TP2,... : Plate Electrode Line Driving Transistor

TB0, TB1, TB2,... Bit Line Drive Transistor

TB0 ', TB1', TB2 ',... Reverse Bit Line Drive Transistor

C00, C01, C02,... : Unit cell

Hereinafter, the ferroelectric memory according to the present invention will be described with reference to FIGS. 3 to 5 with reference to preferred embodiments 1 to 3 of the present invention.

First, the core technical idea of the present invention is to form a structure in which transistors, which are conventionally provided for each unit cell of a ferroelectric memory, are provided for each line, so that M × N (M and N are integers) and capacitors and bit lines. The memory region consisting of plate lines is formed on the upper portion of the logic circuit region, and only the transistors corresponding to each line can be formed on the silicon substrate, and at the same time, each unit cell is conventionally removed by removing word lines that have been separately provided. In order to reduce the silicon area occupied by the transistors provided every time and to reduce the area of the memory cell area itself, the degree of integration is increased, and Examples 1 to 3 to be described below are based on such core technology idea. It should be understood.

Example 1

Hereinafter, this embodiment will be described with reference to FIG. 3. 3 is a circuit diagram showing the structure of the ferroelectric memory according to the present embodiment.

A feature of the ferroelectric memory according to the present embodiment is that the transistors, which were conventionally provided for each unit cell of the ferroelectric memory, have a structure in which each line is provided, so that the selective driving of the transistor connected to the plate electrode line and the transistor connected to the bit line are provided. It is configured to input or output a unit cell to a cell located at an intersection thereof by selective driving. The structure and data input / output process of the ferroelectric memory according to the present embodiment will be described based on such features. Is as follows.

First, referring to FIG. 3, the structure of the memory according to the present embodiment is as follows.

M bit lines B0, B1, B2, ... form a row or column, and N plate electrode lines P0, P1, P2, ... form the M bit lines B0, B1, B2, ... Columns or rows are intersected with each other, and have a matrix form.

At the point where the bit lines B0, B1, B2, ... and the plate electrode lines P0, P1, P2, ... intersect, one electrode is the plate electrode line P0, every MxN capacitors. P1, P2, ...), and the other electrode is connected to the bit line intersecting the plate electrode line to which one electrode is connected, M × N unit cells (for example, indicated by a dotted line in Figure 3) Part).

Each of the M bit lines B0, B1, B2, ... is a bit line driving transistor TB0, TB1, for selectively driving a specific bit line among the M bit lines B0, B1, B2, .... TB2, ... are connected one-to-one, and each of the N plate electrode lines P0, P1, P2, ... is selectively connected to a specific plate electrode line among the N plate electrode lines P0, P1, P2, ... Plate electrode line driving transistors TP0, TP1, TP2, ... for driving are connected one-to-one.

At this time, in the present embodiment, a memory area including M bit lines B0, B1, B2, ..., N plate electrode lines P0, P1, P2, ..., and the MxN capacitors is not shown. And the bit line driving transistors TB0, TB1, TB2,... And the plate electrode line driving transistors TP0, TP1, TP2,... It would be more desirable to be formed on the substrate.

Hereinafter, a process of inputting / outputting data in the ferroelectric memory having the above-described structure according to the present embodiment will be described. In this case, a process of inputting data '1' and '0' and a process of outputting the stored data will be described separately, but for convenience, cell C00 will be described. In this example, the upper voltage is 5V, the lower voltage is 0V, and the driving voltage for driving each transistor is a voltage level obtained by adding 5V to the threshold voltage of the transistor.

First, a process of inputting data '1' into the unit cell C00 will be described.

In order to input the data '1', first, a driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the bit line driving transistor TB0 connected to the bit line B0. The upper voltage 5 [V] is applied to the source electrode. As a result, the potential of 5 [V] will be applied to the bit line B0.

At the same time, a driving voltage, for example, 5 V + Vt (threshold voltage) [V] is applied to the gate gate electrode of the plate electrode driving transistor TP0 connected to the plate electrode line P0, and the lower voltage 0 is applied to the source electrode. Apply [V]. As a result, the potential of 0 [V] will be applied to the plate electrode line P0.

Therefore, the ferroelectric film provided in the cell C00 is polarized in the positive direction by the potential difference, thereby storing data '1'.

Meanwhile, a process of inputting data '0' into the unit cell C00 will be described.

In order to input the data '0', first, a driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the bit line driving transistor TB0 connected to the bit line B0. A low voltage of 0 [V] is applied to the source electrode. As a result, the potential of 0 [V] will be applied to the bit line B0.

At the same time, a driving voltage, for example, 5 V + Vt (threshold voltage) [V] is applied to the gate gate electrode of the plate electrode driving transistor TP0 connected to the plate electrode line P0, and the upper voltage 5 is applied to the source electrode. Apply [V]. As a result, the plate electrode line P0 will have a potential of 5 [V].

Thus, the ferroelectric film provided in the cell C00 is polarized in the negative direction by the potential difference, thereby storing data '0'.

Meanwhile, a process of reading data input to the unit cell C00 by the above-described process is as follows.

In order to read the data written in the unit cell as described above, the upper dummy bit line to which the upper voltage is applied to one side where M bit lines B0, B1, B2, ... are formed in the ferroelectric memory according to the present embodiment. A lower dummy bit line to which an over low voltage is applied is further provided, and an average voltage output line for outputting an average voltage of two voltages is further provided at ends of the upper dummy bit line and the lower dummy bit line. In this case, since the upper dummy bit line and the lower dummy bit line are simple lines for applying a voltage, illustration thereof is omitted.

In order to read the data written in the unit cell C00, first, a driving voltage is applied to the gate electrode of the bit line driving transistor TB0 connected to the bit line B0 and the plate electrode driving transistor TP0 connected to the plate electrode line P0. For example, 5V + Vt (threshold voltage) [V] is applied, and an average voltage of an upper voltage and a lower voltage, for example, 2.5 [V], is applied to a source electrode of the bit line driving transistor TB0. The lower voltage is applied to the source electrode of the plate electrode driving transistor TP0.

At this time, since the unit cell C00 has a different polarization direction according to the data value, the output voltage detected at the last end of the bit line B0 will be larger or smaller than the input average voltage due to the influence. That is, the average voltage output from the above-mentioned upper and lower dummy bit lines and the output voltage detected at the last end of the bit line B0 are compared. If the output voltage is larger than the average voltage, data is read as '1' and If it is, data is read as '0'.

Example 2

Hereinafter, this embodiment will be described with reference to FIG. 4. 4 is a circuit diagram showing the structure of the ferroelectric memory according to the present embodiment.

The ferroelectric memory according to the present embodiment includes 'M inverse bit lines B0', B1 ', B2', ... which are paired with each of the M bit lines B0, B1, B2, ..., as compared with the first embodiment. And the reverse bit line driving transistors TB0 ', TB1', TB2 ', ... connected thereto, and the capacitors provided in the unit cells are formed in a permutation array structure like a black pattern or a white pattern of a chessboard. And to use the output voltage of the reverse bit line paired with the connected bit line as a reference voltage at the time of reading data. The structure of the ferroelectric memory according to the present embodiment is The data input / output process is described as follows.

First, referring to FIG. 4, the structure of the memory according to the present embodiment is as follows.

M bit lines (B0, B1, B2, ...) and M inverted bit lines (B0 ', B1', B2 ', ...), which are arranged alternately with each other, form a row or column, and N The plate electrode lines P0, P1, P2, ... intersect with the M bit lines B0, B1, B2, ... and the M reverse bit lines B0 ', B1', B2 ', ... It forms a column or a row and has a matrix form.

The one electrode is connected to the plate electrode lines P0, P1, P2, ..., and the other electrode is connected to the M bit lines B0, B1, B2, ... in a row. And M × N capacitors arranged in a column-parallel structure such as a black or white pattern on a chessboard, connected in a row with respect to the M reverse bit lines B0 ', B1', B2 ', ... It is provided. That is, when the one electrode is connected to each line provided in one line group (for example, bit line), the other electrode is 0, 2, 4,... When the other electrode is connected to the plate electrode lines (P0, P2, P4, ...) arranged in even columns, such that one electrode is connected to each line provided in the other line group (for example, reverse bit line) 1, 3, 5,... MxN capacitors are provided that are connected to the plate electrode lines P0, P2, P4, ... arranged in an odd number column.

In addition, M bit line driving transistors TB0, TB1, TB2,... Are connected one-to-one to each of the M bit lines B0, B1, B2,..., And the M bit lines B0, B1, B2. M reverse bit line driving transistors TB0 ', TB1', TB2 ', ... are connected to each of the M reverse bit lines B0', B1 ', B2', ... which are paired with each of the lines. . At this time, the gate electrodes of the paired bit line driving transistor TB and the reverse bit line driving transistor TB 'are connected to each other and driven simultaneously. In particular, when each driving transistor is driven, voltages opposite to each other, that is, a lower voltage for the upper voltage and an upper voltage for the lower voltage, are respectively opposite to the source electrodes of the bit line driving transistor TB and the reverse bit line driving transistor TB '. Voltage is applied.

Each of the N plate electrode lines P0, P1, P2, ... is a plate electrode line driving transistor for selectively driving a specific plate electrode line among the N plate electrode lines P0, P1, P2, ... (TP0, TP1, TP2, ...) are connected one-to-one.

At this time, in the present embodiment, M bit lines B0, B1, B2, ..., M reverse bit lines B0 ', B1', B2 ', ..., N plate electrode lines P0, P1, P2 , ...) and the MxN capacitors are formed on the upper portion of the logic circuit region of the semiconductor device (not shown), and the bit line driving transistors TB0, TB1, TB2,. More preferably, TB0 ', TB1', TB2 ', ... and plate electrode line driving transistors TP0, TP1, TP2, ... are formed on the silicon substrate outside the logic circuit region.

Hereinafter, a process of inputting / outputting data in the ferroelectric memory having the above-described structure according to the present embodiment will be described. In this case, the process of inputting the data '1' and '0' and the process of outputting the stored data will be described separately, but for convenience, the cell C00 will be described. In this example, the upper voltage is 5V, the lower voltage is 0V, and the driving voltage for driving each transistor is a voltage level obtained by adding 5V to the threshold voltage of the transistor. At this time, since the gate electrodes of the bit line driving transistor TB and the reverse bit line driving transistor TB 'are connected to each other, a reverse bit paired with the bit line when the driving voltage is applied to the bit line driving transistor TB A driving voltage is also applied to the gate electrode of the line driving transistor TB0 ', and a voltage opposite to the voltage applied to the source electrode of the bit line driving transistor TB is applied to the source electrode, but as shown in FIG. Since the capacitor is not connected to the other line (ie, the bit line or the reverse bit line) of the unit cell to which input is input, the input of the data is not affected. Therefore, the description of the other line will be described only in the data output process.

First, a process of inputting data '1' into the unit cell C00 will be described.

In order to input the data '1', first, a driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the bit line driving transistor TB0 connected to the bit line B0. The upper voltage 5 [V] is applied to the source electrode. As a result, the potential of 5 [V] will be applied to the bit line B0.

At the same time, a driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the plate electrode driving transistor TP0 connected to the plate electrode line P0, and the lower voltage 0 [is applied to the source electrode. V] is applied. As a result, the potential of 0 [V] will be applied to the plate electrode line P0.

Therefore, the ferroelectric film provided in the cell C00 is polarized in the positive direction by the potential difference, thereby storing data '1'.

Meanwhile, a process of inputting data '0' into the unit cell C00 will be described.

In order to input the data '0', first, a driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the bit line driving transistor TB0 connected to the bit line B0. A low voltage of 0 [V] is applied to the source electrode. As a result, the potential of 0 [V] will be applied to the bit line B0.

At the same time, a driving voltage, for example, 5 V + Vt (threshold voltage) [V] is applied to the gate gate electrode of the plate electrode driving transistor TP0 connected to the plate electrode line P0, and the upper voltage 5 is applied to the source electrode. Apply [V]. As a result, the plate electrode line P0 will have a potential of 5 [V].

Thus, the ferroelectric film provided in the cell C00 is polarized in the negative direction by the potential difference, thereby storing data '0'.

In the above-described data input process, the case in which one terminal of the capacitor is connected to the bit line has been described. However, the data is input by the same process even when the terminal of the capacitor is connected to the bit line.

Meanwhile, a process of reading data input to the unit cell C00 by the above-described process is as follows.

To read the data written in the unit cell C00, first, the bit line driving transistor TB0 connected to the bit line B0, the reverse bit line driving transistor TB0 'connected to the bit line B0', and the plate electrode A driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the plate electrode driving transistor TP0 connected to the line P0 to turn on each of the transistors TB0, TB0 ', TP0. .

In this state, the average voltage of the upper voltage and the lower voltage is applied to the source electrodes of the bit line driving transistor TB0 and the reverse bit line driving transistor TB0 ', and the lower voltage is applied to the source electrode of the plate electrode driving transistor TP0. Is applied.

At this time, since the capacitor polarized in the positive (+) or negative (-) direction is connected to the bit line (B0), the output voltage is changed, but because the capacitor is not connected to the reverse bit line, that is, the applied voltage, that is, The average voltage is output as it is.

Therefore, when the voltage output from the bit line B0 is compared with the voltage output from the inverse bit line B0 ', the data value is read as' 1' or '0'. That is, if the voltage output from the bit line B0 is greater than the voltage output from the inverse bit line B0 ', it is read out as data' 1 ', and if it is small, it is read out as data' 0 '.

According to the present embodiment described above, in the first embodiment, a voltage is applied to the dummy bit line every time data is read from each unit cell, whereas in the present embodiment, the output voltage of the bit line or the reverse bit line provided in each cell is different. Using as a reference voltage will extend its life.

Example 3

Hereinafter, the present embodiment will be described with reference to FIG. 5. 5 is a circuit diagram showing the structure of the ferroelectric memory according to the present embodiment.

The ferroelectric memory according to the present embodiment has a structure similar to that of the second embodiment, but includes a capacitor at the intersection of the bit line crossing the plate electrode line and the inverse bit line, and the opposite bit line or inverse is outputted inverted with each other. The structure of the ferroelectric memory and the data input / output process according to the present embodiment will be described below.

First, referring to FIG. 5, the structure of the memory according to the present embodiment is as follows.

At this time, the present embodiment has a structure similar to that of FIG. 4, but includes bit lines B0, B1, B2, ... and inverse bit lines B0 ', B1' that cross the plate electrode lines P0, P1, P2, .... Capacitors are formed for the entire intersections of the points B2 ', ..., so that each unit cell (shown in broken lines in FIG. 5) has two capacitors. That is, in the ferroelectric memory according to the present embodiment, a total of 2M × N capacitors are provided.

Hereinafter, a process of inputting / outputting data in the ferroelectric memory having the above-described structure according to the present embodiment will be described.

First, a process of inputting data '1' into the unit cell C00 will be described.

In order to input the data '1', first, a driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the bit line driving transistor TB0 connected to the bit line B0. The upper voltage 5 [V] is applied to the source electrode. As a result, the potential of 5 [V] will be applied to the bit line B0.

At this time, since the gate electrodes of the bit line driving transistor TB and the reverse bit line driving transistor TB 'are connected to each other, a reverse bit line paired with the bit line driving transistor TB0 when a driving voltage is applied to the bit line driving transistor TB0 is applied. The driving voltage is also applied to the gate electrode of the driving transistor TB0 ', and a voltage opposite to the voltage applied to the source electrode of the bit line driving transistor TB, that is, a lower voltage, is applied to the source electrode of the source transistor TB0'. B0 ') has a potential of 0V.

At the same time, a driving voltage, for example, 5 V + Vt (threshold voltage) [V] is applied to the gate gate electrode of the plate electrode driving transistor TP0 connected to the plate electrode line P0, and the upper electrode and The average value of the lower voltages is applied, for example 2.5 [V]. As a result, the potential of 0 [V] will be applied to the plate electrode line P0.

Therefore, the ferroelectric film of the capacitor connected to the bit line B0 among the capacitors provided in the cell C00 is polarized in the positive direction due to the potential difference, but the ferroelectric film of the capacitor connected to the reverse bit line B0 'is negative. By polarization in the negative direction, data '1' is written in the capacitor connected to the bit line B0, that is, the capacitor in which the actual data is written, and the capacitor connected to the inverse bit line B0 ', A kind of data '-1' is input to a capacitor into which reference data for reading data is input. At this time,-represents the direction.

On the other hand, the data '0' is made by a process opposite to that described above, and the ferroelectric film of the capacitor connected to the bit line B0 among the capacitors provided in the cell C00 is polarized in the negative direction due to the potential difference. Since the ferroelectric film of the capacitor connected to the inverse bit line B0 'is polarized in the positive direction, data' 0 'is written in the capacitor connected to the bit line B0, that is, the capacitor in which the actual data is written. do.

Meanwhile, a process of reading data input to the unit cell C00 by the above-described process is as follows.

To read the data written in the unit cell C00, first, the bit line driving transistor TB0 connected to the bit line B0, the reverse bit line driving transistor TB0 'connected to the bit line B0', and the plate electrode A driving voltage, for example, 5V + Vt (threshold voltage) [V] is applied to the gate electrode of the plate electrode driving transistor TP0 connected to the line P0 to turn on each of the transistors TB0, TB0 ', TP0. .

In this state, a predetermined voltage, for example, 1.25 [V] is applied to the source electrodes of the bit line driving transistor TB0 and the reverse bit line driving transistor TB0 '.

At this time, since the bit line B0 and the reverse bit line B0 'are polarized in opposite directions, the output voltage of the bit line B0 will be larger or smaller than the input voltage and the reverse bit line B0' ), The output voltage becomes smaller or larger, so that the difference between the two output voltages becomes larger.

Therefore, when the output voltage of the bit line B0 is greater than the output voltage of the inverse bit line B0 ', the data is read out as data' 1 ', and the output voltage of the bit line B0 is set to the inverse bit line B0'. If it is less than the output voltage, it is read as data '0'.

At this time, according to the present embodiment, the degree of integration is further lower than in the case of the second embodiment, but the difference between the output voltage is large, that is, the difference between the read data and the reference voltage becomes larger, thereby increasing the reliability.

According to the present invention described above, the formation range of the memory region itself is reduced by removing the transistors and word lines included in each unit cell in the memory region, and the memory region overlaps the upper portion of the logic circuit region due to the removal of the transistor. By forming it, it is advantageous for high integration. In addition, in some embodiments, the reference voltage is individually used for each cell unit, thereby improving reliability and lifespan.

Claims (18)

A ferroelectric memory having unit cells in an M × N (M and N are integers) array. M bit lines, N plate electrode lines crossing each of the M bit lines, M x N capacitors having one electrode connected to the plate electrode line and the other electrode connected to the bit line at each intersection point of the bit line and the plate electrode line; A bit line driving transistor connected one-to-one with each of the M bit lines to selectively drive a specific bit line among the M bit lines; And a plate electrode line driving transistor connected one-to-one with each of the N plate electrode lines to selectively drive a specific plate electrode line among the N plate electrode lines. The method of claim 1, wherein the ferroelectric memory, The memory region consisting of the M bit lines, the N plate electrode lines, and the M × N capacitors is formed on an upper portion of a logic circuit region of a semiconductor device, and the bit line driving transistor and the plate electrode line driving transistor comprise the logic. A ferroelectric memory, which is formed on a silicon substrate outside a circuit region. The method of claim 1 or 2, wherein the ferroelectric memory, In the state where the bit line and the plate electrode line to which the unit cell to input data are connected are respectively driven by the bit line driving transistor and the plate electrode line driving transistor, Applying an upper voltage to a source electrode of the bit line driving transistor, applying a lower voltage to a source electrode of the plate electrode line driving transistor, and writing a digital data value of '1', And applying a lower voltage to the source electrode of the bit line driving transistor and applying an upper voltage to the source electrode of the plate electrode line driving transistor to record digital data '0'. 4. The ferroelectric memory of claim 3, wherein the upper voltage is 5V and the lower voltage is 0V. The method of claim 3, wherein the ferroelectric memory, In a state where the bit line and the plate electrode line to which the unit cell to read data is connected are respectively driven by the bit line driving transistor and the plate electrode line driving transistor, An average voltage of the upper voltage and the lower voltage is applied to the source electrode of the bit line driving transistor, and a lower voltage is applied to the source electrode of the plate electrode line driving transistor, and then the voltage detected at the terminal and the reference voltage are applied. A ferroelectric memory characterized by comparing data values as '1' or '0'. The method of claim 5, wherein the ferroelectric memory, Further comprising an upper dummy bit line and a lower dummy bit line, And applying an upper voltage to the upper dummy bit line, and applying a lower voltage to the lower dummy bit line, and using the average voltage detected at the end thereof as a reference voltage. A ferroelectric memory having unit cells in an M × N (M and N are integers) array. M bit lines, M reverse bit lines, N plate electrode lines intersecting the M bit lines and the reverse bit lines, respectively; One electrode is connected to the plate electrode line, and the other electrode is alternately connected to the bit line and the reverse bit line in a rupture or attack, and arranged in the form of a black or white pattern of a chessboard. With capacitors, A bit line driving transistor connected one-to-one with each of the M bit lines to selectively drive a specific bit line among the M bit lines; The M reverse bit lines are connected one-to-one to the M reverse bit lines so as to pair with the M bit lines, and when a specific bit line is driven, the reverse bit lines paired with the bit lines are simultaneously driven. Reverse bit line driving transistor, A plate electrode line driving transistor connected to each of the N plate electrode lines one-to-one and selectively driving a specific plate electrode line among the N plate electrode lines Ferroelectric memory having a. The method of claim 7, wherein the ferroelectric memory, The memory region consisting of the M bit lines, the M reverse bit lines, the N plate electrode lines, and the M × N capacitors is formed on an upper portion of the logic circuit region of the semiconductor device. A line driving transistor and a plate electrode line driving transistor are formed in a silicon substrate outside the logic circuit region. The method of claim 7 or 8, wherein the ferroelectric memory, In a state where the bit line or the reverse bit line and the plate electrode line to which the unit cell to input data is connected are driven by the bit line driving transistor or the reverse bit line driving transistor and the plate electrode line driving transistor, respectively. An inverse bit line driving transistor or a bit line driving transistor which applies an upper voltage to a source electrode of a bit line driving transistor or a reverse bit line driving transistor to which the unit cell is connected, and which is paired with the bit line driving transistor or a reverse bit line driving transistor. A lower voltage is applied to the digital data, and a lower voltage is applied to the source electrode of the plate electrode line driving transistor to record digital data '1'. A reverse bit line driving transistor or a bit line driving transistor which applies a lower voltage to a source electrode of a bit line driving transistor or a reverse bit line driving transistor to which the unit cell is connected, and is paired with the bit line driving transistor or a reverse bit line driving transistor. And applying an upper voltage to the source electrode of the plate electrode line driving transistor to write a digital data '0' value. 10. The ferroelectric memory of claim 9, wherein the upper voltage is 5V and the lower voltage is 0V. The method of claim 9, wherein the ferroelectric memory, In a state where the bit line or the reverse bit line and the plate electrode line to which the unit cell to which data is to be read are connected are driven by the bit line driving transistor or the reverse bit line driving transistor and the plate electrode line driving transistor, respectively. The average voltage of the upper voltage and the lower voltage is applied to each of the source electrodes of the bit line driving transistor and the reverse bit line driving transistor to which the unit cell is connected, and the detected voltages detected at the terminals thereof are compared, respectively, and data '1' or ' A ferroelectric memory, which is read out at 0 '. The method of claim 11, wherein the ferroelectric memory, If the voltage detected from the bit line or the reverse bit line connected to the cell to which data is to be read is higher than the voltage detected from the reverse bit line or the bit line paired with the bit line or the reverse bit line, '1' is read. A ferroelectric memory, which is read as '0' when low. A ferroelectric memory having unit cells in an M × N (M and N are integers) array. M bit lines, M reverse bit lines, N plate electrode lines intersecting the M bit lines and the reverse bit lines, respectively; 2M × N capacitors whose one electrode is connected to the plate electrode line and the other electrode is connected to the bit line or the reverse bit line; A bit line driving transistor connected one-to-one with each of the M bit lines to selectively drive a specific bit line among the M bit lines; The M reverse bit lines are connected one-to-one to the M reverse bit lines so as to pair with the M bit lines, and when a specific bit line is driven, the reverse bit lines paired with the bit lines are simultaneously driven. Reverse bit line driving transistor, A plate electrode line driving transistor connected to each of the N plate electrode lines one-to-one and selectively driving a specific plate electrode line among the N plate electrode lines Ferroelectric memory having a. The method of claim 7, wherein the ferroelectric memory, The memory region consisting of the M bit lines, the M reverse bit lines, the N plate electrode lines, and the 2M × N capacitors is formed on an upper portion of the logic circuit region of the semiconductor device. The driving transistor and the plate electrode line driving transistor are formed in the silicon substrate outside the logic circuit region. 15. The method of claim 13 or 14, wherein the ferroelectric memory, In a state where the bit line, the reverse bit line, and the plate electrode line to which the unit cell to input data is connected are driven by the bit line driving transistor, the reverse bit line driving transistor, and the plate electrode line driving transistor, respectively. The upper voltage is applied to the source electrode of the bit line driving transistor to which the unit cell is connected, and the lower voltage is applied to the source electrode of the reverse bit line driving transistor paired with the bit line driving transistor. The average voltage of the upper voltage and the lower voltage is applied to a source electrode to record the digital data '1' value, A lower voltage is applied to a source electrode of a bit line driving transistor to which the unit cell is connected, an upper voltage is applied to a source electrode of an inverse bit line driving transistor paired with the bit line driving transistor, and And a digital data '0' value is recorded by applying an average voltage of the upper voltage and the lower voltage to a source electrode. 16. The ferroelectric memory of claim 15, wherein the upper voltage is 5V and the lower voltage is 0V. The method of claim 15, wherein the ferroelectric memory, In a state where the bit line, the reverse bit line, and the plate electrode line to which the unit cell to read data is connected are driven by the bit line driving transistor, the reverse bit line driving transistor, and the plate electrode line driving transistor, respectively. A predetermined voltage is applied to each of the source electrodes of the bit line driving transistor and the reverse bit line driving transistor to which the unit cell is connected, and then the detection voltages detected at the terminal are compared to read data as '1' or '0'. Ferroelectric memory, characterized in that. The method of claim 11, wherein the ferroelectric memory, If the voltage detected from the bit line or the reverse bit line connected to the cell to which data is to be read is higher than the voltage detected from the reverse bit line or the bit line paired with the bit line or the reverse bit line, '1' is read. A ferroelectric memory, which is read as '0' when low.