KR100314445B1 - vehicle speed measureing method and device by use of measuring method for variable reference clock - Google Patents

Abstract

The present invention relates to a method and apparatus for measuring wheel speed using a variable reference clock technique that can reduce a speed measurement error by varying a period of a reference clock according to a speed. To this end, the present invention uses a first step of checking whether the counter for speed measurement is completed, a second step of determining whether the counter is overflowed upon completion of the counter, and a clipping rate value in case of overflow, and not in case of overflow. A third step of determining a speed section using a counter buffer value, a fourth step of determining a reference clock according to the determined speed section, and a fifth step of setting a new reference clock in the frequency divider using the reference clock And a sixth step of enabling a counter for the next speed measurement, and then a seventh step of exiting the current speed measurement routine. Therefore, the speed measurement error can be minimized and the problem that the speed measurement section is proposed can be solved.

Description

Vehicle speed measuring method and device by use of measuring method for variable reference clock}

The present invention relates to a speed measuring method, and more particularly to a method and apparatus for measuring wheel speed using a variable reference clock technique that can reduce the speed measurement error by varying the period of the reference clock according to the speed.

In order to reliably measure the wheel speed of a vehicle, not only the basic feedback signal of the system controller but also the anti-lock braking system (ABS), traction control, cruise control, etc. It is required. In particular, in measuring wheel speeds, measurement accuracy and measurement latency can directly affect the performance and reliability of vehicle control. Therefore, in order to measure the wheel speed reliably, it is necessary to consider a combination of such measurement accuracy and the effect that the measurement delay can have on driving performance. In addition to the influence of driving performance, the related software processing time and the complexity of hardware implementation in real time implementation are important issues to be considered in designing the wheel speed measurement system.

In general, the method of measuring the rotational speed of a rotating body such as an electric motor, a wheel, etc. is largely performed by analog speed conversion hardware such as a tachogenerator, a microprocessor, a counter, It is divided into two types by digital software that combines additional hard air such as timer. The method based on analog hardware has recently been mainly used in the digital processing method due to the nonlinearity of the transformer itself, the error due to external noise, temperature and deterioration, and the inefficiency of precision hardware.

Next, a speed measurement method by a digital method will be described with reference to the accompanying drawings.

The methods measured by the digital method from the encoder output in pulse form are largely divided into a window method for counting the number of encoder pulses within a fixed time-window and an interval method for measuring the interval between encoder pulses. Are distinguished. In order to improve the accuracy, resolution, processing speed, and measurement range of each method by supplementing the advantages and disadvantages of each method, various modified methods have been developed.

At present, when the wheel speed is to be measured by an ABS ECU (electronic control unit), it is common to input an encoder pulse type signal and measure it by a digital method. In this case, the period between encoder pulses is used to compensate for the shortcomings of the interval method for measuring the period of the encoder pulse or the window method for measuring the number of encoder pulses between given measurement intervals and to improve the measurement range and measurement accuracy. The window / interval method or a modified form thereof is used to measure and combine the number of encoder pulses together.

In this modified form, the Constant Elapsed Time (CET) method is the same as the window / interval method and the measurement method. The implementation is rotated using a single chip microcontroller with free running timer, capture register and interrupt function. Measure the speed. In addition, there is a speed measuring technique of varying the window section according to the range of the rotation speed for the purpose of reducing the processing time of the central processing unit (CPU) to increase the range of the measurable speed. In addition, the Sampled Interval Method (SIM) method, which measures the period of the encoder pulse once in accordance with the entire system cycle (cycle-time), has a disadvantage in that it is less versatile because it uses a specific microcontroller.

Next, the wheel speed measurement error is compared with respect to the window measuring method and the interval measuring method with reference to the accompanying drawings. In this case, the vehicle speed, encoder analysis power, and the like are variable.

1 is a waveform diagram illustrating an interval method, and FIG. 2 is a waveform diagram illustrating the window method.

First, the interval method will be described. The wheel speed P (rpm) is obtained by measuring the encoder pulse period Te using a fixed reference clock whose period is Tc as the interval between two encoder pulses.

Here, Np is the number of encoder pulses per revolution, and Nc is the number of clock pulses in the encoder period Te. In this case, if the measurement resolution is Resol [rpm], this is expressed on the basis of the case where Nc is one difference.

In addition, the percentage rotation speed measurement error Error [%] is as follows.

Next, in the window measuring method of counting the number of encoder pulses within a fixed time interval (window) Tw in the interval method, the wheel speed P [rpm] is

Where Np is the number of encoder pulses per revolution and Nw is the number of encoders in Tw. In this case, assuming that the measurement resolution is Resol [rpm], it is obtained as follows based on the case where Nw is one difference.

Since the interval Te between the encoder pulses is Tw / Nw, the percentage rotation speed measurement error Error [%] is obtained by substituting (1) as follows.

In this way, the speed measurement error obtained in the above formulas (3) and (6) is calculated by changing the number of encoder pulses Np.

4 is a graph illustrating a speed measurement error by the window method and the interval method.

The graph shows that the cycle-time considering the dynamics of the automotive system is generally 10 [msec], so that the measurement window Tw is 10 msec and the wheel radius is 0.292 [m], and the vehicle speed is minimum. It shows the percentage error obtained by changing the creeping speed from 5.0 [km / hr] to 200 [km / hr]. In addition, a graph was obtained for the vehicle speed V [km / hr] by substituting the equation of P = 1000 V / 120 pi R instead of the wheel speed P [rpm]. It is an error obtained by setting the period Tc of the reference clock to 1.0 [μsec] in the interval measurement method.

As can be seen from the graph, in the window measuring method, the error is represented in a form inversely proportional to the wheel speed P as shown in Equation (6), so that the measurement error is large at low speed. For example, when the encoder resolution Np is 45, an error of 100 [%], which is a measurement limit, is obtained when the speed reaches about 15 [km / hr]. In this case, in order to obtain an error within ± 1% of the creeping speed, the encoder resolution must be increased to 13,200 [pulse / revolution]. Thus, the method of increasing the encoder pulse number Np cannot be realized.

In addition, unlike the purpose of precision servo motor speed control, incorporating such expensive precision measurement sensors as vehicle wheel speed sensors is uneconomical and unsuitable for maintenance in view of the harsh operating environment of automobiles. And when considering the method of reducing the error by increasing the Tw, the window length becomes relatively too large considering the cycle-time of the system. Therefore, it is not suitable because it adversely affects the stability of automobile dynamics.

In the interval measuring method, the percentage error is proportional to the wheel speed as in Equation (3). Therefore, the error increases at high speed, and there is a limitation in the wheel speed measurement. The interval measurement method shows that the error decreases as the number of encoder pulses per revolution reduced when the speed measurement system is designed. However, if the number of pulses per revolution is designed to be too small, a problem arises in that the interval between one pulse is widened at a low speed, resulting in overflow of the counter by the reference clock. Therefore, when designing the speed measurement system, it is necessary to select an appropriate encoder pulse and reference clock per revolution. For example, the wheel speed is obtained by the clock number Nc accumulated during the encoder pulse interval. Nc is expressed as follows with respect to the range of the measured wheel speed.

Here, the range of the vehicle speed was set from 5 [km / hr] to 200 [km / hr], tire radius was 0.292 [m], encoder pulse number Np was set to 25 and reference clock period Tc was set to 1 [μsec]. . Therefore, the range of Nc is 1321 Nc 52,839 can be represented by a single unsigned 16-bit register of the controller.

Accordingly, an object of the present invention is to provide a method and apparatus for measuring wheel speed using a variable reference clock technique that can minimize measurement errors by dividing a plurality of speed sections and varying a period of a reference clock for each section.

Another object of the present invention is to provide a method and apparatus for measuring wheel speed using a variable reference clock technique that can be applied to all systems by configuring as described above.

1 is a waveform diagram of an interval method;

2 is a waveform diagram of a window method;

3 is a waveform diagram for a SIM method;

4 is a graph showing a speed measurement error according to the window method and the interval method;

5 is a waveform diagram of a speed measuring method according to the VRC method according to the present invention;

6 is an exemplary diagram for a configuration of a VRC measuring method;

7 is a pulse counter logic block diagram used in the VRC measurement method;

8 is an operation flow chart for measuring the speed according to the VRC measurement method,

9 is a graph showing a speed measurement error according to the RC measurement method,

10 is a graph showing a speed measurement error according to the VRC measurement method.

* Description of the symbols for the main parts of the drawings *

10: system controller 20: CPU

30: pulse counter 40: vehicle

50: divider 52: internal reference clock generator

54: counter 56: buffer

58: status register 60: control register

62: pulse detection logic circuit

The wheel speed measuring method using the variable reference clock according to the present invention for achieving the above object comprises a first step of checking whether the counter for speed measurement is completed, a second step of determining whether the counter is overflowed, and overflow A third step of determining a speed section using a clipping speed value in the case of a low value and a counter buffer value in the case of no overflow; a fourth step of determining a reference clock according to the determined speed section; and the reference clock A fifth step of setting a new reference clock in the frequency divider, a sixth step of enabling a counter for the next speed measurement, and a seventh step of exiting the current speed measurement routine. It is done.

In addition, the wheel speed measuring apparatus using a variable reference clock according to the present invention for achieving the above object is divided into a frequency divider for storing a value for dispensing a reference reference clock, and a reference reference clock to divide the variable into the division value An internal reference clock generator for generating a reference clock, a pulse detection logic circuit for detecting an input encoder pulse, and a variable reference clock for input, and only the first two pulses of the encoder pulse when the pulse detection logic circuit is enabled And a pulse counter including a counter for counting, a status register in which a complete bit is set after completion of the counter, and a central processing unit for varying a reference clock by controlling a frequency divider in the pulse counter.

That is, the present invention is composed of a general purpose microprocessor and logic circuits that perform the functions of an encoder pulse counter.

The present invention described above is similar to the SIM method in measuring the period of the encoder pulse only once per system cycle, but the relative clock error can be reduced by changing the basic clock. In addition, in the construction of the hardware, the present invention can be integrated with a general-purpose microprocessor, so that it is applicable to all systems.

That is, the wheel speed measuring method using the variable reference clock technique according to the present invention divides the speed into several sections and varies the period of the reference clock for each section. Therefore, the measurement error increases with the speed increase of the conventional speed measurement method, thereby solving the problem of the proposed range of the speed measurement.

Next, a wheel speed measuring method and apparatus using a VRC technique according to the present invention will be described with reference to the accompanying drawings.

5 is a waveform diagram illustrating a speed measurement method using the VRC technique of the present invention.

In this case, the system cycle is the range from generation of the enable signal to generation of the next enable signal. As shown, according to the present invention, the encoder pulse period is set in various ways, thereby changing the reference clock.

Since the speed measuring method using the VRC technique measures the period of the encoder pulse once per system cycle, this is similar to the SIM method described in FIG. However, the present invention can reduce the relative error according to the speed by varying the basic clock according to the encoder pulse period.

6 is an exemplary view showing the configuration of a VRC measuring method according to the present invention.

As shown in the present invention, the pulse counter 30 inputs an encoder pulse signal generated as the vehicle 40 operates and generates a variable reference clock signal according to the present invention, and an encoder input to the pulse counter 30. And a CPU 20 that controls the pulse counter 30 so that the period of the reference clock varies according to the pulse. The pulse counter 30 and the CPU 20 are included in the system controller 10. That is, the present invention is composed of a general purpose microprocessor and logic circuits that perform the functions of an encoder pulse counter.

The operation of the above configuration will now be described.

When the vehicle 40 operates, a pulse signal is generated accordingly, and the period of the pulse signal is changed according to the speed of the vehicle. Accordingly, the speed of the vehicle 40 may be measured using the pulse signal. In this case, the pulse signal input to the pulse counter 30 is called an encoder pulse. That is, when the vehicle 40 operates, the encoder pulse signal generated thereby is input to the pulse counter 30 in the system controller 10.

The pulse counter 30 counts the encoder pulse signal input under the control of the reference clock signal, thereby calculating the speed of the vehicle 40. In this case, the reference clock signal according to the encoder pulse signal input to the pulse counter is changed by the control of the CPU 20.

Next, the pulse counter 30 of the present invention will be described in more detail with reference to FIG. 7.

7 is a logic block diagram of the pulse counter 30 used in the VRC measurement method.

The pulse counter 30 includes a divider 50 for dividing a reference reference clock, an internal reference clock generator 52 for generating the divided clock, and a counter for inputting an output of the internal reference clock generator 52. (54), a buffer 56 for temporarily storing a counter value between one pulse, a status register 58 to which the pulse signal is input, and a pulse detection logic circuit 62 according to the status register 58. And a control register 60 for outputting a signal.

The pulse detection logic circuit 62 detects an input encoder pulse signal and controls the counter 54 to be counted only for the first two pulses when the enable is active. In addition, the divider 50 stores a value for dividing the reference reference clock, and the value is written from the CPU 20 to vary the reference clock period for each section.

Then, the operation and function of the pulse counter 30 will be described.

When an encoder pulse signal is input to the pulse counter 30, the pulse detection logic circuit 62 in the pulse counter 30 detects the start and end of one period of the encoder pulse. In this case, when the enable is active, the pulse detection logic circuit 62 controls the counter 54 to count only the first two pulses of the input encoder pulse. When the counter 54 completes the counting, the counter value between one pulse output from the counter 54 is input to the buffer 56 and stored for a while. The value is then input to state register 58, indicating that the count is complete by setting the Complete bit.

Next, when the period of the encoder pulse signal is input to the pulse counter 30 is variable, look at the generation of the reference clock to measure the speed accordingly. When the reference clock signal is input to the internal reference clock generator 52 inside the pulse counter 30, the internal reference clock generator 52 generates a divided clock signal under the control of the frequency divider 50. The clock signal generated by the internal reference clock generator 52 is input to the counter 54. Here, the divider 50 varies the period of the reference clock for each section by dividing the reference reference clock.

That is, in this way, the reference clock signal is input to the counter 54, and the counter 54 is controlled by an encoder pulse. As a result, the pulse counter 30 has a variable reference clock signal according to the period of the encoder pulse. Is output.

8 is a software flow chart for speed measurement according to the VRC technique.

The operation of the present invention will be described with reference to the operation flowchart.

It is checked whether the count is completed at a predetermined cycle time, that is, every system cycle (step 110). At this time, the counter counts only the first two cycle pulses of the encoder pulse signal of the same cycle input to the pulse detection logic circuit. In this way, when it is confirmed that the count has not been completed, the speed measurement routine is exited.

However, if the count is complete, it is then checked whether an overflow has occurred (step 120). In this way, if no overflow occurs, the counter value is output to the buffer and stored for a while, and then the speed is calculated by converting the counter value stored in the buffer into Tc (reference clock period) for each section. Then, the reference clock period in the future is determined from the calculated new speed value (step 140).

After this, a new divider value is written to the divider of the pulse counter according to the reference clock period, and the counter is enabled for the next speed measurement (step 150). After that, the cycle measurement routine is exited by clearing cycle_time_flag to 0 (step 160).

The overflow will be described when the overflow is confirmed. Overflow means that the result of the arithmetic operation exceeds the range of numbers that the register or counter can accommodate. When overflow occurs, the creeping speed, which is the calculated minimum speed, is determined as a new speed value. step). Subsequent operations are the same as when no operation occurs.

As described above, when the enable signal of the pulse detection logic circuit is activated, the pulse counter is counted by an internal reference clock signal that divides two incoming encoder pulses by a new divider value. Then, the count value is output to the buffer and stored for a while, and the counter value stored in the buffer is converted into Tc (reference clock period) for each section to calculate the speed.

Next, the speed measurement error according to the reference clock in the VRC speed measuring method of the present invention operating as described above will be described with reference to FIGS. 9 and 10. 9 is a graph of a speed measurement error according to a variable clock, and FIG. 10 is a graph of a speed measurement error according to the VRC measuring method of the present invention.

Here, the vehicle speed ranges from 5 [km / hr] to 200 [km / hr], tire radius is 0.292 [m], number of encoder pulses per revolution Np is 25, and variable section speed is 40 [km / hr with high error increase rate. hr] and 80 [km / hr]. And, when the reference clock period Tc is set to 1, 0.5, 0.25 [μsec], relative errors are shown for each section. That is, comparing FIG. 8 and FIG. 9, the speed measurement error according to the present invention VRC measuring method is L1 according to the increase in speed. M2 It has a speed measurement error value in the H3 section. That is, the increase of the speed measurement error is suppressed by varying the period of the reference clock as the speed increases.

As described above, the present invention divides a plurality of speed sections and measures the speed by varying a period of a reference clock for each speed section. This reduces the speed measurement error. In addition, by solving the problem that the speed measurement error is increased according to the speed increase, the present invention does not propose a speed measurement range.

That is, the present invention can reduce the relative error for each speed section by using the VRC technique. This improves the reliability of the overall system, and the present invention is also used to improve the performance of ABS, traction control, cruise control and the like.

In addition, the pulse counter logic circuit in the present invention does not require any additional hardware by using the VHDL code. And by doing so, the present invention has high fluidity as a general-purpose speed measurement system.

The wheel speed measuring method and apparatus according to the present invention configured as described above has the advantage of minimizing the speed measurement error by measuring the speed by varying the period of the reference clock according to the speed of the vehicle. In addition, the present invention improves the performance of the system when applied to a system requiring safety and reliability by minimizing the speed measurement error according to the speed increase.

In addition, the present invention has the advantage that it can be applied to all systems because it can be linked to a general purpose microprocessor without using a specific microcontroller by changing the period of the reference clock according to the speed in software.

Claims (2)

A first step of checking whether a counter for speed measurement is completed; Determining whether the counter is overflowed upon completion of the counter; A third step of determining a speed section using a clipping rate value in case of overflow and a counter buffer value in case of no overflow; Determining a reference clock according to the determined speed section; A fifth step of setting a new reference clock in the frequency divider using the reference clock; A sixth step of enabling a counter for a next speed measurement; And a seventh step of exiting the current speed measurement routine. A divider for storing a value for dividing the reference reference clock; An internal reference clock generator configured to input a reference reference clock and divide the reference reference clock to generate a variable reference clock; A pulse detection logic circuit for detecting an input encoder pulse; A counter for inputting the variable reference clock and counting only the first two pulses of the encoder pulse when the pulse detection logic circuit is enabled; A pulse counter provided with a status register in which a complete bit is set after completion of the counter; And a central processing unit for varying the reference clock by controlling the frequency divider in the pulse counter.