KR100310542B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100310542B1 KR100310542B1 KR1019980035027A KR19980035027A KR100310542B1 KR 100310542 B1 KR100310542 B1 KR 100310542B1 KR 1019980035027 A KR1019980035027 A KR 1019980035027A KR 19980035027 A KR19980035027 A KR 19980035027A KR 100310542 B1 KR100310542 B1 KR 100310542B1
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- forming
- peripheral circuit
- conductor
- insulating film
- circuit portion
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title abstract description 16
- 230000002093 peripheral effect Effects 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 72
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 24
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000002955 isolation Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/01—Manufacture or treatment
- H10D1/041—Manufacture or treatment of capacitors having no potential barriers
- H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 셀부의 캐패시터로 인한 단차를 완화시키기 위하여 주변회로부에 PSG 절연막을 형성하되, 상기 PSG 절연막 형성공정전에 주변회로부에 일종의 콘택패드를 형성하고 후속공정으로 상기 콘택패드에 접속되는 금속배선을 형성함으로써 콘택깊이를 감소시켜 전도성이 좋으나 단차피복비가 나쁜 알루미늄으로 금속배선을 형성할 수 있어 반도체소자의 동작특성을 향상시키고 후속공정을 용이하게 실시할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술이다.The present invention relates to a method for manufacturing a semiconductor device, in which a PSG insulating film is formed in a peripheral circuit part to alleviate a step caused by a capacitor of a cell part, a kind of contact pad is formed in the peripheral circuit part before the PSG insulating film forming process, By forming a metal wiring connected to the contact pad, the contact depth can be reduced to form a metal wiring made of aluminum with good conductivity but poor step coverage, thereby improving the operation characteristics of the semiconductor device and facilitating subsequent processing. It is a technology that can improve the characteristics and reliability of the device.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 DRAM 의 경우 메모리 셀 ( memory cell ) 과 주변회로지역 간의 단차를 최소화하며 금속콘택의 깊이를 얕게 형성하게 함으로써 금속 콘택공정시 기판의 손상으로 인해 발생하는 누설전류를 방지하는 동시에 금속배선의 선저항을 감소시켜 전류를 빨리 흘릴수 있는 알루미늄으로 금속배선을 형성할 수 있도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in the case of a DRAM, a step between the memory cell and a peripheral circuit area is minimized and the depth of the metal contact is made shallow, resulting from damage to the substrate during the metal contact process. The present invention relates to a technology for forming a metal wiring from aluminum capable of flowing a current quickly by preventing leakage current and reducing wire resistance of the metal wiring.
DRAM 반도체 소자 제조시 셀부와 주변회로부 간에는 캐패시터에 기인한 단차가 존재한다.When manufacturing a DRAM semiconductor device, there is a step due to a capacitor between the cell portion and the peripheral circuit portion.
반도체 소자의 집적도를 증가시켜 주기 위하여 cell뿐만 아니라 주변회로가 차지하는 면적을 최대한 줄여주는 것이 주어진 웨이퍼의 면적에서 최대로 많은 디바이스를 만들 수 있다. 이를 위하여 셀부와 주변회로부 사이에 존재하는 면적 또한 최대한 줄이고 있다.Reducing the area occupied by not only cells but also peripheral circuits in order to increase the integration density of semiconductor devices can make the maximum number of devices in a given wafer area. To this end, the area existing between the cell portion and the peripheral circuit portion is also reduced as much as possible.
그래서 원하는 캐패시터의 면적을 확보하기 위해서는 캐패시터의 높이를 최대한 높여주어야 한다. 그러나 캐패시터의 높이가 높아지면 셀부와 주변회로 지역간의 단차가 더 커지게 되고 그러면 후속 공정시 특히 금속 박막의 패턴닝 공정시 단차에 기인한 포토마스크 작업의 공정 마진 ( margin ) 이 거의 없어지게 되고 단차가 형성되는 지역에 금속배선을 형성하는 식각을 한 후에 큰 단차로 인하여 제거되지 못한 금속 성분의 잔존물이 남게되어 인접한 금속배선과의 단락이 발생하여 원하는 디바이스의 동작을 하지 못하게 할 수 있는 문제점이 있다.Therefore, in order to secure the desired area of the capacitor, the height of the capacitor should be increased as much as possible. However, as the height of the capacitor increases, the step height between the cell portion and the peripheral circuit area becomes larger, so that the process margin of the photomask operation due to the step difference in the subsequent process, especially in the patterning process of the metal thin film, is almost eliminated After etching to form the metal wiring in the area where is formed, there is a problem that the residual of the metal component that could not be removed due to the large step is left, resulting in a short circuit with the adjacent metal wiring to prevent the operation of the desired device. .
도 1 은 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.
먼저, 반도체기판(20) 상부에 소자분리산화막(1), 게이트전극(2), 비트라인(3)을 형성하고 그 상부를 평탄화시키는 제1층간절연막(4)을 형성한다.First, a device isolation oxide film 1, a gate electrode 2, and a bit line 3 are formed on the semiconductor substrate 20, and a first interlayer insulating film 4 is formed to planarize an upper portion thereof.
그리고, 저장전극 콘택공정으로 상기 반도체기판(20)을 노출시키는 저장전극 콘택홀을 형성하고 상기 콘택홀을 통하여 상기 반도체기판(20)에 접속되는 캐패시터를 셀부에 형성하고 주변회로부에는 PSG 절연막(6)을 형성한다.In addition, a storage electrode contact hole for exposing the semiconductor substrate 20 is formed by a storage electrode contact process, and a capacitor connected to the semiconductor substrate 20 through the contact hole is formed in the cell portion, and the PSG insulating film 6 is formed in the peripheral circuit portion. ).
이때, 상기 캐패시터는 제1다결정실리콘막(5) 및 제2다결정실리콘막(8)으로 형성된 하부전극인 저장전극, 유전체막(10) 그리고 제3다결정실리콘막(11)으로 형성된 상부전극인 플레이트전극으로 형성된 것이다.In this case, the capacitor is a plate which is an upper electrode formed of a storage electrode, a dielectric film 10, and a third polysilicon film 11, which are lower electrodes formed of the first polycrystalline silicon film 5 and the second polycrystalline silicon film 8. It is formed as an electrode.
그 다음에, 셀부 상부에 제2층간절연막(13)을 형성한다.Next, a second interlayer insulating film 13 is formed over the cell portion.
그리고, 금속배선 콘택마스크(도시안됨)를 이용한 식각공정으로 상기 반도체기판(10)의 불순물 접합영역, 게이트전극(2), 비트라인(3)을 각각 노출시키는 금속배선 콘택홀을 형성한다.A metal wiring contact hole exposing the impurity junction region, the gate electrode 2 and the bit line 3 of the semiconductor substrate 10 is formed by an etching process using a metal wiring contact mask (not shown).
그리고, 상기 콘택홀을 통하여 상기 반도체기판(10)의 불순물 접합영역, 게이트전극(2), 비트라인(3)에 접속되는 금속배선(14)을 형성한다. (도 1)A metal wiring 14 connected to the impurity junction region, the gate electrode 2 and the bit line 3 of the semiconductor substrate 10 is formed through the contact hole. (Figure 1)
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 셀부와 주변회로부의 단차를 완화시키고 금속 콘택공정을 형성하기 전에 콘택길이를 감소시킬 수 있도록 비트라인의 형성공정후 일종의 콘택패드를 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the semiconductor device is formed by forming a kind of contact pad after the bit line forming process so as to alleviate the step difference between the cell portion and the peripheral circuit portion and reduce the contact length before forming the metal contact process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that improves the characteristics and reliability of the device and thereby enables high integration of the semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 제조방법을 도시한 단면도.1 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2k 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
도 3a 내지 도 3c 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : 소자분리산화막 2 : 게이트용 다결정실리콘막1: device isolation oxide film 2: polysilicon film for gate
3 : 비트라인용 다결정실리콘막 4 : 제1차 층간절연막3: polysilicon film for bit line 4: primary interlayer insulating film
5 : 제1다결정실리콘막 6 : PSG 절연막5: first polysilicon film 6: PSG insulating film
7 : 제2감광막패턴 8 : 제2다결정실리콘막7: second photosensitive film pattern 8: second polycrystalline silicon film
9 : 제3감광막패턴 10 : 유전체막9: third photosensitive film pattern 10: dielectric film
11 : 제3다결정실리콘막 12 : 제4감광막패턴11: third polycrystalline silicon film 12: fourth photosensitive film pattern
13 : 제2층간절연막 14 : 금속박막13 second interlayer insulating film 14 metal thin film
15 : 제3층간절연막,CVD산화막 16 : 제1감광막패턴15: third interlayer insulating film, CVD oxide film 16: first photosensitive film pattern
17 : 주변회로의 금속콘택 형성을 위한 섬형태의 감광막17: island type photosensitive film for forming metal contact of peripheral circuit
20 : 반도체기판20: semiconductor substrate
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a semiconductor device manufacturing method according to the present invention,
반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate;
상기 반도체기판의 셀부와 주변회로부에 각각 콘택홀을 형성하는 공정과,Forming contact holes in the cell portion and the peripheral circuit portion of the semiconductor substrate, respectively;
상기 콘택홀을 매립하는 제1도전체를 형성하는 공정과,Forming a first conductor filling the contact hole;
상기 제1도전체의 주변회로부를 패터닝하되, 후속 금속배선 콘택공정시 콘택패드로 사용되는 공정과,Patterning the peripheral circuit portion of the first conductor, wherein the process is used as a contact pad during a subsequent metallization contact process;
상기 반도체기판 상부에 PSG 절연막을 형성하는 공정과,Forming a PSG insulating film on the semiconductor substrate;
상기 PSG 절연막을 저장전극마스크를 이용하여 패터닝하는 공정과,Patterning the PSG insulating layer using a storage electrode mask;
전체표면상부에 제2도전체를 일정두께 형성하는 공정과,Forming a second thickness on the entire surface of the second conductor;
상기 주변회로부만을 도포하는 마스크를 이용하여 셀부의 제2도전체를 이방성식각함으로써 상기 PSG 절연막의 측벽에 제2도전체 스페이서를 형성하는 공정과,Forming a second conductive spacer on the sidewall of the PSG insulating film by anisotropically etching the second conductive portion of the cell portion using a mask for coating only the peripheral circuit portion;
전체표면상부에 유전체막과 플레이트전극을 형성하는 공정과,Forming a dielectric film and a plate electrode on the entire surface;
상기 셀부만을 도포하는 마스크를 이용하여 주변회로부의 플레이트전극, 유전체막 및 제2도전체를 식각하는 공정과,Etching the plate electrode, the dielectric film, and the second conductor of the peripheral circuit portion by using a mask for coating only the cell portion;
전체표면상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
상기 주변회로부의 제1도전체에 콘택되는 금속배선을 형성하는 공정을 포함하는 것을 제1특징으로한다.It is a 1st characteristic that the process includes forming the metal wiring contacted with the 1st conductor of the said peripheral circuit part.
또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은,In addition, the manufacturing method of the semiconductor device according to the present invention in order to achieve the above object,
반도체기판 상부에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the semiconductor substrate;
상기 반도체기판의 셀부와 주변회로부에 각각 콘택홀을 형성하는 공정과,Forming contact holes in the cell portion and the peripheral circuit portion of the semiconductor substrate, respectively;
상기 콘택홀을 매립하는 제1도전체를 형성하는 공정과,Forming a first conductor filling the contact hole;
상기 제1도전체의 주변회로부를 패터닝하되, 후속 금속배선 콘택공정시 콘택패드로 사용되는 공정과,Patterning the peripheral circuit portion of the first conductor, wherein the process is used as a contact pad during a subsequent metallization contact process;
상기 반도체기판 상부에 PSG 절연막을 형성하는 공정과,Forming a PSG insulating film on the semiconductor substrate;
상기 PSG 절연막을 저장전극마스크를 이용하여 패터닝하는 공정과,Patterning the PSG insulating layer using a storage electrode mask;
전체표면상부에 제2도전체를 일정두께 형성하는 공정과,Forming a second thickness on the entire surface of the second conductor;
상기 제2도전체를 일정두께 식각하여 상기 PSG 절연막의 측벽에 제2도전체 스페이서를 형성하는 공정과,Etching the second conductor to a predetermined thickness to form a second conductor spacer on a sidewall of the PSG insulating film;
상기 주변회로부만을 도포하는 감광막패턴을 형성하고 상기 PSG 절연막을 제거하는 공정과,Forming a photoresist pattern for coating only the peripheral circuit portion and removing the PSG insulating film;
상기 감광막패턴을 제거하는 공정과,Removing the photoresist pattern;
전체표면상부에 유전체막과 플레이트전극을 형성하는 공정과,Forming a dielectric film and a plate electrode on the entire surface;
상기 셀부만을 도포하는 마스크를 이용하여 주변회로부의 플레이트전극, 유전체막 및 제2도전체를 식각하는 공정과,Etching the plate electrode, the dielectric film, and the second conductor of the peripheral circuit portion by using a mask for coating only the cell portion;
전체표면상부에 제2층간절연막을 형성하는 공정과,Forming a second interlayer insulating film over the entire surface;
상기 주변회로부의 제1도전체에 콘택되는 금속배선을 형성하는 공정을 포함하는 것을 제2특징으로한다.It is a 2nd characteristic that the process includes forming the metal wiring contacted with the 1st conductor of the said peripheral circuit part.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
본 발명의 경우, 캐패시터의 높이에 기인한 셀부와 주변회로 지역 간의 단차를 최소화하는 방안을 강구하였다. 기존에 DRAM 제조시 일반적으로 사용되는 실린더 형태의 캐패시터를 형성할 때 사용되는 PSG 산화막을 보면 다결정실리콘막으로 실린더형의 기둥을 제조하기 위해 사용되고 추후 이 박막은 제거해 버린다. 그런데, 본 발명의 경우 이 PSG 산화막을 주변회로 지역에 존재하게 함으로써 주변회로 지역의 높이를 셀부와 동일하게 유지시켜주어 금속배선 공정과 같은 후속공정시 많은 공정 마진을 가질 수 있도록 한다.In the present invention, a method of minimizing the step difference between the cell portion and the peripheral circuit region due to the height of the capacitor was devised. The PSG oxide film, which is used to form a capacitor in the form of a cylinder, which is generally used in DRAM manufacturing, is used to manufacture a cylindrical pillar with a polysilicon film, and the thin film is removed later. However, in the present invention, the PSG oxide film is present in the peripheral circuit region so that the height of the peripheral circuit region is maintained to be the same as that of the cell portion, so that a large process margin can be obtained in a subsequent process such as a metal wiring process.
또한, 본 발명의 경우 캐패시터를 반도체기판에 연결하기 위해 콘택홀을 형성할 때, 주변회로 지역의 금속배선에 연결될 콘택홀도 형성시켜 주고 이를 매립하는 도전체를 증착시키고 금속 콘택이 형성될 부분에 포토마스크의 작업을 통하여 일종의 콘택패드를 만들어 줌으로써 후속공정인 금속콘택공정시 콘택 깊이를 감소시켜 콘택공정을 용이하게 하고 반도체기판이 손상되는 현상을 방지할 수 있다.In addition, in the present invention, when the contact hole is formed to connect the capacitor to the semiconductor substrate, it also forms a contact hole to be connected to the metal wiring in the peripheral circuit area, deposits a conductor filling the buried material, and forms a portion in which the metal contact is to be formed. By making a kind of contact pad through the operation of the photomask, it is possible to reduce the contact depth during the subsequent metal contact process, thereby facilitating the contact process and preventing the semiconductor substrate from being damaged.
그리고, 낮은 콘택 깊이로 인하여 단차피복비가 나쁘지만 전도성이 우수한 알루미늄으로 금속배선을 형성할 수 있도록 하여 반도체소자의 동작 특성을 향상시킬 수 있는 것이다.In addition, due to the low contact depth, the step coverage ratio is bad, but it is possible to form a metal wiring with aluminum having excellent conductivity, thereby improving operating characteristics of the semiconductor device.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2k 는 본 발명의 제1 실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
먼저, 반도체기판(20) 상부에 소자분리산화막(1), 게이트전극(2), 비트라인(3)을 형성하고 그 상부를 평탄화시키는 제1층간절연막(4)을 형성한다.First, a device isolation oxide film 1, a gate electrode 2, and a bit line 3 are formed on the semiconductor substrate 20, and a first interlayer insulating film 4 is formed to planarize an upper portion thereof.
그리고, 상기 제1층간절연막(4) 상부에 제1감광막패턴(16)을 형성한다. 이때, 상기 제1감광막패턴(16)은 셀부와 주변회로부에 동시에 형성한다.A first photoresist layer pattern 16 is formed on the first interlayer insulating layer 4. In this case, the first photoresist layer pattern 16 is simultaneously formed in the cell unit and the peripheral circuit unit.
이때, 상기 셀부의 제1감광막패턴(16)은 저장전극 콘택홀을 형성할 수 있도록 형성하고 상기 주변회로부의 제1감광막패턴(16)은 금속배선 콘택홀을 형성할 수 있도록 형성된 것이다. (도 2a)In this case, the first photoresist pattern 16 of the cell part may be formed to form a storage electrode contact hole, and the first photoresist pattern 16 of the peripheral circuit part may be formed to form a metal wiring contact hole. (FIG. 2A)
그 다음, 상기 제1감광막패턴(16)을 마스크로하여 상기 반도체기판(20)을 노출시키는 저장전극 콘택홀을 셀부에 형성하는 동시에 주변회로부에 각각 반도체기판(20), 게이트전극(2) 및 비트라인(3)을 노출시키는 금속배선 콘택홀을 형성한다. (도 2b)Next, a storage electrode contact hole for exposing the semiconductor substrate 20 is formed in the cell part by using the first photoresist pattern 16 as a mask, and the semiconductor substrate 20, the gate electrode 2, and the peripheral circuit part are respectively formed. A metal wiring contact hole exposing the bit line 3 is formed. (FIG. 2B)
그리고, 상기 저장전극 및 금속배선 콘택홀 측벽에 절연막 스페이서(도시안됨)를 형성한다. 그리고, 상기 콘택홀을 매립하는 제1다결정실리콘막(5)을 전체표면상부에 일정두께 형성하고, 그 상부에 주변회로부의 금속콘택 형성을 위한 섬형태의 감광막(17)을 형성하고 이를 마스크로하여 상기 제1다결정실리콘막(5)을 패터닝하되, 후속공정으로 금속배선과 각각 콘택될 수 있도록 형성한다.An insulating layer spacer (not shown) is formed on sidewalls of the storage electrode and the metal wiring contact hole. The first polysilicon film 5 filling the contact hole is formed to have a predetermined thickness on the entire surface, and an island-type photosensitive film 17 for forming a metal contact on the peripheral circuit part is formed on the upper surface of the first polycrystalline silicon film 5, which is used as a mask. By patterning the first polysilicon film 5, it is formed to be in contact with the metal wiring in a subsequent process.
그 다음에, 상기 섬형태의 감광막(17)을 제거한다. (도 2c, 도 2d)Then, the island-shaped photosensitive film 17 is removed. (FIG. 2C, FIG. 2D)
그리고, 캐패시터의 높이를 형성시켜주는 PSG 절연막(6)을 증착시킨다. 그리고, 상기 PSG 절연막(6) 상부에 저장전극마스크(도시안됨)를 이용한 노광 및 현상공정으로 제2감광막패턴(7)을 형성한다. (도 2e)Then, the PSG insulating film 6 which forms the height of the capacitor is deposited. The second photoresist layer pattern 7 is formed on the PSG insulating layer 6 by an exposure and development process using a storage electrode mask (not shown). (FIG. 2E)
그리고, 상기 제2감광막패턴(7)을 마스크로하여 상기 PSG 절연막(6)과 제1다결정실리콘막(5)을 식각하고, 상기 제2감광막패턴(7)을 제거한다.The PSG insulating layer 6 and the first polysilicon layer 5 are etched using the second photoresist pattern 7 as a mask, and the second photoresist pattern 7 is removed.
그 다음에, 전체표면상부에 제2다결정실리콘막(8)을 일정두께 형성하고 그 상부에 상기 주변회로부를 도포하는 제3감광막패턴(9)을 형성한다.Next, a second polycrystalline silicon film 8 is formed on the entire surface with a predetermined thickness, and a third photosensitive film pattern 9 is formed on the upper portion of the second polycrystalline silicon film 8 to apply the peripheral circuit portion.
그리고, 상기 제3감광막패턴(9)을 마스크로하여 상기 제2다결정실리콘막(8)을 전면 이방성식각공정을 실시함으로써 셀부의 상기 PSG 절연막(6)의 측벽에 제2다결정실리콘막(8) 스페이서가 형성된다. (도 2f)The second polysilicon film 8 is formed on the sidewall of the PSG insulating film 6 of the cell portion by performing an anisotropic etching process on the second polysilicon film 8 using the third photoresist pattern 9 as a mask. Spacers are formed. (FIG. 2F)
그 다음에, 상기 제3감광막패턴(9)을 제거하고, 전체표면상부에 유전체막(10)과 플레이트전극인 제3다결정실리콘막(11)을 형성함으로써 캐패시터를 형성한다. (도 2g)Next, the third photosensitive film pattern 9 is removed, and a capacitor is formed by forming the dielectric film 10 and the third polysilicon film 11, which is a plate electrode, on the entire surface. (Fig. 2g)
그리고, 상기 셀부만을 도포하여 주변회로부만을 노출시키는 제4감광막패턴(12)을 형성하고 이를 이용하여 상기 제3다결정실리콘막(11), 유전체막(10) 및 제2다결정실리콘막(8)을 식각한다.In addition, a fourth photoresist film pattern 12 is formed to apply only the cell part to expose only the peripheral circuit part, and the third polysilicon film 11, the dielectric film 10, and the second polycrystalline silicon film 8 are formed using the fourth photoresist film pattern 12. Etch it.
그 다음에, 상기 제2감광막패턴(12)을 제거한다. (도 2h, 도 2i)Next, the second photoresist pattern 12 is removed. (FIG. 2H, FIG. 2I)
그리고, 전체표면상부에 제2층간절연막(13)을 형성하고 그 상부에 금속배선(14)을 형성한다.Then, the second interlayer insulating film 13 is formed on the entire surface, and the metal wiring 14 is formed thereon.
이때, 상기 금속배선(14)는 상기 주변회로부의 제1다결정실리콘막(5)에 접속되도록 콘택시킨다. (도 2k)At this time, the metal wiring 14 is brought into contact with the first polysilicon film 5 of the peripheral circuit portion. (FIG. 2K)
도 3a 내지 도 3c 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도로서, 상기 제1실시예의 도 2e 도의 공정후의 공정을 도시한 것이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, and illustrate a process after the process of FIG. 2E in the first embodiment.
먼저, 상기 제2감광막패턴(7)을 마스크로하여 상기 제1층간절연막(4)을 노출시키는 PSG 절연막(6)과 제1다결정실리콘막(5)을 식각함으로써 패터닝하고, 그 측벽에 제2다결정실리콘막(8)으로 스페이서를 형성한다. (도 3a)First, the PSG insulating film 6 exposing the first interlayer insulating film 4 and the first polysilicon film 5 are patterned by etching the second photoresist film pattern 7 as a mask, and the second sidewalls are patterned by etching. A spacer is formed from the polysilicon film 8. (FIG. 3A)
그 다음에, 상기 주변회로부를 도포하는 제3감광막패턴(9)을 형성하고 상기 셀부의 PSG 절연막(6)을 제거한다. (도 3b)Next, a third photosensitive film pattern 9 is formed to apply the peripheral circuit portion, and the PSG insulating film 6 of the cell portion is removed. (FIG. 3B)
그리고, 상기 제3감광막패턴(9)을 제거하고 전체표면상부에 유전체막(10)과 상부전극인 플레이트전극을 제3다결정실리콘막(11)으로 형성하고 후속공정으로 금속배선을 형성한다.Then, the third photoresist layer pattern 9 is removed, and the dielectric layer 10 and the plate electrode, which is the upper electrode, are formed on the entire surface of the third polycrystalline silicon layer 11 and metal wirings are formed in a subsequent process.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 셀부와 주변회로부의 단차를 완화시켜 후속공정을 용이하게 하고 콘택깊이를 낮게 형성하여 콘택공정시 유발되는 하부층의 손상을 방지하며 단차피복비가 나쁜 물질을 사용할 수 있도록 공정마진을 향상시킬 수 있어 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention may reduce the step between the cell part and the peripheral circuit part, thereby facilitating subsequent processes, and to form a low contact depth, thereby preventing damage to the lower layer caused during the contact process and providing a step coverage ratio. Process margins can be improved so that poor materials can be used, thereby improving the characteristics and reliability of semiconductor devices.
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