KR100307532B1 - Generating circuit of reference voltage - Google Patents

Abstract

The present invention relates to a reference voltage generator circuit. In the related art, when the threshold voltage of the PMOS transistor forming the first and second current paths of the pull-up unit is high, and the level of the power supply voltage is low, the PMOS transistor is completely conducting. As a result, the operation of the entire memory circuit is delayed as the level setting of the reference voltage is delayed. Accordingly, the present invention monitors the level rise of the power supply voltage, receives a power detection signal that transitions to a low potential when the power supply voltage reaches a constant level, and supplies a constant pull-up current through the first and second current paths. When the pull-up is completed at a constant level by the pull-up part that cuts off the current path and the pull-up current output from the pull-up part, a constant current is generated to block the second current path of the pull-up part through the output signal. In the conventional reference voltage generation circuit comprising an output unit for receiving the output signal of the constant current generating unit and the output signal of a constant level, when the power detection signal is input at high potential, the first pull-up unit And providing a reference voltage generator circuit further comprising a morph transistor for directly supplying the power supply voltage level to the second current path, thereby checking the power supply at an initial state at which the power supply voltage level rises. As applied to the constant current generation unit directly to the pull-up current from the signal by minimizing the delay of the reference voltage level set period of time, there is an effect that it is possible to prevent the operation of the overall memory circuit delay.

Description

Reference voltage generating circuit {GENERATING CIRCUIT OF REFERENCE VOLTAGE}

The present invention relates to a reference voltage generator circuit, and more particularly, to a reference voltage generator circuit suitable for minimizing the time that the level of the reference voltage applied to the internal voltage of the memory circuit rises.

In general, the internal voltage of the memory circuit is generated by the signal PUPB which detects when the power supply voltage VDD rises from 0V to a constant level (for example, 3.3V) and transitions from about 1.6 to 1.8V. It is made using the reference voltage VBDREF. The conventional reference voltage generating circuit will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a conventional reference voltage generating circuit. As shown in FIG. 1, when the power supply voltage VDD is monitored and the level rises, the power supply detection signal PUPB transitions to a low potential. A pull-up unit 10 for supplying a constant pull-up current through the first and second current paths and then cutting off the first current paths; When the pull-up is completed at a predetermined level by the pull-up current output from the pull-up unit 10, the constant current generator 20 blocks the second current path of the pull-up unit 10 through an output signal. Wow; The output unit 30 receives the output signal of the constant current generating unit 20 and outputs a reference level VBDREF of a predetermined level, and reference numeral '40' in the drawing denotes the constant current generating unit 20 and Each signal of the output unit 30 is grounded through the bipolar transistors Q1 to Q3, thereby preventing the ripple of the signals.

At this time, the pull-up unit 10 includes first to third inverter units 11 to 13 which sequentially invert the power detection signal PUPB; A source is connected to the power supply voltage VDD, a PMOS transistor PM1 whose gate is grounded VSS, a source is connected to the drain of the PMOS transistor PM1, and a gate is connected to the current path control unit 14. A PMOS transistor (PM2) which is controlled to be conductive; Each source is commonly connected to the drain of the PMOS transistor PM2, each drain is commonly connected to the constant current generator 20, and a gate is connected to the output of the third inverter unit 13 A PMOS transistor (PM3) for forming one current path and a PMOS transistor (PM4) connected to the current path control unit (14) to form a second current path; A gate is connected to the source connection point of the PMOS transistors PM3 and PM4, a source is connected to the current path controller 14, a drain is grounded (VSS), and a well-capacitor (WELL-CAP1) between the source and the drain. ) Is formed PMOS transistor (PM5); A source is connected to a power supply voltage VDD, a drain is connected to a source connection point of the PMOS transistors PM3 and PM4, and an output of the second inverter unit 12 is input to a gate to control conduction. PM6).

Here, the first to third inverter parts 11 to 13 detect the power at a common gate connection point of a PMOS and NMOS transistor connected in series between a power supply voltage VDD and a ground VSS as is commonly known. The signal PUPB and the outputs of the preceding inverter units 11 and 12 are respectively input, and the next stage inverter units 12 and 13 and the PMOS transistor PM3 are connected from the common drain connection point of the PMOS and NMOS transistors. The current path control unit 14 is configured to output a signal inverted to a gate, and the current path control unit 14 is connected to a power supply voltage VDD so that the gate receives a first output signal fed back from the constant current generating unit 20. Controlled PMOS transistor (PM7); A source is connected to the drain of the PMOS transistor PM7, and the drain is connected to the gates of the PMOS transistors PM2 and PM4 and the source of the PMOS transistor PM5 to be fed back from the constant current generator 20. The second output signal is applied to the gate, and is configured as a PMOS transistor PM8 that is electrically controlled.

The constant current generator 20 includes PMOS transistors PM9 and PM10 each having a source connected to a power supply voltage VDD and a gate connected to each other to output a first output signal from the connection point; A source is connected to the drains of the PMOS transistors PM9 and PM10, respectively, and the gates are connected to each other to output a second output signal from the connection point, and the drain is the first and second currents of the pull-up part 10. A PMOS transistor PM12 and a drain connected to a path are connected to gate connection points of the PMOS transistors PM9 and PM10; The gates are connected to each other and grounded through the well-capacitor WELL-CAP2. The drains are connected to their gates and connected to the drains of the PMOS transistor PM11, and the source is bipolar of the ripple prevention part 40. The nMOS transistor NM1 and the drain connected to the transistor Q1 are connected to the drain of the PMOS transistor PM11 through a resistor R1 and to the gate connection points of the PMOS transistors PM11 and PM12. The source is composed of an NMOS transistor NM2 connected to the bipolar transistor Q2 of the ripple prevention part 40 through a resistor R2.

The output unit 30 includes a PMOS transistor PM13 having a source connected to a power supply voltage VDD and receiving a first output signal of the constant current generator 20 into a gate thereof; A source is connected to the drain of the PMOS transistor PM13, the drain is connected to the bipolar transistor Q3 of the ripple prevention part 40 through the resistor R3, and the gate of the constant current generator 20 And a reference voltage VBDREF through the resistor R3 and the well-capacitor WELL-CAP3 having one side grounded.

Hereinafter, the operation of the conventional reference voltage generating circuit as described above will be described in detail with reference to the simulation graph of FIG.

First, in the initial state in which the power supply voltage VDD level rises, the power detection signal PUPB level rises in the same manner as the power supply voltage VDD, so that the first to third inverter parts 11 to 13 are driven at high potential. In this case, the first and second output signals of the constant current generator 20 have a level difference between a power supply voltage VDD level and a threshold voltage Vt or less and is similar to the power supply voltage VDD. Since the slope rises, the PMOS transistors PM7 and PM8 of the current path control unit 14 are blocked.

Accordingly, the third inverter unit 13 outputs a 'low potential' to conduct the first current path of the PMOS transistor PM3, while the well-capacitor WELL-CAP1 is not initially charged, As the first node slowly rises from the ground (VSS) level to the power supply voltage (VDD) level, the PMOS transistors PM2 and PM4 are initially conducted to form a second current path, and the PMOS transistors PM1, Charges the current by the power supply voltage VDD to the second node through PM2), and supplies the charged current to the constant current generator 20 through the first and second current paths to pull-up the third node. Let's do it.

In this state, when the third node is pulled up to a constant voltage (about 1.4 V), the first and second output signal levels of the constant current generator 20 configured as the current mirror are at the power supply voltage VDD level. And a level difference equal to or greater than the threshold voltage Vt, so that the PMOS transistors PM7 and PM8 of the current path control unit 14 become conductive.

Accordingly, the first node is set to the power supply voltage VDD level so that the second current path of the PMOS transistor PM4 is blocked, and at this time, since the power detection signal PUPB transitions to a low potential, the third inverter part 13 'High potential' is outputted to block the first current path of the PMOS transistor PM3, and 'low potential' is output from the second inverter unit 12 so that the PMOS transistor PM6 is conducted. Since the second node is set to the power supply voltage (VDD) level to block the PMOS transistor PM5, the well-capacitor WELL-CAP1 is charged to the power supply voltage (VDD) level to maintain the blocking state of the second current path. Let's do it.

In this case, since the first and second output signals of the constant current generator 20 to block the second current path of the pull-up unit 10 are applied to the gates of the PMOS transistors PM13 and PM14 of the output unit 30. The reference voltage VBDREF is output from the output unit 30.

However, in the conventional reference voltage generator circuit as described above, the first node is set to the power supply voltage level by the first and second output signals fed back from the constant current generator pulled up to a constant level, so that the PMOS transistor PM2 is blocked. The pull-up current is supplied to the constant current generator through the first and second current paths until the threshold voltage of the PMOS transistors PM2 and PM4 is high and the level of the power supply voltage is low. Since PM4) is not completely conducted, the operation of the entire memory circuit is delayed as the level setting of the reference voltage is delayed.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a reference voltage generating circuit that can minimize the time that the level of the reference voltage applied to the internal voltage of the memory circuit increases. It is.

1 is an exemplary view showing a conventional reference voltage generation circuit.

2 is a simulation graph of FIG.

Figure 3 is an exemplary view showing an embodiment of the present invention.

4 is a simulation graph of FIG.

*** Description of the symbols for the main parts of the drawings ***

10: pull-up part 11-13: 1st-3rd inverter part

14: current path control unit 20: constant current generating unit

30: output part 40: ripple prevention part

The reference voltage generating circuit for achieving the object of the present invention as described above monitors the level rise of the power supply voltage and receives a power detection signal that transitions to a low potential when the power supply voltage reaches a constant level to receive the first and second current paths. When the pull-up is completed at a constant level by the pull-up unit for supplying a constant pull-up current through the first current path and the pull-up current output from the pull-up unit, In the conventional reference voltage generating circuit comprising a constant current generating section for blocking the second current path of the up section and an output section for receiving the output signal of the constant current generating section and outputting a reference level of a constant level, the power detection signal is high When input upward, the transistor further comprises a morph transistor for directly supplying the power supply voltage level to the first and second current path of the pull-up portion.

Referring to the drawings with reference to the reference voltage generating circuit according to the present invention as described above in detail as follows.

FIG. 3 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, a source is connected to a power supply voltage VDD and a drain is connected to a second node and applied to a gate. It further comprises a PMOS transistor (PM100) which is conductively controlled by the output of the first inverter unit (11).

Hereinafter, the operation of the reference voltage generating circuit according to an embodiment of the present invention as described above will be described in detail with reference to the simulation graph of FIG.

Most operations of the present invention are performed in the same manner as in the related art, but in the initial state in which the power supply voltage VDD level rises, the power detection signal PUPB level rises equal to the power supply voltage VDD so as to be set to 'high potential'. When the first to third inverters 11 to 13 are applied, the second transistor is set to the power supply voltage VDD level by conducting the PMOS transistor PM100, so that the ' The pull-up current is supplied directly to the constant current generator 20 through the first current path of the PMOS transistor PM3 conducted by the low potential 'output.

Therefore, it is possible to minimize the time that the constant current generator 20 is pulled up.

In the operation of the present invention as described above, the pull-up of the third node is completed at the time when the power detection signal PUPB transitions to the low potential in the simulation graph of FIG. 4, and thus the reference voltage VBDREF level is finally set. It can be seen that the time is faster than the conventional FIG.

As described above, the reference voltage generation circuit according to the present invention minimizes the delay of the reference voltage level setting time by directly applying the pull-up current of the power detection signal to the constant current generator in the initial state at which the power supply voltage level rises. There is an effect that the operation of the memory circuit can be prevented from being delayed.

Claims (2)

When the power supply voltage reaches a certain level by monitoring the power supply voltage level increase, the power supply detects a low-potential power supply signal, supplies a constant pull-up current through the first and second current paths, and then cuts off the first current path. When the pull-up is completed at a predetermined level by the pull-up unit and the pull-up current output from the pull-up unit, the constant current generator and the constant current generation block the second current path of the pull-up unit through an output signal. In the conventional reference voltage generator circuit configured to receive a negative output signal and output a reference voltage of a constant level, when the power detection signal is input at high potential, the first and second current path of the pull-up part And a morph transistor for directly supplying a power supply voltage level to the reference voltage generation circuit. 2. The apparatus of claim 1, wherein the pull-up unit comprises: first to third inverter units 11 to 13 which sequentially invert the power detection signal PUPB; A source is connected to the power supply voltage VDD, a PMOS transistor PM1 whose gate is grounded VSS, a source is connected to the drain of the PMOS transistor PM1, and a gate is connected to the current path control unit 14. A PMOS transistor (PM2) which is controlled to be conductive; Each source is commonly connected to the drain of the PMOS transistor PM2, each drain is commonly connected to the constant current generator 20, and a gate is connected to the output of the third inverter unit 13 A PMOS transistor (PM3) for forming one current path and a PMOS transistor (PM4) connected to the current path control unit (14) to form a second current path; A gate is connected to the source connection point of the PMOS transistors PM3 and PM4, a source is connected to the current path controller 14, a drain is grounded (VSS), and a well-capacitor (WELL-CAP1) between the source and the drain. ) Is formed PMOS transistor (PM5); A source is connected to a power supply voltage VDD, a drain is connected to a source connection point of the PMOS transistors PM3 and PM4, and an output of the second inverter unit 12 is input to a gate to control conduction. PM6) and a source are connected to a power supply voltage VDD, and a drain is connected to the drain of the PMOS transistor PM6, and the PMOS transistor is electrically controlled by receiving the output of the first inverter unit 11 at the gate. And a reference voltage generating circuit (PM100).