KR100307488B1 - Method for forming contact hole of semiconductor - Google Patents
Method for forming contact hole of semiconductor Download PDFInfo
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- KR100307488B1 KR100307488B1 KR1019980055798A KR19980055798A KR100307488B1 KR 100307488 B1 KR100307488 B1 KR 100307488B1 KR 1019980055798 A KR1019980055798 A KR 1019980055798A KR 19980055798 A KR19980055798 A KR 19980055798A KR 100307488 B1 KR100307488 B1 KR 100307488B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 배선과 콘택 홀을 동시에 형성함으로써, 배선과 콘택 홀 사이의 오버레이 문제를 개선할 수 있도록 한 반도체 디바이스의 콘택 홀 형성 방법에 관한 것으로, 이를 위하여 본 발명은, 콘택 홀을 먼저 형성하고 금속 배선을 나중에 형성하는 전술한 종래 방법과는 달리, 한 번의 마스크 공정에서 금속 배선과 콘택 홀을 동시에 형성하고, 후속 공정에서 콘택 홀 부분을 오픈시킨다. 따라서, 본 발명은 금속 배선과 콘택 홀 사이의 오버레이 마진을 향상시키고, 또한 콘택 홀의 한정 능력을 증진시킬 수 있다.The present invention relates to a method for forming a contact hole in a semiconductor device, by forming a wiring and a contact hole at the same time, thereby improving the overlay problem between the wiring and the contact hole. Unlike the aforementioned conventional method of forming the wiring later, the metal wiring and the contact hole are simultaneously formed in one mask process, and the contact hole portion is opened in a subsequent process. Therefore, the present invention can improve the overlay margin between the metal wiring and the contact hole, and also enhance the limiting ability of the contact hole.
또한, 본 발명은, 콘택 홀 및 금속 배선 형성 시에 고가의 크리티칼 장비를 2개 사용하는 종래 방법과는 달리, 단지 콘택 홀 형성 시에 저가의 넌크리티칼 장비 하나만을 사용하기 때문에 반도체 디바이스의 제조 원가가 상승하는 것을 효과적으로 억제할 수 있는 것이다.In addition, unlike the conventional method in which two expensive critical equipments are used to form contact holes and metal wirings, the present invention uses only one low-cost non-critical equipment to form contact holes. The rise in manufacturing costs can be effectively suppressed.
Description
본 발명은 반도체 디바이스의 콘택 홀을 형성하는 방법에 관한 것으로, 더욱 상세하게는 고집적도와 고신뢰도를 요구하는 반도체 디바이스에서 콘택 홀을 형성하는 데 적합한 콘택 홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming contact holes in a semiconductor device, and more particularly, to a method for forming contact holes in a semiconductor device requiring high integration and high reliability.
최근 들어, 반도체 디바이스가 대용량화 및 고집적화됨에 따라 반도체 디바이스내의 금속 배선의 선폭 또한 점차 감소되고 있으며, 셀 면적의 축소에 따른 콘택 홀 면적의 축소 또한 필수적이다.In recent years, as the semiconductor devices have increased in capacity and density, the line widths of the metal wirings in the semiconductor devices are also gradually reduced, and the contact hole area is reduced due to the reduction in the cell area.
도 2는 종래 방법에 따라 반도체 디바이스의 콘택 홀을 형성하는 과정을 도시한 공정 순서도이다.2 is a process flowchart illustrating a process of forming contact holes of a semiconductor device according to a conventional method.
도 2a를 참조하면, 포토 리소그라피 공정 및 식각 공정을 수행하여 도시 생략된 실리콘 기판 상에 형성된 절연막(200)상에 콘택홀(T), 즉 실리콘 기판과 금속 배선간을 전기적으로 연결하는 콘택 홀(T)을 형성한다.Referring to FIG. 2A, a contact hole T, that is, a contact hole for electrically connecting a silicon substrate and a metal wire on an insulating layer 200 formed on a silicon substrate (not shown) by performing a photolithography process and an etching process ( Form T).
이어서, 도 2b에 도시된 바와 같이, 스핀 코팅을 통해 절연막(200)의 상부 전면에 걸쳐 콘택 홀(T)이 매립되는 형태로 아크막(ARC막 : 202)을 형성시키고, 다시 리소그라피 공정을 수행하여 소정 패턴(즉, 콘택 홀 주위의 포토 레지스트가 제거된 패턴)을 갖는 마스크 패턴(204)을 형성한다.Subsequently, as shown in FIG. 2B, an arc film (ARC film) 202 is formed in a form in which the contact hole T is buried over the entire upper surface of the insulating film 200 through spin coating, and again, a lithography process is performed. To form a mask pattern 204 having a predetermined pattern (ie, a pattern in which the photoresist around the contact hole is removed).
다음에, 마스크 패턴(204)을 마스크로 하는 식각 공정을 수행하여 콘택 홀 주위의 절연막 일부를 설정된 깊이까지 제거한 다음, 마스크 패턴(204)과 잔존하는 아크막(202)을 순차 제거함으로써, 배선용 콘택 홀(T')을 형성한다(도 2c).Next, an etching process using the mask pattern 204 as a mask is performed to remove a portion of the insulating film around the contact hole to a predetermined depth, and then the mask pattern 204 and the remaining arc film 202 are sequentially removed to thereby form a wiring contact. A hole T 'is formed (FIG. 2C).
또한, 도 2d에 도시된 바와 같이, 배선용 콘택 홀(T')이 형성된 절연막(200)의 상부 전면에 걸쳐 스퍼터링 등과 같은 공정을 수행하여 배선용 콘택 홀(T')이 충분하게 매립되도록 금속 배선 물질(206)을 형성시킨다.In addition, as shown in FIG. 2D, a metal wiring material is formed to sufficiently fill the wiring contact hole T 'by performing a process such as sputtering over the entire upper surface of the insulating film 200 on which the wiring contact hole T' is formed. 206 is formed.
그런 다음, 절연막(200)을 종말점으로 하는 화학적/기계적 연마(CMP) 공정을 수행하여 절연막(200)의 상부에 형성된 금속 배선 물질을 제거함으로써, 도 2e에 도시된 바와 같이, 절연막(200)내에 금속 배선 및 콘택 홀(208)을 형성, 즉 금속배선(a)과 콘택 홀(b)로 된 금속 배선 및 콘택 홀(208)을 형성한다.Then, by performing a chemical / mechanical polishing (CMP) process having the insulating film 200 as an end point to remove the metal wiring material formed on the insulating film 200, as shown in Figure 2e, the insulating film 200 Metal wires and contact holes 208 are formed, that is, metal wires and contact holes 208 formed of metal wires a and contact holes b are formed.
즉, 상술한 바와 같은 종래 방법에서는 콘택 홀을 먼저 형성한 다음 후속 공정을 통해 금속 배선을 형성하고 있다.That is, in the conventional method as described above, the contact hole is first formed and then the metal wiring is formed through the subsequent process.
그러나, 상술한 바와 같은 종래 방법의 경우 반도체 디바이스가 고집적화(즉, 금속 배선 폭의 감소 등)되어감에 따라 다음과 같은 문제점들이 노출되고 있다.However, in the conventional method as described above, the following problems are exposed as semiconductor devices are highly integrated (i.e., reduction of metal wiring width, etc.).
즉, 콘택 홀과 배선 사이의 오버레이 마진이 부족하고, 또한 디지인 룰이 작아지면서 포토 마스크 공정 시에 콘택 홀을 한정(define)하기가 어렵게 되는 등의 문제가 야기되고 있다.In other words, there is a problem that the overlay margin between the contact hole and the wiring is insufficient, and the design rule becomes smaller, which makes it difficult to define the contact hole during the photo mask process.
따라서, 종래에는 콘택 홀을 형성하는 데 고가의 크리티칼 장비(critical M/C)를 사용하고, 또한 배선 홀을 형성하는 데도 마찬가지로 고가의 크리티칼 장비를 사용하고 있다.Therefore, conventionally, expensive critical equipment (critical M / C) is used to form contact holes, and expensive critical equipment is similarly used to form wiring holes.
그러나, 콘택 홀 및 금속 배선을 형성하는 데 고가의 크리티칼 장비를 사용하더라도 오버레이 마진 부족 및 콘택 홀 한정 곤란 등의 문제는 여전히 잔존하며, 오히려 고가의 장비 사용으로 인해 반도체 디바이스의 제조 원가만이 상승되는 결과가 초래되고 있다.However, even if expensive critical equipment is used to form contact holes and metal wiring, problems such as lack of overlay margin and difficulty in defining contact holes still remain. Rather, the use of expensive equipment only increases the manufacturing cost of semiconductor devices. Results are incurred.
본 발명은 종래 기술의 문제점을 해결하기 위한 것으로, 한 공정에서 금속 배선과 콘택 홀을 동시에 형성함으로써, 오버레이 마진을 향상시키고, 또한 콘택 홀의 한정 능력을 증진시킬 수 있는 반도체 디바이스의 콘택 홀 형성 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention is to solve the problems of the prior art, and by forming a metal wiring and a contact hole at the same time, a method for forming a contact hole in a semiconductor device that can improve the overlay margin and also improve the limiting ability of the contact hole The purpose is to provide.
상기 목적을 달성하기 위하여 본 발명은, 반도체 디바이스에 형성된 두 층 간의 막을 전기적으로 연결시키는 콘택 홀을 형성하는 방법에 있어서, 콘택 홀을 형성하고자하는 절연막 상에 후속 공정에서 콘택 홀이 형성될 콘택 홀 예정 영역을 둘러싸는 금속 배선 예정 영역을 패터닝하는 제 1 과정; 상기 패터닝된 상부 전면에 걸쳐 아크막 및 포토 레지스트를 코팅한 후 마스크 패턴을 형성하는 제 2 과정; 식각 공정을 순차 수행하여 상기 아크막의 일부 및 상기 콘택 홀 예정 영역의 절연막을 제거함으로써, 상기 금속 배선 예정 영역 내에 콘택 홀 공간을 형성하는 제 3 과정; 상기 마스크 패턴과 상기 절연막 상에 잔류하는 아크막을 제거함으로써, 금속 배선 및 콘택 홀 공간을 형성하는 제 4 과정; 및 상기 형성된 금속 배선 및 콘택 홀 공간에 금속 배선 물질을 매립시킴으로써 금속 배선 및 콘택 홀을 형성하는 제 5 과정으로 이루어진 반도체 디바이스의 콘택 홀 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a method for forming a contact hole for electrically connecting a film between two layers formed in a semiconductor device, the contact hole in which the contact hole is to be formed in a subsequent process on the insulating film to be formed A first process of patterning a metal wiring scheduled area surrounding the predetermined area; A second process of forming a mask pattern after coating an arc film and a photoresist over the patterned upper entire surface; A third step of forming a contact hole space in the metal wiring planning region by sequentially performing an etching process to remove a portion of the arc film and the insulating film of the contact hole planning region; A fourth step of forming a metal wiring and a contact hole space by removing the arc pattern remaining on the mask pattern and the insulating film; And a fifth process of forming a metal wiring and a contact hole by embedding a metal wiring material in the formed metal wiring and contact hole space.
도 1은 본 발명의 바람직한 실시 예에 따라 반도체 디바이스의 콘택 홀을 형성하는 과정을 도시한 공정 순서도,1 is a process flowchart illustrating a process of forming a contact hole in a semiconductor device according to a preferred embodiment of the present invention;
도 2는 종래 방법에 따라 반도체 디바이스의 콘택 홀을 형성하는 과정을 도시한 공정 순서도.2 is a process flowchart showing a process of forming contact holes in a semiconductor device according to a conventional method.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 절연막 102,106 : 마스크 패턴100: insulating film 102,106: mask pattern
104 : 아크막 108 : 금속 배선 물질104: arc film 108: metal wiring material
110 : 금속 배선 및 콘택 홀110: metal wiring and contact hole
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시 예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 본 발명의 가장 큰 기술적인 특징은, 콘택 홀을 형성한 다음에 금속 배선을 형성하는 전술한 종래 방법과는 달리, 한 번의 마스크 공정에서 금속 배선과 콘택 홀을 동시에 형성한다는 데 있는 것으로, 이러한 공정을 통해 본 발명에서 목적으로 하는 바를 쉽게 달성할 수 있다.First, the biggest technical feature of the present invention is that, unlike the above-described conventional method of forming contact holes and then forming metal wires, the metal wires and contact holes are simultaneously formed in one mask process. Through this process it is easy to achieve the purpose of the present invention.
도 1은 본 발명의 바람직한 실시 예에 따라 반도체 디바이스의 콘택 홀을 형성하는 과정을 도시한 공정 순서도이다.1 is a process flowchart illustrating a process of forming a contact hole in a semiconductor device according to a preferred embodiment of the present invention.
도 1a를 참조하면, 포토 리소그라피 공정을 수행하여 도시 생략된 실리콘 기판 상에 형성된 절연막(100)상에 후속하는 공정을 통해 형성하고자하는 콘택 홀 부분(즉, 콘택 홀 예정 영역)을 제외한 금속 배선 부분(즉, 금속 배선 예정 영역)을 형성하기 위한 패턴을 갖는 마스크 패턴(102)을 형성한다.Referring to FIG. 1A, a metal wiring portion except for a contact hole portion (that is, a contact hole region) to be formed through a photolithography process and a subsequent process on an insulating film 100 formed on a silicon substrate (not shown). A mask pattern 102 having a pattern for forming (that is, a metal wiring scheduled region) is formed.
이어서, 마스크 패턴(102)을 마스크로 하는 식각 공정을 수행하여 절연막의 일부를 제거하고, 스트립 공정을 통해 절연막(100)상의 마스크 패턴(102)을 제거함으로써, 절연막(100)내에 금속 배선 예정 영역(A)을 형성한다(도 1b). 이때, 금속 배선 예정 영역(A)에 둘러싸인 영역(B)은 후속하는 공정을 통해 콘택 홀이 형성될 예정 영역이다. 즉, 본 발명에서는 한 번의 마스크 공정을 통해 금속 배선 예정 영역(A)과 콘택 홀 예정 영역(B)을 동시에 형성한다.Subsequently, an etching process using the mask pattern 102 as a mask is performed to remove a portion of the insulating film, and the mask pattern 102 on the insulating film 100 is removed through a stripping process, thereby forming the metal wiring predetermined region in the insulating film 100. (A) is formed (FIG. 1B). At this time, the area B surrounded by the metal wiring plan area A is a plan area in which a contact hole is to be formed through a subsequent process. That is, in the present invention, the metal wiring planning area A and the contact hole planning area B are simultaneously formed through one mask process.
다음에, 도 1c에 도시된 바와 같이, 스핀 코팅을 통해 절연막(100)의 상부 전면에 걸쳐 금속 배선 예정 영역(A)이 매립되는 형태로 아크막(104)을 형성하고, 다시 리소그라피 공정을 수행하여 아크막(104)의 상부에 소정 패턴(즉, 후에 형성될 콘택 홀 예정 영역 주위의 포토 레지스트가 제거된 패턴)을 갖는 마스크 패턴(106)을 형성한다.Next, as shown in FIG. 1C, the arc film 104 is formed in a form in which the metal wiring predetermined region A is buried over the entire upper surface of the insulating film 100 through spin coating, and again, a lithography process is performed. Thus, a mask pattern 106 is formed on the arc film 104 with a predetermined pattern (ie, a pattern in which photoresist around the contact hole predetermined region to be formed later is removed).
또한, 마스크 패턴(106)을 마스크로 하는 식각 공정을 수행하여 콘택 홀 예정 영역 주위의 아크막(104) 일부를 설정된 깊이까지 제거한 다음, 도 1d에 도시된 바와 같이, 후속 공정에서 콘택 홀로 형성될 부분의 절연막 상부(100a)를 노출시킨다.Further, an etching process using the mask pattern 106 as a mask is performed to remove a portion of the arc film 104 around the predetermined area of the contact hole to a predetermined depth, and then, as shown in FIG. 1D, to be formed as a contact hole in a subsequent process. The insulating film upper portion 100a of the portion is exposed.
그런 다음, 포토 리소그라피 공정 및 건식 식각 공정을 수행하여 노출된 절연막 상부(100a) 부분의 절연막을 제거함으로써, 금속 배선 영역 내에 콘택 홀 공간(T)을 형성하며(도 1e), 이어서 마스크 패턴(106)과 잔존하는 아크막(104)을 순차 제거함으로써, 도 1f에 도시된 바와 같이, 금속 배선 및 콘택 홀 공간(T')을 형성한다.Then, the photolithography process and the dry etching process are performed to remove the exposed insulating film of the portion of the upper insulating film 100a, thereby forming the contact hole space T in the metal wiring region (FIG. 1E), and then the mask pattern 106 ) And the remaining arc film 104 are sequentially removed to form a metal wiring and a contact hole space T ', as shown in FIG. 1F.
이때, 콘택 홀 공간의 형성에 사용되는 노광 장비로서는, 종래 방법에서 사용하는 고가의 크리티칼 장비가 아닌, 저가의 넌크리티칼 장비를 사용, 즉 콘택 홀 예정 영역 부위의 마스크를 정렬할 때 오버레이 마진이 없기 때문에 저가의 넌크리티칼 장비를 사용할 수 있다.At this time, as exposure equipment used to form the contact hole space, using an inexpensive non-critical device, not the expensive critical equipment used in the conventional method, that is, overlay margin when aligning the mask in the area of the contact hole planned area. Because of this, low cost non-critical equipment can be used.
또한, 도 1g에 도시된 바와 같이, 금속 배선 및 콘택 홀 공간(T')이 형성된 절연막(100)의 상부 전면에 걸쳐 스퍼터링 등과 같은 공정을 수행하여 금속 배선 및 콘택 홀 공간(T')이 충분하게 매립되도록 금속 배선 물질(108)을 형성시킨다.In addition, as shown in FIG. 1G, a process such as sputtering is performed over the entire upper surface of the insulating film 100 on which the metal wiring and the contact hole space T 'are formed, so that the metal wiring and the contact hole space T' are sufficient. Metal wiring material 108 is formed to be buried.
그런 다음, 절연막(100)을 종말점으로 하는 화학적/기계적 연마(CMP) 공정을 수행하여 절연막(100)의 상부에 형성된 금속 배선 물질을 선택적으로 제거함으로써, 도 1h에 도시된 바와 같이, 절연막(100)내에 금속 배선 및 콘택 홀(110)을 형성, 즉 금속 배선(a)과 콘택 홀(b)로 된 금속 배선 및 콘택 홀(110)을 형성한다.Then, by performing a chemical / mechanical polishing (CMP) process having the insulating film 100 as an end point, selectively removing the metal wiring material formed on the insulating film 100, as shown in Figure 1h, the insulating film 100 The metal wirings and the contact holes 110 are formed in the metal wires, that is, the metal wires and the contact holes 110 formed of the metal wires a and the contact holes b are formed.
이상 설명한 바와 같이 본 발명에 따르면, 콘택 홀을 먼저 형성하고 금속 배선을 나중에 형성하는 전술한 종래 방법과는 달리, 한 번의 마스크 공정에서 금속 배선과 콘택 홀을 동시에 형성함으로써, 오버레이 마진을 향상시키고, 또한 콘택홀의 한정 능력을 증진시킬 수 있다.As described above, according to the present invention, unlike the above-described conventional method of forming the contact hole first and forming the metal wiring later, the overlay margin is improved by simultaneously forming the metal wiring and the contact hole in one mask process, In addition, it is possible to increase the limiting ability of contact holes.
또한, 종래 방법에서 콘택 홀 및 금속 배선 형성 시에 고가의 크리티칼 장비를 2개 사용하였으나, 본 발명에서는 단지 콘택 홀 노출, 노광 시에 저가의 넌크리티칼 장비 하나만을 사용하기 때문에 반도체 디바이스의 제조 원가가 상승하는 것을 효과적으로 억제할 수 있다.In addition, in the conventional method, two expensive critical equipments are used to form contact holes and metal wirings, but in the present invention, only one low-cost non-critical equipment is used to expose and expose contact holes. The rising cost can be effectively suppressed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980055798A KR100307488B1 (en) | 1998-12-17 | 1998-12-17 | Method for forming contact hole of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980055798A KR100307488B1 (en) | 1998-12-17 | 1998-12-17 | Method for forming contact hole of semiconductor |
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| KR100307488B1 true KR100307488B1 (en) | 2001-11-02 |
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| KR1019980055798A Expired - Fee Related KR100307488B1 (en) | 1998-12-17 | 1998-12-17 | Method for forming contact hole of semiconductor |
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