KR100303443B1 - Thin film transistor substrate for liquid crystal display and a manufacturing method thereof - Google Patents

Abstract

In manufacturing a thin film transistor substrate for a liquid crystal display device, a base layer made of an aluminum alloy or aluminum, a buffer layer made of a heat resistant metal such as molybdenum or titanium, and a stable layer made of a material resistant to corrosion such as ITO are sequentially stacked on an insulating substrate. And patterning at the same time to form gate wirings such as gate electrodes and gate pads. The gate insulating film, the amorphous silicon layer, the doped amorphous silicon layer, and the data metal are sequentially stacked and patterned on top of each other to form a data wiring, and the ITO is stacked and patterned to form an auxiliary layer and a pixel electrode. The exposed data metal and the doped amorphous silicon layer beneath it are etched and separated on both sides, and a protective film is laminated and patterned to form pad contact holes. In this way, the base layer, which is vulnerable to corrosion, is not covered and exposed to the stable layer, thereby ensuring the reliability of the gate pad.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND A MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to a thin film transistor substrate manufactured using a four-sheet mask and a method for manufacturing the same.

A thin film transistor substrate for a conventional liquid crystal display device will now be described with reference to the drawings.

1A, 1B, and 1C are cross-sectional views of a thin film transistor unit, a gate pad unit, and a data pad unit of a thin film transistor substrate for a liquid crystal display device according to the related art, respectively.

Gate wirings, such as the gate pad 23 and the gate electrode 21, are formed on the transparent insulating substrate 1, and the gate insulating film 3 is laminated on the gate wiring. An amorphous silicon pattern 4 is formed on the gate insulating layer 3, and a contact layer 5 made of doped amorphous silicon is separated on both sides of the amorphous silicon pattern 4 around the gate electrode 21. Formed. The data line 6 connected to the source electrode 61, the drain electrode 62, and the source electrode 61 is formed on the contact layer 5, and the data pad 63 is formed at the beginning of the data line 6. ) Is formed. Auxiliary patterns 71, 72, 73, and 7 made of indium tin oxide (ITO) are formed on the data pad 63, the source electrode 61, the drain electrode 62, and the data line 6. The electrode auxiliary pattern 62 extends to form the pixel electrode 74. A passivation layer 8 is stacked on the auxiliary patterns 71, 72, 73, and 7 and the pixel electrode 74, and the passivation layer 8 contacts the gate pad 23 to expose the data pad auxiliary pattern 73. Spheres 81 and 82 are formed.

There is a problem in the reliability of the gate pad 23 in the thin film transistor substrate for liquid crystal display devices manufactured using such four masks. Gate wiring is usually formed of aluminum alloy (Al-Nd) or aluminum, which is very susceptible to corrosion. However, in the gate pad 23, since the material is exposed to the outside, the electrical contactability of the pad 23 may be degraded due to corrosion. In fact, the pad reliability evaluation conducted at 120 ° C, 2 atm, and 100% humidity resulted in pads after 1 hour regardless of whether they were treated with Si or UV (ultraviolet) curing bonds during the module process. Moisture penetrated into (23) and corrosion progressed after 4 hours. In particular, the corrosion occurred badly at the contact portion between the gate pad 23 surface and the conduction ball, and some corrosion occurred even at the portion not in contact with the conduction hole. This is particularly corrosive at the contact portion with the conductive hole because the water present between the conductive sphere coated with nickel (Ni) and gold (Au) on the plastic sphere and the aluminum alloy acts as an electrolyte to cause an electrochemical reaction.

In addition, since the gate pad 23 exposed during the cleaning, such as after a rubbing process, may be corroded, the cleaning agent, such as an acid or an alkali, cannot be used. Cause badness.

The technical problem to be achieved by the present invention is to increase the reliability of the pad portion.

1A, 1B, and 1C are cross-sectional views of a thin film transistor unit, a gate pad unit, and a data pad unit of a thin film transistor substrate for a liquid crystal display device according to the related art, respectively.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3A, 3B, and 3C are cross-sectional views taken along lines IIIa-IIIa ', IIIb-IIIb', and IIIc-IIIc 'of FIG. 2, respectively.

4A, 4B, 4C to 6A, 6B, and 6C illustrate a procedure of manufacturing a thin film transistor substrate according to an embodiment of the present invention, wherein a, b, and c are IIIa-IIIa of FIG. It shows sectional drawing about a line, a IIIb-IIIb 'line, and a IIIc-IIIc' line.

In order to solve this technical problem, in the present invention, the gate wiring is formed by successively stacking three layers of a first gate layer made of an aluminum alloy, a second gate layer made of a heat resistant metal, and the like and a third gate layer made of ITO. do.

Specifically, a first gate layer made of aluminum or an aluminum alloy is formed on the insulating substrate, a second gate layer is formed on the first gate layer, and a third gate layer made of ITO is formed on the second gate layer. A gate insulating film having a contact hole for exposing the second gate layer, is stacked over the second gate layer, an amorphous silicon pattern is formed over the gate insulating film, a contact layer is formed over the amorphous silicon pattern, and the data The wiring is formed on the contact layer, the data auxiliary pattern is formed on the data wiring, the pixel electrode is connected to the data auxiliary pattern on the drain electrode, the data auxiliary pattern is formed on the pixel electrode, and the data on the data pad is formed. A contact that exposes the auxiliary pattern and the second gate layer over the gate pad A liquid crystal thin film transistor substrate for a display device including a protective film having a sphere.

Here, the second gate layer may be formed of any one of molybdenum, molybdenum alloy, titanium, titanium alloy, chromium, chromium alloy, tungsten, tungsten alloy, cobalt, cobalt alloy, thallium and thallium alloy.

Such a thin film transistor may be formed by sequentially stacking first, second and third gate layers, simultaneously patterning the first, second and third gate layers to form a gate wiring, a gate insulating layer, an amorphous silicon layer, and a doped layer. Stacking an amorphous silicon layer and a data metal in sequence, patterning the data metal, the doped amorphous silicon layer and the amorphous silicon layer to form an amorphous silicon pattern, a contact layer, a data wiring, and forming a data auxiliary pattern and a pixel electrode Etching the exposed data metal and the underlying contact layer without being covered by the data auxiliary pattern and the pixel electrode; laminating a protective film; depositing the protective film and the gate pad portion of the second gate layer and the data auxiliary on the gate insulating film And a contact hole for exposing the data pad portion of the pattern.

Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 3A, 3B, and 3C are lines IIIa-IIIa ', IIIb-IIIb', and IIIc-IIIc 'of FIG. 2, respectively. Sectional view of the line.

Stable made of a material resistant to corrosion such as base layers 211 and 231 made of aluminum or aluminum-neodymium alloy (Al-Nd), buffer layers 212 and 232 and ITO on a transparent insulating substrate 10 such as glass. A gate wiring including the gate electrode 210 (part of the gate line 20), the gate pad 230, and the gate line 20 formed by stacking the layers 213 and 233 in succession is formed. The buffer layers 212 and 232 are formed to prevent interfacial reaction between aluminum or aluminum alloy forming the base layers 211 and 231 and ITO forming the stable layers 213 and 233. Heat resistance such as molybdenum (Mo) or molybdenum alloy, titanium (Ti) or titanium alloy, chromium (Cr) or chromium alloy, tungsten (W) or tungsten alloy, cobalt (Co) or cobalt alloy, thallium (Ta) or thallium alloy Metals and their compounds are used.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is stacked on the gate wiring, and an amorphous silicon pattern 40 is formed on the gate insulating film 30. The amorphous silicon pattern 40 extends in the longitudinal direction, and branches out to form a thin film transistor. Contact layers 510 and 520 are formed on the amorphous silicon pattern 40, which are separated on both sides of the gate electrode 210 and made of amorphous silicon heavily doped with N-type impurities. A source electrode 610 and a drain electrode 620 made of chromium or the like are formed on the contact layers 510 and 520, and the source electrode 610 is connected to the data line 60 and the data line 60. At the beginning of the data pad 630 is formed. Auxiliary patterns 710, 720, 70, and 730 formed of ITO are formed on the source electrode 610, the drain electrode 620, the data line 60, and the data pad 630, and the drain electrode auxiliary pattern 720 is formed thereon. ) Extends to form the pixel electrode 740. A passivation layer 80 is formed on the auxiliary patterns 710, 720, 730, and 70 and the pixel electrode 740. The passivation layer 80 on the data pad 630 and the gate insulating layer on the gate pad 230 are formed. 30 and the contact holes 810 and 820 are formed in the passivation layer 80 to expose the gate pad stabilization layer 233 and the data pad auxiliary pattern 730.

In this case, the gate pad base layer 231 made of aluminum alloy or the like is not directly exposed to the outside, but is covered with a stable layer 233 made of ITO or the like, which is resistant to corrosion, thereby preventing poor contact due to corrosion. Since the cleaning agent may be used in the process, impurities may be easily removed to ensure the reliability of the gate pad 230.

Now, a method of manufacturing a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

4A, 4B, 4C to 6A, 6B, and 6C illustrate a procedure of manufacturing a thin film transistor substrate according to an embodiment of the present invention, wherein a, b, and c are IIIa-IIIa of FIG. It shows sectional drawing about a line, a IIIb-IIIb 'line, and a IIIc-IIIc' line.

First, as shown in FIGS. 4A, 4B, and 4C, a heat-resistant metal such as aluminum, an aluminum alloy, molybdenum, or titanium, a compound resistant to corrosion, such as ITO, and the like, are sequentially deposited on the insulating substrate 10, and the first substrate is deposited. Photolithography is performed using a mask to form a gate line including a gate line 20, a gate electrode 210, and a gate pad 230 formed of a three-layer film. At this time, etching is performed by dry etching to prevent undercut profile and CD skew instability and to prevent display defects due to staining.

Next, as illustrated in FIGS. 5A, 5B, and 5C, conductive materials such as the gate insulating layer 30, the amorphous silicon layer, the doped amorphous silicon layer, and chromium are sequentially deposited, and the photo is etched using a second mask. The pattern in which the electrode 610 and the drain electrode 620 are connected, the data line 60, the data pad 630, the contact layer 50 and the amorphous silicon pattern 40 below are simultaneously formed.

6A, 6B, and 6C, ITO is deposited and the auxiliary patterns 70, 710, 720, and 730 and the pixel electrode 740 are formed using a third mask.

Next, the exposed source electrode 610 and the drain electrode 620 are connected by using the auxiliary patterns 70, 710, 720, and 730 and the pixel electrode 740 or a photoresist film (not shown) thereon as an etch barrier. The pattern and the contact layer 50 at the bottom thereof are simultaneously etched and separated into both sides. Then, in the data line 60, the source and drain electrodes 610 and 620, the portion of the auxiliary pattern 70, 710, 720, and 730 and the pixel electrode 740 and the amorphous silicon layer 40 overlap with each other in FIG. 2. do. A protective film 80 is deposited thereon and contact holes 81 and 82 are formed using a fourth mask.

As described above, by forming the gate wiring in triple, the metal layer, which is vulnerable to corrosion, can be covered with a material resistant to corrosion such as ITO, thereby increasing the reliability of the gate pad.

Claims (4)

Insulation board, A first gate layer formed on the insulating substrate and made of aluminum or an aluminum alloy; A second gate layer formed on the first gate layer, A third gate layer formed on the second gate layer and made of ITO, A gate insulating layer stacked on the third gate layer and having a contact hole exposing the third gate layer; An amorphous silicon pattern formed on the gate insulating film, A contact layer formed on the amorphous silicon pattern, A data line formed on the contact layer, A data auxiliary pattern formed on the data line; A pixel electrode connected to the data auxiliary pattern, A passivation layer formed on the data auxiliary pattern and the pixel electrode and having a contact hole exposing the data auxiliary pattern on the data pad and the third gate layer on the gate pad; Including; The first to third gate layers may be formed by a single photolithography process. In claim 1, The second gate layer is formed of any one of molybdenum, molybdenum alloy, titanium, titanium alloy, chromium, chromium alloy, tungsten, tungsten alloy, cobalt, cobalt alloy, thallium and thallium alloy. The method of claim 1 or 2, And the data line and the contact layer are formed only at a portion where the amorphous silicon pattern and the pixel electrode overlap. Stacking the first, second and third gate layers in sequence, Simultaneously patterning the first, second, and third gate layers to form a gate wiring; Stacking the gate insulating film, the amorphous silicon layer, the doped amorphous silicon layer, and the data metal in sequence, Patterning the data metal, the doped amorphous silicon layer, and the amorphous silicon layer to form an amorphous silicon pattern, a contact layer, and a data wire; Forming a data auxiliary pattern and a pixel electrode, Etching the data metal and the contact layer below it, which are not covered by the data auxiliary pattern and the pixel electrode; Laminating a protective film, Forming a contact hole in the passivation layer and the gate insulating layer to expose a gate pad portion of the third gate layer and a data pad portion of the data auxiliary pattern Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a.