KR100303325B1 - Method for monitoring inter-processor communication module in switching system - Google Patents

Abstract

The present invention relates to a method for auditing an IPC module, and provides an IPC module audit method capable of securing IPC reliability. To this end, the present invention provides a CIN having a CIP, a CIP node and a CCS gateway, an OMP having an OMP gateway connected to the CCS gateway, and an OMP connected to the CIP by the TD bus and an OMP connected by the IS bus. A method of auditing an IPC module in a switching system having a CCPP and having an IPC module from a CIP to an CMP node and an OMP through a CCS gateway and an OMP gateway, wherein the OMP is in an IPC response to all MPs mounted on the CIN. MP status monitoring process for monitoring, CIP status monitoring process for OMP status monitoring with IPC response to CIP through the IPC path between CIP and OMP, and if the monitoring result for CIP is abnormal, OMP IPC module status monitoring process that obtains IPC module status monitoring information through the combination of MP status monitoring information obtained from MP status monitoring process and determines IPC module status, and IPC If it determined to be a fault in the module status monitoring process, indicating a fault on the line with the operator is provided with the IPC module status recovery process.

Description

Audit method for inter-processor communication module in exchange system {METHOD FOR MONITORING INTER-PROCESSOR COMMUNICATION MODULE IN SWITCHING SYSTEM}

The present invention relates to an exchange system, and more particularly to a method for auditing an interprocessor communication module.

In an exchange system, it is important to secure inter-processor communication, that is, IPC (Inter-Processor Communication) reliability. This requires an audit of IPC modules ranging from Control Interworking Processor (CIP), an IPC-only processor, to Operation & Maintenance Processor (OMP), a processor whose main function is maintenance. CIP is a processor that controls the CIN (Control Interworking Node), a dedicated network for IPC.

As described above, the exchange system requires an audit of the IPC module to secure IPC reliability.

Accordingly, an object of the present invention is to provide an IPC module audit method capable of securing IPC reliability.

1 is a block diagram showing the relevant part including the IPC module in the exchange system,

2 is an IPC module state audit flowchart according to an embodiment of the present invention;

3 is an IPC module state audit control procedure according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. While many specific details are set forth in the following description and in the accompanying drawings, such as specific processor names, to provide a more general understanding of the invention, these specific details are illustrated for purposes of explanation of the invention, meaning that the invention is limited thereto. It is not. It should also be noted that the same elements in the figures represent the same signs wherever possible. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

FIG. 1 is a block diagram showing a relevant part including an IPC module in an exchange system, and shows a configuration between an OMP 100, a Central Control Peripheral Processor (CCPP) 106, and a CIN 108 in an SDX-200 exchange system. will be. The CIN 108 is a dedicated network for the IPC and includes a CIP 110 and a plurality of nodes 112 to 118, which are processors for controlling the CIN 108. Among the nodes 112-118, the node 112 is a CIP node connected to the CIP 110, and the node 114 is a central control subsystem connected to the OMP gateway 102 of the OMP 100. A gateway 120 and is connected to the CIP node 112. The OMP 100 has an OMP gateway connected to the CCS gateway 120 and an IPCH 104 connected by the CCPP 106 and the IS-bus. The CCPP 106 is connected to the CIP 110 by the TD bus as well as to the OMP 100 by the IS bus. Here, the IPC between the CIP 110 and the OMP 100 is represented by a thick line in FIG. 1, that is, an OMP (the CIP node 112, the CCS gateway 120, and the OMP gateway 102 from the CIP 110). Through the path up to 100). The range of the IPC module is CIP 110, CIP node 112, CCS gateway 120, cable between CCS gateway 120 and OMP gateway 102, and CIN 108. Therefore, OMP gateway 102 and IPCH 104 of OMP 100 are excluded.

Status auditing for the IPC module according to the present invention is done in System Status Control (SSC) in the OMP 100. Monitoring is performed by the main processor (MP) and CIP IPC answer (back) at regular intervals, and recovery is performed by the operator offline. Of course, fault descriptions or actions are recommended as faults to aid operator judgment.

The status audit for the IPC module of the present invention is performed by the MP status monitoring result, the CIP 110 status monitoring result and the IPC module status monitoring result. Where MP status monitoring is the IPC processor status monitoring for the MP, CIP (110) status monitoring is the IPC processor status monitoring for the CIP (110), IPC module status monitoring is the IPC module through CCPP 106 matching the bypass path It's a condition monitoring. Here, the CCPP 106 matching has two preconditions that the IPC processor status monitoring result for the CIP 110 is abnormal and the CCPP status must be normal.

2 is an IPC module state audit flow chart according to an embodiment of the present invention, which shows the steps performed by the SSC in the OMP 100 in steps 200 through 206. First, the OMP 100 monitors the state as an IPC answer-back for all MPs mounted in the CIN 108 in step 200, and the CIP through the IPC path between the CIP 110 and the OMP 100. State monitoring is performed with an IPC response to 110.

The MP state monitoring period is, for example, 7 seconds, and the IPC response attempt is defined as a delay signal processing of up to 2 times and 2 seconds. If a response is received within the period, the processor state is defined as normal. If the response is not received within the period, the processor state is defined as abnormal.

In addition, CIP status monitoring OMP 100 monitors the status of the IPC response to the CIP (110). As described above, each point existing on the path indicated by the bold line in FIG. 1, that is, the CIP 110, the CIP node 112, the CCS gateway 120, and the OMP gateway 102 are the most important IPC control in the exchange. , Delivery, and management take place. If problems occur at these points, the safety and reliability of the system is lost. As such, it periodically monitors this path. This monitoring is CIP status monitoring. For example, in this CIP state monitoring, a cycle is defined as 6 seconds, IPC response attempts are defined up to 2 times, and IPC module status monitoring through CCPP 106 matching, which is a bypass path, is defined as 3 seconds. The CIP state is defined as normal when the response is received within the period and abnormal when no response is received within the period.

The CIP 110 monitoring, in practice, the monitoring method between the CIP 110 and the OMP 100 sends a CIP monitoring signal from the OMP 100 to the CIP 110 as shown in FIG. If it waits and receives it within 3 seconds, it is determined that the path is normal.

In operation 202, the OMP 100 checks whether the CIP state is abnormal as a result of the CIP state monitoring. In this case, if the CIP state is not abnormal, the process returns to the step 200, but if it is determined that the state is abnormal, the IPC module state monitoring is performed in step 204. That is, if it is normal, CIP monitoring is continued every 6 seconds. If abnormal, IPC module monitoring signal is sent to CCPP 106 and IPC module status monitoring information is received from CCPP 106 as shown in FIG. Investigate where the problem occurred. This is the IPC module status monitoring. The CIP 110 monitoring can only know if it has received a positive acknowledgment acknowledgment from the CIP 110, but cannot know at what point the problem occurred. However, IPC module status monitoring can provide information on where the problem is. The IPC module state monitoring is performed at the time when it is determined that the CIP monitoring result is abnormal, that is, when no acknowledgment ACK is received within 3 seconds from the CIP 110.

At this time, the IPC module state monitoring information is obtained through the CCPP 106, and the MPC state monitoring information obtained from the MP state monitoring is combined to determine the IPC module state. In addition, IPC module status monitoring is performed every turn only when the previous judgment was no response, and every other time, every other time.

Information is provided from the CIP 110 via the CCPP 106 connected to the IS-bus in one subsystem. However, since the TD-bus performance providing the interface between the CCPP 106 and the CIP 110 performs not only the IPC module status monitoring but also various other functions, it cannot be continuously connected every six seconds. Therefore, after interlocking once, it rests and then interlocks next time. Of course there are constraints. CCPP 106 must be alive normally and CIP 110 must be alive. Monitoring for the CCPP 106 processor is performed in the OMP 100. The normal / abnormal status of the CIP processor itself can only be determined by entering the IPC module status monitoring.

Here, the determination according to the data about the IPC module obtained by the OMP 100 through the bypass path, that is, the CCPP 106 matching is performed by the CIN 108 module fault, the CIP node 112 fault, and the CCS gateway 120 fault. And the cable fault between the CCS gateway 120 and the OMP gateway 102, the CIP 110 processor fault, and the TD-bus fault. Among them, the CIN 108 module fault is all MP IPC state management data when the operating system (OS) is disconnected, the CIP 110 processor fault is no response, and the TD-bus fault is an abnormal TD-bus. If

If it is determined as a fault as described above, the OMP 100 performs an IPC module state recovery that informs the operator by fault online in step 206 and ends. The IPC module state recovery is performed with the monitoring result determination data made through CCPP 106 matching, which is a bypass path. First, notify the operator by fault online. In this case, the fault history allows the operator to recover the offline state with the fault history or recommended action.

Therefore, when the CIP 110 status monitoring result is abnormal, it is possible to secure the IPC reliability by determining the fault status through the CCPP 106 matching, which is the bypass path, and informing the operator to recover the IPC module state.

Meanwhile, in the above description of the present invention, specific embodiments have been described, but various modifications can be made without departing from the scope of the present invention. In particular, in the embodiment of the present invention, the example applied to the SDX-200 exchange system, but if the same structure is applied as well. Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the equivalent of claims and claims.

As described above, the present invention has an advantage of ensuring IPC reliability by auditing the IPC module.

Claims (3)

A CIN having a CIP and a CIP node and a CCS gateway, an OMP having an OMP gateway connected to the CCS gateway, a CCPP connected to the CIP by a TD bus and an OMP by an IS bus. And auditing the IPC module in a switching system having an IPC module from the CIP to the CIP node, the CCS gateway, and the OMP through the OMP gateway, An MP status monitoring process in which the OMP monitors the status of all MPs mounted in the CIN in an IPC response; A CIP status monitoring process in which the OMP monitors an IPC response to the CIP through an IPC path between the CIP and the OMP; If it is determined that the monitoring result for the CIP is abnormal, the IPC module that the OMP obtains the IPC module status monitoring information through the CCPP and combines the MP status monitoring information obtained in the MP status monitoring process to determine the IPC module status. Status monitoring process, IPC module audit method characterized in that it comprises a process for recovering the IPC module status to notify the operator on-line when the fault is determined during the IPC module status monitoring process. The method of claim 1, wherein the fault details are fault details or recommended actions for causing the operator to recover the offline state. The method of claim 1, wherein the determination of the IPC module status in the IPC module status monitoring process comprises: CIN module fault, CIP node fault, CCS gateway fault, cable fault between CCS gateway and OMP gateway, and CIP processor. IPC module audit method characterized in that it determines which of the fault and the TD-bus fault.