KR100302928B1 - Hardware-managed programmable unified/split caching mechanism for instructions and data - Google Patents

Abstract

In accordance with the present invention, a method is provided for allocating cache used by a processor of a computer system between at least two value classes, such as instructions and data. One logical device is connected to the cache to monitor the relative usage of the cache by each class and to select a predetermined cache usage rate by the class among a number of available rates, and cache blocks within the cache replace the cache that has been removed. Is removed using a cache replacement mechanism that restricts to a particular class of value classes based on a given cache usage ratio. The multi-bit function is provided to indicate how to limit the selected victor to a given cache block, and the logic device selects a given cache usage rate by setting the multi-bit function. The cache replacement mechanism may be a least recently used replacement mechanism that has been modified to limit replacement of removed caches to a particular class of value classes based on a given cache usage rate. Multiple available ratios may include, for example, instruction / data cache block usage ratios of 1: 1, 1: 2, and 2: 1.

Description

HARDWARE-MANAGED PROGRAMMABLE UNIFIED / SPLIT CACHING MECHANISM FOR INSTRUCTIONS AND DATA}

TECHNICAL FIELD The present invention generally relates to computer systems, and more particularly, to a cache used by a processor, and more particularly to a method of efficiently using an associative cache.

1 shows the basic structure of a conventional computer system 10. Computer system 10 may include one or more processing devices, of which two processing devices 12a, 12b are shown, such processing devices (such as display monitors, keyboards, permanent storage devices). Input / output (I / O) device 14, a memory device 16 (such as random access memory, or RAM) that is used by a processing device to execute program instructions, one of the peripheral devices each time the computer is first turned on. It is connected to several peripheral devices, including firmware 18, whose primary purpose is to seek and load an operating system from one device (usually a permanent memory device). Processing devices 12a and 12b communicate with peripheral devices by a variety of means, including common interconnects, bus 20. For example, computer system 10 may have many additional components not shown, such as serial and parallel ports for connecting to a modem or printer. One of ordinary skill in the art has other components that can be used in connection with what is shown in the block diagram of FIG. 1, for example a display adapter can be used to control a video display monitor, It will be appreciated that the memory controller can be used to access memory 16, and so forth. Also, instead of connecting the I / O device 14 directly to the bus 20, the I / O device 14 is connected to a secondary (I / O) bridge of the I / O bridge of the bus 20. May be connected to the bus. The computer may have two or more processing devices.

In symmetric multiprocessor (SMP) computers, all processing units are generally the same. That is, these processing units all use a common set of instructions and protocols or a set of protocols for operation, and generally have the same architecture. A typical structure is shown in FIG. The processing device includes a processor core 22 having a plurality of registers and execution units for executing program instructions for computing a computer. Exemplary processing apparatus includes a power ^TM PC (PowerPC ^TM) processor marketed by International Business Machines (IBM) Corporation. The processing device may also have one or more caches, such as an instruction cache 24 and a data cache 26, implemented using a high speed memory device. Instructions and data may be distinguished and passed to each cache 24, 26 by examining a signal indicating whether the CPU requires an operation with an operand as an operand or an operation with the data as an operand. The cache is typically used to temporarily store values that can be repeatedly accessed by the processor to speed up processing by avoiding longer steps of loading values from memory 16. This cache is referred to as an "on-board" when packaged integrally with the processor core on a single integrated chip 28. Each cache is associated with a cache controller (not shown) that manages the transfer of data between the processor core and the cache memory.

Processing device 12 may include additional caches, such as cache 30, referred to as level 2 (L2) caches because they support on-board (level 1) caches 24 and 26. In other words, the cache 30 acts as an intermediate step between the memory 16 and the on-board cache, and can store a greater amount of information (instructions and data) than the on-board cache can store, but more There is a large access penalty. For example, the cache 30 may be a chip having a storage capacity of 256 or 512 kilobytes, and the processor may be an IBM PowerPC ^™ 604 series processor with an on-board cache with a total storage capacity of 64 kilobytes. have. The cache 30 is connected to the bus 20, and the loading of all information from the memory 16 to the processor core 22 must be through the cache 30. Although FIG. 1 shows only a two-level cache hierarchy, a multilevel cache scheme with a multilevel serial connection cache may be provided.

The cache has many "blocks" that store several instructions and data values separately. Blocks in any cache are divided into groups of blocks called "sets". One set is a collection of cache blocks in which a given memory block can reside. For any given memory block, depending on the preset mapping function, there is a unique set in the cache to which the block can be mapped. The number of blocks in one set is called the associative nature of the cache. For example, a two-way set association means that for any given memory block, there are two blocks in the cache to which the memory blocks can be mapped. it means. However, several different blocks in main memory can be mapped to any given set. The one-way set associative cache is mapped directly, i.e. there is only one cache block that can contain a particular memory block. A cache is said to be fully associative when a memory block can occupy some cache block, that is, when there is a set, and the address tag is a pool of memory blocks ( full) address.

The illustrated cache line (block) includes an address-tag field, a state-bit field, an inclusivity-bit field, and a value field for storing the actual instruction or data. The status-bit field and the overall-bit field are used to maintain cache coherency in multiprocessor computer systems. The address tag is a subset of the full address of the corresponding memory block. A comparison match between one of the tags in the address-tag field and an incoming valid address represents a cache "hit." The set of all address tags (and sometimes status-bit and aggregate-bit fields) in one cache is called a directory, and the set of all value fields is a cache-entry array.

When all blocks in one set for a given cache are full and such a cache receives a request whether it is a "read" or a "write" to a memory location that maps to a full set, the cache will block the current block in this set. You must "evict" one of them. The cache selects the block for removal by one of a number of means known to those skilled in the art (least recently used, random, pseudo-LRU, etc.). If the data in the selected block is modified, that data can be another cache (in the case of L1 or on-board cache) or main memory (in the case of L2 cache, as shown in the two-level structure of FIG. 1). Which is then written to the next lowest level in the hierarchy. By the principle of inclusion, the lower levels of the memory hierarchy already have blocks available for holding the written correction data. However, if the data in the selected block is not modified, the block is simply discarded and is not written to the next lowest level of the hierarchy. This process of removing one block from one level of the scheme is known as "eviction". At the end of this process, the cache no longer retains a copy of the removed block.

Certain procedures (programs) executed on the processor have the unintended effect of repeatedly using a limited number of sets (congruence classes), thus making the cache less efficient. In other words, if one procedure causes a large number of removals within a small number of joint class members without using a large number of other members, the memory latency delay is increased. This effect, called stride, is associated with the joint mapping function and the manner in which certain procedures allocate memory blocks in main memory device RAM 16. The statistical advantage of using a specific associative cache is not obtained for this type of procedure.

Another statistical advantage that is sometimes obsolete relates to providing partitioned cache blocks (eg, cache 24 and cache 26) for instructions and data. Typical processing units provide the same number of L1 cache blocks for instructions and data, so 50% of available cache entries can be used at this level for instructions and 50% can be used for data. There is no distinction in the L2 cache. That is, at the L2 level, 100% of the cache can be used for instructions and 100% can be used for the data. However, this ratio of available blocks for instruction to data is not always the most efficient use of cache for a particular procedure. Many software applications perform better when run in a system with partitioned I / D caching, while others perform better when run in a uniform, integrated cache (assuming the entire cache space is the same). . If the cache I / D ratio is not particularly close to the actual rate of instruction and data cache operations, there is a problem of removal.

Another statistical advantage of associative caches that can be lost is associated with a cache replacement algorithm that determines which cache block of a given set is removed. For example, an 8-way association cache may use an LRU device that examines a 7-bit field associated with that set. Due to the specific cycling frequency of the procedure executed on the processor, this 7-bit LRU algorithm may result in removing more cache blocks than if the cache is 4-way or 2-way associative.

Statistical optimization of the associative cache is difficult. This is because different technical applications may provide different stride states or different instruction / data ratios. For example, desktop publishing programs, warehouse inventory programs, aerodynamic modeling programs, and server programs can all provide different stride states or instruction operation to data operation ratios. Therefore, it is desirable and advantageous to design a cache that can more fully optimize its statistical benefits regardless of the type of procedure executed on the processor.

It is therefore an object of the present invention to provide an improved cache for a processor of a computer system.

Another object of the present invention is to provide a cache that optimizes the statistical advantages of association.

Another object of the present invention is to provide a cache that optimizes the statistical advantages of accessing instruction versus data.

It is another object of the present invention to provide a cache that optimizes the statistical advantages of the cache replacement (removal) algorithm.

The above object is achieved in a method of allocating a cache used by a processor of a computer system between at least two value (instruction and data) classes, which method is connected to the cache and relative to the cache by each class. Providing a logic device for monitoring usage; Selecting a predetermined cache usage rate by class among a plurality of available rates; And removing the cache block in the cache using a cache replacement mechanism that restricts replacement of the removed cache to a particular class of value classes based on a predetermined cache usage ratio. A multi-bit function may be provided to indicate how to limit the selected Victim to a given cache block, and the logic device selects a given cache usage rate by setting the multi-bit function. The cache replacement mechanism may be an LRU replacement mechanism that has been modified to limit replacement of removed caches to a particular class of values based on a given cache usage ratio. Multiple available ratios may include, for example, instruction / data cache block usage ratios of 1: 1, 1: 2, and 2: 1.

The above and further objects, features and advantages of the present invention will become apparent from the following detailed description.

1 is a block diagram of a prior art multi-processor computer system.

2A-2C illustrate a novel method of changing the association for an association cache.

FIG. 3 illustrates one method of providing programmable associations, such as those shown in FIGS. 2A-2C, using basic congruence class mapping modified by creating additional classes using bits from address tags. drawing.

4 illustrates a novel method of providing a programmable joint class that allows random assignment of specific addresses to specific joint classes by switching address bits.

FIG. 5 is a high-level schematic diagram of a hardware implementation that provides a programmable joint class such as that shown in FIG. 4, using encoding values for each bit of the address as a whole.

6 is a block diagram of a novel cache with a replacement control device allowing random components to be introduced in varying the rank of the LRU algorithm.

<Description of Symbols for Main Parts of Drawings>

40: cache

50: 5-bit programmable field

52: 5-to-32 decoder

54: AND gate array

56: OR gate array

The present invention relates to more efficient computation by the cache of a processing apparatus and provides several methods for improving cache efficiency. One method relates to the association of cache structures and can be understood with reference to FIGS. 2A-2C, which illustrate the different states of a single cache 40. Cache 40, which may include a cache controller (not shown), has a number of cache lines arranged in sets (joint classes) to provide association. In the first state of the cache 40 shown in FIG. 2A, there are eight cache lines in one set, for example, cache lines 1 through 8 in set 1, cache lines 9-16 in set 2, and the like. This means 8-way association. Entries in cache 40 may be of varying formats, such as having an address tag field, a status bit field, a global bit field, and a value field.

The still picture of FIG. 2A provides the advantages of a conventional eight-way associative cache, but the present invention additionally provides associative adaptability or programmability, as shown in FIGS. 2B and 2C. In FIG. 2B, each 8-block set was divided into two smaller sets, including sets 1a, 1b, 2a, 2b. Each of these sets contains four blocks, so the state of this cache 40 is a four-way association. In Figure 2c, this set is further subdivided to generate two blocks per set, i.e. to generate a two-way association. This progression may extend to one-way association. Also, such progression may begin with 16 instead of a larger number of cache blocks, eg 8, in the largest set.

The ability to replace the associative level of cache 40 allows the cache to operate more efficiently. As described in the description of the prior art, there may be some procedures that cause a stride, in part due to a particular association size, that is, causing a cache to circulate within one or two joint classes. In this procedure, strides can be eliminated or minimized by using different association sizes. This degree of association can be optimized for different applications by providing one or more programmable bits that are used to indicate which level of association is desired. For example, Table 1 shows how a programmable 2-bit function can be used to implement the adaptive association scheme of FIGS. 2A-2C.

correlation Program bits Joint class Address bits LRU bit 8-way 00 N A 7 4-way 01 N x 2 A-1 3 2-way 10 N x 4 A-2 One Directly mapped 11 N x 8 A-3 0

The 2-bit function is set to "00" to indicate 8-way associations, to "01" to indicate 4-way associations, to "10" to indicate 2-way associations, Set to "11" to indicate one-way association (ie, direct mapping). The necessary subdivision for this set is controlled by modifying the joint-class mapping function to conveniently use one or more specific subsets of the original set. In other words, the two sets 1a and 1b contain only the cache lines that were in the original set 1 and the sets 1c and 1d contain only the cache lines that were in the first subdivided set 1a. For a cache 40 with a fixed number of cache lines, this means that the number of joint classes varies between N and N x 8, where N is the minimum number of joint classes defined by the basic mapping function.

The manner in which a particular subset is identified can vary. Some of the full addresses of memory blocks may be used to distinguish joint class mappings. For example, a 32-bit full address may be classified into three parts, namely an offset field, a joint class field, and an address-tag field, as shown in FIG. In this example, the six bit offset field defines the exact location of the byte in the value field corresponding to the actual instruction or data. The joint class field is used as an operand input to the mapping function and allocates a block of memory to the primary set, ie one set has eight blocks, such as set 1. In this example, the joint class field is 13 bits and the address tag is 13 bits for 8-way association, but the joint-class field is efficiently augmented for different levels of association by using different bits in the address tag, in this case The address-tag field is reduced. Four-way association is performed by using the last bit in the original address tag field to subdivide the eight-block set into two smaller groups of four blocks each. Similarly, two-way or one-way association is performed by using the second bit as the last bit or the third bit as the last bit in the original address tag field to further refine the set.

Programmable association may be provided by hardware or software that realizes 2-bit functionality. In the implementation described above, the logic device may collect miss information and select an association level based on a predefined criterion, which criterion is the maximum miss rate for any one joint class, or one or more It is equal to the maximum-miss rate for a class above a predetermined number of joint classes having a miss rate above a threshold. This association management can be done dynamically, so that the cache reacts quickly to changes in the nature of procedures running on the processor, such as replacements in the form of applications running on a computer system. Alternatively, a set of connection pins can be used for manual selection. Similarly, software (program instructions) can be operated to adjust the level of association. Although application software may be provided for certain programs known to have procedures that can cause strides, the application software may set the 2-bit associative function to a known and appropriate level to reduce excessive memory latency due to strides. Can be. The application software may intermittently adjust the level of association based on the different routines used by the program. Operating system software can be used to monitor address requests and to predict in a predictive manner how this procedure works at different levels of association. In this case, the operating system can select the most efficient level. This technique provides real-time control of the level of association even during program execution.

Programmable association described above provides one way of influencing a joint class, for example by increasing the number of joint classes according to multiplicative factors in the illustrated embodiment. Another way to improve cache efficiency in accordance with the present invention relates to other features of the joint class and to the feature of the mapping function that specifies which particular memory block should be assigned to which joint class. Prior art mapping techniques typically include modulo-type functions, but the circular nature of such functionality can cause stride problems. The present invention solves this problem by using a mapping function that allows a pool or partial address to be encoded with a new and unique address, i.e., by randomly (predefining) assigning a particular address to a particular joint class. As shown in the example of Figure 4, the tenth bit in the full (original) 32-bit address is shifted to the 26th bit in the encoded 32-bit address, and the 26th bit in the original address is in the encoded address. Shifted to the 18th bit, the 18th bit in the original address is shifted to the 22nd bit in the encoded address, and the 22nd bit in the full (original) address is shifted to the 10th bit in the encoded address. In this example, a unique random assignment of a given address to a particular joint class is provided by switching address bits.

In addition, the programmability of such joint classes can be realized by hardware or software implementation. The application software may provide an encoding of the appropriate address before it is passed to the cache / processor, or the interpreter may be used to monitor the allocation of memory blocks and modify the address as it is passed to the hardware. This technique allows for adjusting the number of joint classes intermittently or in real time. 5 shows a hardware implementation. Multiple 5-bit programmable fields 50 are provided, one for each bit in the address (full or partial) to be encoded. Each of these 5-bit programmable fields 50 is fed into a respective 5-to-32 decoder 52, with each decoder output 32 lines having a respective AND gate array 54. (32 AND gates per array). The output of AND gate array 54 (32 lines each) is branched to a number of OR gates 56. Each OR gate 56 receives one output from each AND gate array 54. The output of the OR gate 56 provides a shifted value for the encoded address. Such hardware provides a programmable joint class by selecting the appropriate value for the 5-bit programmable field 50, and can also dynamically collect miss information and select any mapping function based on predetermined criteria. Flushing the cache is required by the hardware implementation before changing the association level to ensure consistency.

The programmable joint class described above is independent of the programmable associations described above. This is irrelevant even though the two can be used in combination. For example, programmable association can be used to set the two-bit association function to optimize its level, and a programmable joint class using a 5-bit encoding field can also be used to lower the removal rate.

Another method for improving cache efficiency in accordance with the present invention relates to the use of cache for instruction versus data. In computer systems implementing a CPU-caching scheme, a cache is a federated cache in which instructions and data are always treated the same, or a portion of the total cache RAM space (usually 1/2) is instruction-only and the rest is data-only. It is common to be predefined as a partitioned I / D cache. In addition, in conventional partitioned I / D cache designs, the ratio of space dedicated to instruction to data is fixed (usually 50% / 50%).

This specification describes a novel cache allocation design in which the instruction / data partition ratio is programmed according to varying degrees. In one implementation, programmability is provided by a 2-bit I / D function (hereinafter referred to as "id_ratio") that is read and written by software. The definition for setting this function shown in Table 2 below is for the illustrated implementation. However, the present invention can be easily adapted or extended to other cache rates.

id_ratio Justice 00 100% cache allocated within instructions and data 01 50% of cache instruction and 50% of data allocated to instructions only 10 50% of cache instructions allocated to data only and 50% of data allocated to data 11 Suspended

Programmable I / D ratios are performed by modifying the Victim replacement algorithm of the set association cache. In the implementation below, the cache is an 8-way set association (having 8 members, denoted as a, b, c, d, e, f, g, h) and a 7-bit LRU algorithm is used. In this implementation, the normal Victim selection logic is described by the following boolean equation. The following logic represents a 7-bit LRU algorithm of the prior art (in this Boolean expression, "＾" is logical NOT (inverted), "&" is logical AND and "+" is logical OR).

victim_is_member_a = ＾ 1ru_bits (0) & ＾ 1ru_bits (1) & ＾ 1ru_bits (3);

victim_is_member_b = ＾ 1ru_bits (0) & ＾ 1ru_bits (1) & 1ru_bits (3);

victim_is_member_c = ＾ 1ru_bits (0) & 1ru_bits (1) & ＾ 1ru_bits (4);

victim_is_member_d = ＾ 1ru_bits (0) & 1ru_bits (1) & 1ru_bits (4);

victim_is_member_e = 1ru_bits (0) & ＾ 1ru_bits (2) & ＾ 1ru_bits (5);

victim_is_member_f = 1ru_bits (0) & ＾ 1ru_bits (2) & 1ru_bits (5);

victim_is_member_g = 1ru_bits (0) & 1ru_bits (2) & ＾ 1ru_bits (6);

victim_is_member_h = 1ru_bits (0) & 1ru_bits (2) & 1ru_bits (6);

In order to modify the I / D ratio, the selected BIC team depends on the setting of "id_ratio" and depending on whether the CPU requires an instruction read (i_read) or a data read (\ i_read). Limited to members only.

d50_mode = (id_ratio = "01");

i50_mode = (id_ratio = 10 ");

gate_abcd = ＾ ((d50_mode & ＾ i_read) + (i50_mode & i_read)).

The " gate_abcd " signal, when " 1 ", allows the joint class members a, b, c or d to be used as a big team for replacement. If "gate_abcd" is "0", the joint class members e, f, g or h should be used as the big team. Therefore, the big team selection formula is modified as follows.

victim_is_member_a = gate_abcd & &quot; 1ru_bits (0) & &quot; 1ru_bits (1) & &quot; 1ru_bits (3);

victim_is_member_b = gate_abcd & &quot; 1ru_bits (0) & &quot; 1ru_bits (1) & 1ru_bits (3);

victim_is_member_c = gate_abcd & &quot; 1ru_bits (0) & 1ru_bits (1) & &quot; 1ru_bits (4);

victim_is_member_d = gate_abcd & ＾ 1ru_bits (0) & 1ru_bits (1) & 1ru_bits (4);

victim_is_member_e = (＾ gate_abcd + 1ru_bits (0)) & 1ru_bits (2) & 1ru_bits (5);

victim_is_member_f = (＾ gate_abcd + 1ru_bits (0)) & ＾ 1ru_bits (2) & 1ru_bits (5);

victim_is_member_g = (＾ gate_abcd + 1ru_bits (0)) & 1ru_bits (2) & ＾ 1ru_bits (6);

victim_is_member_h = (＾ gate_abcd + 1ru_bits (0)) & 1ru_bits (2) & 1ru_bits (6);

As an example of use of the present invention described above, consider the case where id_ratio = " 01 ". In this case, if the CPU requires reading the instruction, gate_abcd = "1", any of the eight joint class members can be selected as the big team for replacement. If the CPU requires reading data, members e, f, g or h can be selected as the big team. As a result, the entire cache can be used to store instructions, but only 50% of the cache can be used to store data. Therefore, in this mode, the cache is "weighted" toward the instruction. The above example provides instruction / data cache block usage ratios of 2: 1, 1: 1 and 1: 2. For example, by increasing the available cache capacity by 12.5%, other ratios such as 3: 1, 4: 1, or 8: 1 can be provided, with 3-bit I / D being 12.5%, 25%, 37.5 It can be used to provide relative usage of%, 50%, 62.5%, 75%, 87.5% or 100%.

This new cache-allocation design provides a programmable instruction / data partitioning ratio. This allows a software application or operating system to adjust the weight of instructions versus data in the cache in real time for optimal performance. The I / D cache rate setting can be changed at any time without the need for software to first save the state of the CPU and cache. The technique can also be implemented in hardware by monitoring the relative usage of instruction reads versus data reads. In addition to the LRU victor selection logic, the cache controller logic works in the same way regardless of which I / D ratio mode is used. This programmability can be adapted for use in all types of caches (in-line, lookaside, write-through, etc.). While the embodiments of the present invention described above use an 8-way set associative cache, the present invention can be applied to any degree of associative (2-way or more). In addition, although the implementation described above uses a 7-bit LRU algorithm, the present invention can be applied to other LRU algorithms. By using Victim selection logic as a means by which variable I / D weighting is performed, the present invention can be implemented with very little logic circuitry.

Another method for improving cache efficiency in accordance with the present invention is directed to a mechanism for removing cache blocks in a manner other than controlling the relative cache usage of two value classes (command or data). Even with the techniques described above for improving the efficiency of the cache, there may be some levels of striding, especially due to the allocation of memory blocks and the recursive pattern that occurs between each cache block. In this case, one method may be provided for further modifying the cache replacement algorithm (e.g., LRU) to introduce a defined dement of randomness that eliminates inefficient cyclic elimination to reduce strides. Can be.

One embodiment of this feature of the invention is shown in FIG. The cache 60 includes a cache entry array 62 of various values stored in the cache, a cache directory 64 for tracking entries, and a replacement control device 66 using an LRU algorithm that is optionally modified by a random factor. It contains several components. In this embodiment, there are four possible variations of the replacement control device for introducing a random element. In the first variant 68, when randomization is not introduced, 7-bit is used to select the LRU cache block within the 8-block set (ie, the cache is an 8-way association) and some random No additional bits are required for the randomizer.

If some randomization is needed, in the second variant 70, the replacement algorithm is modified by introducing some randomness. Only three LRU bits are used for selection within a given joint class (cache set) between the four groups, each group containing one quarter of the class, or two in the case of an 8-way associative cache. Contains a block. After this two-member group (subclass) is selected, a single random bit is used to select one of the two blocks in that group. If further randomization is required, the third variant 72 uses a 1-bit LRU algorithm to classify the original joint class into two subclasses (four blocks each when the cache is an 8-way association), Two random bits are used to select one of the four subclass members. Finally, in the last variant 74, no LRU is used, and three random bits are used to completely determine the block for removal within the eight-member class.

In Figure 6, the LRUs and random blocks are shown separately, but they can be combined into a single 7-bit field. In other words, these fields are fully used for variant 68, but only four bits of these fields are variant 70 (three LRU bits and one random bit) and variant 72 (two LRU bits). And two random bits), and in variant 74 only three bits of the field are used.

Although the example of Figure 6 is for 8-way association, one of ordinary skill in the art will appreciate that the present invention can be applied to other set sizes. For example, in a four-way association set, there can be three variants, a first variant that uses three LRU bits and no random bits, one LRU bit, and one random bit. There may be a second variant, and a third variant using two random bits without using the LRU bit. The two-way association set can have two variants. That is, there is a first variant that uses one LRU bit and no random bits, and a second variant that uses one random bit and no LRU bits. This varying randomness is another way of optimizing the removal and can be used with any of the programmable associations, programmable joint classes, and programmable I / D ratios described above.

The improved cache described herein can be used as an on-board L1 cache, or a low-level cache (eg, L2). While such a cache configuration may be used for one or a limited number of cache levels in the cache scheme, one of ordinary skill in the art would recognize that it is desirable to use this configuration for all cache levels to maximize performance. The invention is generally applicable to single processor computer systems as well as to multiprocessor computer systems.

Although the present invention has been described with reference to specific embodiments, this description is not meant to be interpreted in a limiting sense. Referring to the description of the present invention, those skilled in the art will appreciate that various modifications of the illustrated embodiments, as well as alternative embodiments of the present invention, are possible. It is, therefore, to be understood that such modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

According to the present invention, there is an effect of designing a cache that can more fully optimize its statistical advantages regardless of the type of procedure executed on the processor.

Claims (18)

A method of allocating cache used by a processor of a computer system between at least two value classes, Providing a logic device connected to the cache to monitor the relative use of the cache by each class; Selecting a predetermined cache usage rate by classes from the plurality of available rates; And Removing the cache block in the cache using a cache replacement mechanism that restricts replacement of the removed cache to a particular class of value classes based on a predetermined cache usage ratio. Cache allocation method comprising a. 2. The method of claim 1 wherein the two value classes are instructions and data. The method of claim 1, Providing a multi-bit function to indicate how to limit the selected big team to a given cache block; And the logical unit selects a predetermined cache usage ratio by setting a multi-bit function. The method of claim 1, wherein the cache replacement mechanism is an LRU replacement mechanism modified to limit replacement of removed caches to a particular class of value classes based on a predetermined cache usage ratio. 3. The cache allocation method of claim 2, wherein the plurality of available ratios comprises an instruction / data cache block usage ratio of 1: 1. 3. The cache allocation method of claim 2, wherein the plurality of available ratios comprises an instruction / data cache block usage ratio of 1: 2. 3. The cache allocation method of claim 2, wherein the plurality of available ratios comprises a 2: 1 instruction / data cache block usage ratio. The method of claim 2, The multiple available magnifications include instruction / data cache block usage ratios of 1: 1, 1: 2, and 2: 1, Providing a 2-bit faculty to indicate which of the instruction / data cache block utilization rates will be used as a given cache usage rate. Cache allocation method further included. 9. The method of claim 8, wherein the cache replacement mechanism is an LRU replacement mechanism modified to limit replacement of the removed cache to instruction reading or data reading based on a predetermined cache usage ratio. In a computer system, A processor; Memory devices; A cache connected to the processor and the memory device, the cache having a plurality of cache blocks to store a memory block corresponding to an address of the memory device; A logic device connected to the cache for monitoring the relative usage of the cache by at least two value classes and for selecting a predetermined cache usage rate by the classes from a plurality of available rates; And A cache replacement mechanism for removing a cache block in the cache that limits replacement of the removed cache to a particular one of the value classes based on the predetermined cache usage ratio Computer system comprising a. The method of claim 10, The two value classes are instruction and data; And the logic unit monitors the relative usage of the cache by detecting instruction read requests and data read requests. 11. The computer system of claim 10 further comprising a multi-bit functionality to indicate how to limit the selected Victim to a given cache block. 12. The computer system of claim 10 wherein the cache replacement mechanism is an LRU replacement mechanism modified to limit replacement of removed caches to a particular class of value class based on the predetermined cache usage ratio. 12. The computer system of claim 11 wherein the plurality of available ratios comprises an instruction / data cache block usage ratio of 1: 1. 12. The computer system of claim 11 wherein the plurality of available ratios comprises an instruction / data cache block usage ratio of 1: 2. 12. The computer system of claim 11 wherein the plurality of available ratios comprises an instruction / data cache block usage ratio of 2: 1. The method of claim 11, The plurality of available ratios includes instruction / data cache block usage ratios of 1: 1, 1: 2 and 2: 1, A 2-bit function for indicating which of the instruction / data cache block usage ratios will be used as the predetermined cache usage ratio; Computer system further including. 18. The method of claim 17, wherein the cache replacement mechanism is a least recently used replacement mechanism modified to limit replacement of the removed cache to one of the instruction read request or one of the data read requests based on a predetermined cache usage rate. Computer system.