KR100294048B1 - APPARATUS FOR REDUCING CLOCK JITTER WHEN OCCURS Synchronous Residual Time Stamp ERROR - Google Patents

Abstract

The present invention relates to a method and apparatus for preventing clock jitter in which an error may occur when using a phase locked loop technology called a synchronous residual time stamp, which is the core of the AAL1 technology. And a first difference value which is a difference value between a synchronous residual time stamp value detected by an arbitrary detection means and a locally generated synchronous residual time stamp value, and when the value of the counter reaches a predetermined value. A memory for storing a second difference value that is a difference value between two synchronous residual time stamp values, a means for obtaining a third difference value that is a difference value between a first difference value and a second difference value, and a third difference value having a specific value If the previous digital phase locked loop value is maintained or the TSDO value is changed by a certain value, and the third difference value has a value other than the specific value, an error is detected. And a protection block for maintaining the previous state, wherein the method for clock jitter mitigation in the case of a synchronous residual time stamp error comprises: driving a counter by a local clock, synchronous residual time stamp value detected by an arbitrary detecting means; Storing a first difference value, which is a difference value of the locally generated synchronous residual time stamp value, in a memory; and when the counter value reaches a predetermined value, a second difference value, which is a difference value between two synchronous residual time stamp values, is stored in the memory. Storing; obtaining a third difference value that is a difference value between the first difference value and the second difference value; if the third difference value has a specific value, maintaining a previous digital phase-locked loop value or setting a TSDO value to a predetermined value; If it has a value other than a specific value, it is recognized as an error and keeps the previous state. Can improve the quality.

Description

Clock jitter mitigation device and method for synchronous residual time stamp error {APPARATUS FOR REDUCING CLOCK JITTER WHEN OCCURS Synchronous Residual Time Stamp ERROR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device and a method for mitigating clock jitter in the case of a synchronous residual time stamp (SRTS) error. The present invention relates to an asynchronous transfer mode (ATM) network. The present invention relates to an apparatus and a method for minimizing jitter of a clock when an error of a synchronous residual time stamp is a clock recovery method of a transmission mode adaptation layer 1 (hereinafter referred to as AAL 1) technology.

In general, to realize a Broadband Integrated Service Digital Network (B-ISDN), as a core technology, asynchronous transmission mode is widely applied to the exchange and transmission fields. In addition, many systems using AAL 1 (not standard) have been introduced to absorb the telephone networks currently used, such as E1 / T1, into the asynchronous transmission mode network.

The synchronous residual time stamp is a technique in I.363.1, a standard drafted by the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T), which can transmit received clock information to devices that want to transmit it. It can be classified as one of phase locked loops (PLLs).

1 is a diagram of an apparatus for generating a synchronous residual time stamp, and FIG. 2 is a diagram of an apparatus for detecting a phase difference of a clock from a received synchronous residual time stamp. First, the parameters fs and fs' defined in FIGS. 1 and 2. fnx is

fn: Network clock (clock used for both transmitting and receiving side)

fs: service clock (clock recovered from input signal used in FIG. 1)

fs': service clock (local clock used in Figure 2)

fnx: A clock that satisfies the following two conditions

fs

fnx = fn / 2 ^ ⁿ (n: integer)

When applied to DS1E, which has a transmission rate of 2.048 Mbps, which is one of European communication methods, the parameter is fn = 155.52 Mbps, fs = 2.048 Mbps (the service clock of DS1E is 2.048 Mbps), fnx = 2.43 Mbps (the above). N = 3) that satisfies the condition.

In FIG. 1, fs is used to drive a 3008 counter 20 having a coefficient from 0 to 3007. Then, 16 counters 20 having coefficients of 0 to 15 are driven using fnx. When the value of the driven 3008 counter reaches 3007, the value of the 16 counter is stored in the memory element 30. This value stored in the memory element is the synchronous residual time stamp value, and is transferred to FIG. 2 by the method specified in the AAL 1 protocol.

2 has the same two devices. First, the 16 counters 100 are driven by fnx. Since fnx is the same value as in FIG. 1, the counters are operated at the same interval. In operation 3007, the 3008 counter 110 is driven at fs' to store the count value of the 16 counter 100 in the memory 120 as in FIG. 1. Where fs' is different from fs, the local clock can be adjusted. Then, the subtractor 130 obtains the difference between the value stored in the memory 120 and the synchronous residual time stamp value extracted from the received asynchronous transmission mode cell and stores the difference in the memory. By repeating this operation, you can see how out of phase you are by comparing the difference between the value stored in memory and the current value. Decision block 140 of FIG. 2 is responsible for this function, and has the following functions.

First, compare the current difference with the previous difference.

Second, the current difference is greater than the previous difference

If large: fs' is slower than fs-> increase PLL driving value by 1.

If small: fs' is faster than fs-> decrease PLL drive value by 1.

If same: Maintain previous state-> Maintain PLL drive value.

Third, error detection (if the difference between the current difference value and the previous difference value cannot come out other than +-1 or 0, if other values are not continuous, an error message is displayed and it is judged as a glitch. Maintain state.

If the decision block 140 described above determines how to adjust the clock, then action must be taken. The action here is either to make the clock faster, slower, or stay in that state. There are three ways to increase the clock.

1. There is an analog phase locked loop method that uses an op-amp to make an integrator to drive a voltage controlled oscillator (VCO).

2. There is a phase locked loop method using a digital analog converter (D / A converter). The information in the decision block is digitized to drive a voltage controlled oscillator.

3. A phase locked loop method using a digital phase locked loop, in which a clock is adjusted while appropriately dividing a high frequency signal based on information of a decision block.

These three methods have different circuits and methods, but ultimately take a passive action driven by the decision of the decision block. The reference that the decision block instructs to adjust the clock depends only on the difference between the input synchronization residual time stamp and the synchronization residual time stamp value generated by itself. Therefore, if an error occurs in these synchronous residual time stamp values, the decision block malfunctions and this malfunction affects the three phase locked loop circuits as they are.

As a result, transient cell losses in the system can amplify the jitter in the clock. And, when the high frequency transmission of DS3 (transmission method operating at 44.735Mbps), this effect can be further amplified. And once jitter occurs on the clock, it takes time to get back to normal, which can cause errors in the data.

Therefore, the present invention was devised to solve the above problems, and by identifying the characteristics of the clock and predicting the maximum possible jitter value and its effects, the synchronization to minimize the jitter of the clock generated in case of error, It is an object of the present invention to provide an apparatus and method for mitigating clock jitter in a residual time stamp error.

The above and other objects and novel features of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a circuit diagram for generating a synchronous residual time stamp using the protocol of ITU-T 363.1 applied to the present invention.

FIG. 2 is a circuit diagram of detecting a synchronous residual time stamp by using a protocol of ITU-T 363.1 applied to the present invention, and grasping a state of a clock.

3 is a circuit diagram illustrating in detail the internal structure of the crystal clock of FIG. 2 according to the present invention;

4 is coded in a high speed integrated circuit hardware description language of the protection block of FIG. 3 in accordance with the present invention;

<Description of the symbols for the main parts of the drawings>

10, 100: 16 counter

20, 110, 200: 3008 counter

30, 120, 210: Memory

130, 220: Subtractor

140: decision block

230: protection block

A preferred embodiment of the clock jitter mitigating device in case of a synchronous residual time stamp error according to the present invention, which was devised to achieve the above object, is a counter driven by a local clock and a synchronous residual time stamp detected by an arbitrary detecting means. A first difference value that is a difference between a value and a locally generated synchronous residual time stamp value, and a second difference value that is a difference value between the two synchronous residual time stamp values when the value of the counter reaches a predetermined value. Means for obtaining a third difference value that is a difference value between the first difference value and the second difference value, and maintaining the previous digital phase-locked loop value or resetting the TSDO value if the third difference value has a specific value. If the third difference value has a value other than the specific value, and if the third difference value has a value other than the specific value it is recognized as an error to continue the protection block It achieved by also.

In addition, a preferred embodiment of the clock jitter mitigation method in the case of a synchronous residual time stamp error according to the present invention, which is designed to achieve the above object, includes a step of driving a counter by a local clock and a synchronization detected by an arbitrary detection means. Storing a first difference value, which is a difference between a residual time stamp value and a locally generated synchronous residual time stamp value, in a memory; and when the value of the counter reaches a predetermined value, the difference value between the two synchronous residual time stamp values is determined. Storing a second difference value in the memory, obtaining a third difference value that is a difference value between the first difference value and the second difference value, and if the third difference value has a specific value, a previous digital phase synchronization If the loop value is maintained or the TSDO value is changed by a certain value, and it has a value other than the specific value, it is recognized as an error and the previous state is maintained. It is achieved by having the step of.

The present invention relates to a method for preventing jitter in a clock that may occur when an error occurs when using a phase locked loop technique called a synchronous residual time stamp, which is the core of the ALL1 technique. To do this, the characteristics of the clock are identified, and the maximum jitter value of the clock and its effects are predicted and compared with the current value. In this case, the jitter can be minimized by using this method when the predicted value and the measured value differ.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 shows the overall configuration of the decision block of the present invention.

Here, DIF is a difference between the synchronization residual time stamp detected in FIG. 2 and the locally generated synchronization residual time stamp value. This difference serves as a criterion for determining how different fs in FIG. 1 and fs' in FIG. 2 are. This value is stored once in memory 210, and the interval at which a new DIF occurs is at the time when the 3008 counter 200 of FIG. The value stored in the memory 210 is obtained by the subtractor 220 and the difference value DIF-DIF of the input value DIF is applied to the protection block 230. The difference value DIF-DIF is a factor that determines whether the value is applied from an error occurred synchronous residual time stamp or a value from a steady state. Once this value is determined how to control the clock, the output will be appropriate depending on what the external circuitry is.

All of the most important operations of FIG. 3 take place in the protection block 230, and are made by the VHSIC hardware description language (VHDL) source code as shown in FIG. The operation principle is as follows.

Once we calculate how jitter the clock can be for a change in the synchronous residual time stamp value,

For example, suppose you have applied the digital phase-locked loop technique described earlier in the DS1E system. At this time, the digital phase locked loop may bring a value change from -100 ppm to +100 ppm when an integer value (TSDO in VHDL Code) of -7 to +7 is applied. At this time, fs' may be offset from fs by up to +200 ppm. At this time, the time t that can be shifted while the 3008 counter has a value of 3007 is as follows.

t = 10 ^ ⁶ / (1000200 * 2.048 * 10 ^ ⁶ ) = 488.18361 ns

Therefore, even when the clock is shifted to the maximum, one or more values of the 16 counters driven by fnx may not differ by 3030 cycles. This indicates that DIF_DIF of FIG. 3 may not have a value other than 1, 0, and -1. Based on the above result, the VHDL code of FIG. 4 maintains the previous digital phase-locked loop value when 0, decreases the value of TSDO by 1 according to the definition of the decision block when -1, and increases the value by 1. Let's do it. In all other cases, it is regarded as an error state and the previous state is maintained.

Although the present invention may be modified in various ways and may take various forms, the detailed description of the present invention has been described with reference to specific embodiments only. It is to be understood, however, that the present invention is not limited to the specific forms referred to in the specification, but rather that the invention is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to include.

In the present application operating as described above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

By using the apparatus and method as described above, the present invention can predict that a value already comes next by a value stored once in memory. You can also take action ahead of time, which can greatly improve the quality of clock jitter or synchronous phase loops.

Claims (5)

A counter driven by a local clock; A first difference value, which is a difference value between a synchronous residual time stamp (SRTS) value detected by an arbitrary detection means and a locally generated synchronous residual time stamp value, and stored when the count value of the counter reaches a predetermined value; A memory for storing a second difference value which is a difference value between synchronous residual time stamp values; A subtractor for obtaining a third difference value which is a difference value between the first difference value and the second difference value; And When the third difference value has a specific value, the previous digital phase locked loop value is maintained or a TSDO value is changed by a predetermined value, and when the third difference value has a value other than the specific value, it is recognized as an error. A clock jitter mitigation device in the event of a synchronous residual time stamp error, characterized in that it includes a protective device to maintain the previous state. 2. The apparatus of claim 1, wherein the specific value of the third difference value is one of + −1 and 0. 3. Driving a counter by a local clock; Storing in the memory a first difference value that is a difference between a synchronous residual time stamp value detected by any detection means and a locally generated synchronous residual time stamp value; Storing a second difference value in the memory, the second difference value being a difference value between the two synchronization residual time stamp values when the value of the counter reaches a predetermined value; Obtaining a third difference value which is a difference value between the first difference value and the second difference value; When the third difference value has a specific value, the previous digital phase locked loop value is maintained or a TSDO value is changed by a predetermined value. When the third difference value has a value other than the specific value, the third difference value is recognized as an error and the previous state is maintained. And clock jitter mitigation in the event of a synchronous residual time stamp error. 4. The method of claim 3, wherein the specific value of the third difference value is one of + -1 and 0. 5. The method of claim 4, wherein when the specific value of the third difference value is 0, the previous digital phase locked loop value is maintained, when -1, the TSDO value is decreased by 1, and when +1, the TSDO value is decreased by 1. Clock jitter mitigation on synchronous residual time stamp error characterized by increasing.