KR100291769B1 - Gate driver for driving liquid crystal device - Google Patents

Abstract

The present invention is to provide a gate driver of a liquid crystal display device which can reduce the cost by enabling the same image expression while reducing the number of data lines to half the level of the past. The gate driver of the liquid crystal display device of the present invention is a gate driver for applying a drive signal to a scan line of a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal enclosed therebetween, and gates a vertical synchronization signal pulse. A shift register unit for shifting by a pulse clock; A logic circuit unit configured to selectively input a plurality of output signals from the output signals of the shift register unit and then output the logic operation; A level shifter unit configured to shift the output of the logic circuit unit to a predetermined level and sequentially output the same; And an output buffer unit sequentially applying the level shifted signal to the scan line.

Description

Gate driver for liquid crystal display {GATE DRIVER FOR DRIVING LIQUID CRYSTAL DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver of a liquid crystal display device. In particular, the number of data lines is halved by controlling a driving signal applied to two adjacent scanning lines so that an image signal can be transmitted to both pixel regions as one data line. The present invention relates to a gate driver of a liquid crystal display device, which can reduce the cost of the present invention and reduce the production cost while maintaining a high resolution.

A general liquid crystal display (LCD) is composed of a liquid crystal encapsulated between the upper and lower plates and the upper and lower plates.

On the upper plate, color filters layers of R (red), G (green), and B (blue) are arranged to express a black matrix, a common electrode, and a color.

In the lower plate, the data line and the gate line intersect each other and have a pixel area in a matrix form.

Each pixel region includes one thin film transistor (TFT) and a pixel electrode.

1 is a cross-sectional structure diagram of a general liquid crystal display device.

As shown in FIG. 1, the lower plate 1 includes a thin film transistor including a gate electrode Gate extending from the scan line (gate line), and a source electrode S and a drain electrode D extending from the data line. Are formed in matrix form at regular intervals.

In each pixel area, a pixel electrode 2a connected to the drain electrode D of each thin film transistor 2 is formed.

In the upper plate 3, a black matrix layer 4 is formed in a mesh form to block light transmission at portions other than the pixel electrode 2a formed on the lower plate 1.

R, G, and B color filter layers 5 for expressing color are formed between the black matrix layers 4.

The common electrode 6 is formed over the color filter layer 5 and the black matrix layer 4.

2 is a configuration diagram of a general liquid crystal display device.

As shown in FIG. 2, a panel unit 21 including a lower plate, an upper plate, and liquid crystals enclosed therebetween to display an image, and a gate driver for applying a driving signal in a row direction of the panel unit 21. A gate driver portion 22 made of (GD) and a source driver portion 23 composed of source drivers SD for applying a driving signal in the column direction of the panel portion 21.

Hereinafter, a liquid crystal display and a driver thereof will be described with reference to the accompanying drawings.

3 is a block diagram of a liquid crystal display according to the prior art.

As illustrated in FIG. 3, a plurality of scan lines G1, G1,... Gn-1, Gn are formed at predetermined intervals along the row direction, and each scan line is transversely formed. A plurality of data lines D1, D2,... Dn-1, Dn are formed in the losing direction.

The thin film transistors T1 are formed at the intersections of the scan line and the data line, and the pixel electrode C _LC is connected to each thin film transistor.

Therefore, the driving voltage is sequentially supplied to the scan line to turn on the thin film transistor, and the signal voltage of the corresponding data line is charged to the pixel electrode through the turned on thin film transistor.

4 is a waveform diagram of a driving signal applied to a scan line of a conventional liquid crystal display.

As shown in FIG. 4, since a driving signal is sequentially applied from the first scan line G1 to the n th scan line Gn during one horizontal period, the corresponding data line through the thin film transistor turned on by the corresponding scan line. The signal voltage of is transferred to the pixel electrode to display an image.

5A is a configuration diagram of a source driver according to a conventional liquid crystal display, and FIG. 5B is an operation waveform diagram of the source driver.

For reference, the source driver illustrated in FIG. 5A represents a 384 channel 6 bit driver. In other words, R, G, and B data each consists of 6 bits, and the column line (data line) is a source driver composed of 384 lines.

As shown in FIG. 5A, the shift register unit 51, the sampling latch unit 52, the holding latch unit 3, the digital / analog converter unit 54, and the amplifier unit 55 are constituted. do.

The shift register section 51 shifts the horizontal synchronizing signal pulse HSYNC by the source pulse clock HCLK to output the latch clock to the sampling latch section 52.

The sampling latch unit 52 samples and latches digital R, G, and B data for each column line according to the latch clock output from the shift register unit 51.

The holding latch unit 53 simultaneously receives and latches R, G, and B data latched to the sampling latch unit 52 by a load signal LD (Load).

The digital / analog converter unit 54 converts the digital R, G, and B data stored in the holding latch unit 53 into analog R, G, and B data.

The amplifier 55 amplifies the R, G, and B data converted into analog signals to a predetermined width and outputs the data to the panel data lines.

That is, during one horizontal period, the digital, R, G, and B data are converted to analog R, G, and B data after sample & holding, and then amplified and outputted by the current. If the R, G, and B data corresponding to the nth column line are held, the sampling latch unit 52 samples the R, G, and B data corresponding to the n + 1th column line.

6A is a configuration diagram of a gate driver according to a conventional liquid crystal display, and FIG. 6B is an input waveform diagram according to it.

As shown in FIG. 6A, the shift register section 61, the level shifter section 62, and the output buffer section 63 are formed.

The shift register 61 shifts the vertical synchronizing signal pulse VSYNC by the gate pulse clock VCLK to sequentially enable the scan lines.

The level shifter 62 smoothly level shifts a signal applied to the scan line and outputs the signal to the output buffer 63.

Therefore, the plurality of scan lines connected to the output buffer unit 63 are sequentially enabled.

As described above, the conventional liquid crystal display includes a thin film transistor for each data line, and sequentially supplies a driving voltage to the scan line to turn the thin film transistor on and off, and the corresponding data line through the double turn-on thin film transistor. The signal voltage is transmitted to the pixel area to display an image.

However, in the conventional liquid crystal display device as described above, when more pixels are configured to satisfy high resolution and enlargement, the number and size of drivers increase, resulting in an increase in cost, which is not only a packaging but also a driver. It causes new problems such as connection between panel and panel.

The present invention has been made to solve the above-described problems of the prior art, and the gate driver according to the liquid crystal display device which can reduce the cost by enabling the same image representation while reducing the number of data lines to the previous half level The purpose is to provide.

The gate driver according to the liquid crystal display device of the present invention is a gate driver for applying a drive signal to a scan line of a liquid crystal display device including a first substrate and a second substrate and a liquid crystal enclosed therebetween. A shift register unit configured to shift by a gate pulse clock; A logic circuit unit configured to selectively input a plurality of output signals from the output signals of the shift register unit and then output the logic operation; A level shifter unit configured to shift the output of the logic circuit unit to a predetermined level and sequentially output the same; And an output buffer unit sequentially applying the level shifted signal to the scan line.

1 is a cross-sectional structure diagram of a general liquid crystal display device

2 is a schematic configuration diagram of a general liquid crystal display device

3 is a block diagram of a liquid crystal display according to the prior art

4 is a waveform diagram of a driving signal applied to a scanning line of a conventional liquid crystal display device;

5A is a configuration diagram of a source driver according to a conventional liquid crystal display device.

5B is an operation waveform diagram of a source driver according to a conventional LCD.

6A is a block diagram of a gate driver according to a conventional liquid crystal display device.

6b is an operation waveform diagram of a gate driver according to a conventional liquid crystal display device.

7A is a block diagram of a liquid crystal display according to a first embodiment of the present invention.

7B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 7A.

8A is a block diagram of a liquid crystal display according to a second embodiment of the present invention.

8B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 8A;

9A is a block diagram of a liquid crystal display according to a third embodiment of the present invention.

FIG. 9B is a configuration signal waveform diagram applied to a scan line of the liquid crystal display of FIG. 9A; FIG.

10A is a configuration diagram of a liquid crystal display according to a fourth embodiment of the present invention.

FIG. 10B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 10A;

11A is a block diagram of a liquid crystal display according to a fifth embodiment of the present invention.

FIG. 11B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 11A.

12A is a configuration diagram of a liquid crystal display according to a sixth embodiment of the present invention.

12B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 12A.

13A is a configuration diagram of a liquid crystal display according to a seventh embodiment of the present invention.

13B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 13A.

14A is a block diagram of a liquid crystal display according to an eighth embodiment of the present invention.

14B is a waveform diagram of a driving signal applied to a scan line of the liquid crystal display of FIG. 14A.

15A is a configuration diagram of a source driver of a liquid crystal display according to the present invention.

15B is an operation waveform diagram according to FIG. 15A

16A is a configuration diagram showing another embodiment of a source driver of a liquid crystal display of the present invention;

16B is an operation waveform diagram according to FIG. 16A

17A is a block diagram illustrating a gate driver of a liquid crystal display according to the present invention.

17B is an operation waveform diagram according to FIG. 17A

18 is a view showing an image signal writing procedure according to the liquid crystal display of the present invention.

<< Explanation of symbols for main part of drawing >>

71: first switching unit

71a and 71b: first and second thin film transistors

71c: first pixel electrode

73: second switching unit

73a, 73b: third and fourth thin film transistors

73c: second pixel electrode

Hereinafter, a gate driver of the liquid crystal display device of the present invention will be described with reference to the accompanying drawings.

First, the liquid crystal display of the present invention reduces the number of data lines by halving by controlling driving signals applied to two adjacent scanning lines so that image signals can be transmitted to both pixel regions with one data line. There is a characteristic.

7A is a block diagram of a liquid crystal display according to a first embodiment of the present invention.

As shown in Fig. 7A, scan lines G1, G2, ..., Gn-1, Gn are formed in the row direction, and scan lines G1, G2, ..., Gn-1, Data lines D1, D2, .... Dn-1, Dn are formed in the column direction across the Gn).

Data lines D1, D2, ... at the point where scan lines G1, G2, ..., Gn-1, Gn intersect with data lines D1, D2, .... Dn-1, Dn. A first switching unit 71 which transfers an image signal to a pixel area on the left side is formed around Dn-1 and Dn, and an image signal is transmitted to a pixel area on the right side around a data line. 2 switching sections 73 are formed.

The first pixel electrode 71c is connected to the first switching unit 71, and the second pixel electrode 73c is connected to the second switching unit 73.

Here, the first switching unit 71 and the second switching unit 73 is composed of a thin film transistor, the thin film transistor is composed of an N type thin film transistor or a P type thin film transistor.

This will be described in more detail with reference to the 'X' part of FIG. 7A.

The first switching unit 71 configured on the left side of the data line D1 includes a first thin film transistor 71a having a source or a drain connected to the data line D1 and a gate connected to the corresponding scan line G1. The second thin film transistor 71b is connected in series with the first thin film transistor 71a and has a gate connected to the next scan line G2.

A first pixel electrode 71c is connected to the second thin film transistor 71b to selectively transmit an image signal by an on / off operation of the first and second thin film transistors 71a and 71b.

The second switching unit 73 formed on the right side of the data line D1 may include a third thin film transistor 73a having a gate connected to the corresponding scan line G1 and a source or a drain connected to the data line D1. And a fourth thin film transistor 73b connected in series with the third thin film transistor 73a and having a gate connected to the corresponding scan line G1.

Here, the second switching unit 73 may constitute only the third thin film transistor 73a.

In the liquid crystal display according to the first exemplary embodiment of the present invention configured as described above, a process of transferring image signals to the first pixel electrode and the second pixel electrode will be described with reference to the waveform diagram shown in FIG. 7B.

7B illustrates waveforms of driving signals applied to scan lines of the liquid crystal display according to the first exemplary embodiment of the present invention.

As shown in FIG. 7B, one horizontal period is divided into two sections, and in the first section a, pixel regions on the left and right sides of the data lines D1, D2,... The image signal is applied to the image signal, and the image signal is applied only to the right pixel area in the second section (b).

That is, a high signal is applied to the first scan line G1 during one horizontal period, and a second horizontal line (not necessarily exactly 1/2) to the second scan line G2, that is, ( a) The high signal is applied only during the interval and the low signal is applied during the remaining 1/2 horizontal period.

Therefore, while the first scan line G1 and the second scan line G2 are both high, the first and second thin film transistors 71a and 71b and the second switch that constitute the first switching unit 71. The third and fourth thin film transistors 73a and 73b constituting 73 are both turned on to transmit image signals to the first pixel electrode 71c and the second pixel electrode 73c.

Subsequently, when a low signal is applied to the second scan line G2, the second thin film transistor 71b is turned off so that the image signal is not transmitted to the first pixel electrode 71c and the second pixel electrode 73c is not applied. Only the image signal is transmitted.

Thus, by dividing one horizontal period into two sections (a, b), an image signal carried on one data line can be selectively transferred to the pixel electrode at the same time to the left, right, left and right.

As a result, since one data line transfers the image signal to the left and right pixel areas by controlling the driving signal applied to the scan line, the number of data lines can be reduced by half compared to the conventional method, and thus the number of source drivers can be reduced. You can cut it in half.

8A is a configuration diagram of the liquid crystal display according to the second embodiment of the present invention.

As shown in FIG. 8A, the gate connection portions of the first thin film transistor 71a and the second thin film transistor 71b constituting the first switching unit 71 are different from each other in comparison with the first embodiment described above. You can see that.

That is, the first switching unit 71 according to the second embodiment of the present invention may include a first thin film transistor 71a having a source or a drain connected to the data line D1 and a gate connected to the next scan line G2. The second thin film transistor 71b is connected in series with the first thin film transistor 71a and has a gate connected to the corresponding scan line G1.

At this time, the second switching unit 73 is the same as the configuration according to the first embodiment.

In the love display device according to the second exemplary embodiment of the present invention, when the waveform shown in FIG. 8B is applied to the scan line, an image is displayed while moving from the top to the bottom of the liquid crystal panel, and one data line is left and right. The image signal is transferred to the pixel region of the second embodiment so that the number of data lines can also be reduced.

9A is a block diagram of a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 9B is a waveform diagram of a driving signal applied to a scan line.

As shown in FIG. 9A, the third embodiment of the present invention configures the first switching unit 71 on the right side of the data lines D1, D2,.... The switching section 73 is configured on the left side.

That is, in the first and second embodiments of the present invention, the first switching unit 71 is configured on the left side of the data lines D1, D2,... Dn-1, Dn. In the Example, it configured on the right side.

The liquid crystal display according to the third exemplary embodiment of the present invention has a plurality of scan lines G1, G2,... Gn-1, Gn formed in a row direction and are formed in a direction intersecting the scan lines. Formed on the right side of the data lines D1, D2,... Dn-1, Dn and the data lines D1, D2, ... First switching units 71, second switching units 73 formed on the left side of the data lines D1, D2,... Dn-1, Dn, and the first switching unit ( A first pixel electrode 71c connected to 71 and a second pixel electrode 73c connected to the second switching unit 73 are formed.

This will be described in more detail with reference to the 'X' part of FIG. 9A as follows.

The first switching unit 71 is formed on the right side of the data line at the point where the scan line G1 and the data line D1 cross each other, and the first thin film transistor 71a and the first thin film transistor 71a constituting the first switching unit 71. The gate of the second thin film transistor 71b of the two thin film transistors 71b is connected to the next scan line G2.

That is, a first thin film transistor 71a having a source or a drain connected to the data line D1 and a gate connected to the corresponding scan line G1, and connected in series with the first thin film transistor 71a and having a gate next time. The second thin film transistor 71b is connected to the scan line G2.

The second switching unit 73 is formed on the left side of the data line D1 and consists of two thin film transistors.

That is, a third thin film transistor 73a having a source or a drain connected to the data line D1 and a gate connected to the corresponding scan line G1, and a third thin film transistor 73a connected in series with a gate connected to the corresponding scan line G1. 4th thin film transistor 73b connected to the line G1.

Here, the second switching unit 73 can be configured with one thin film transistor.

The liquid crystal display according to the third exemplary embodiment of the present invention configured as described above applies the driving signal as shown in FIG. 9B to the scan line.

As shown in FIG. 9B, a high signal is applied to the first scan line G1 and a high signal is applied only to the second scan hypothesis G2 for the period (a) during one horizontal period. While the low signal is applied.

Therefore, when the high signal is applied to both the first scan line G1 and the second scan line G2, all the thin film transistor frames constituting the first switching unit 71 and the second switching unit 73 are all present. The image signal is turned on to transmit the image signal to the first pixel electrode 71c and the second pixel electrode 73c.

Then, when the high signal is applied to the first scan-in G1 and the low signal is applied to the second scan line G2, the second thin film transistor 71b constituting the first switching unit 71 is turned on. Since the signal is turned off, the image signal is not transmitted to the first pixel electrode 71c, and the image signal is only transmitted to the second pixel electrode 73c.

Through this process, an image is displayed while moving from the top to the bottom of the liquid crystal panel.

10A is a configuration diagram of a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIG. 10B is a waveform diagram of FIG. 10A.

As shown in FIG. 10A, the fourth embodiment of the present invention is a gate connection portion of the first and second thin film transistors 71a and 71b constituting the first switching unit 71 as compared with the third embodiment. Will be configured differently.

That is, in the third embodiment, the gate of the second thin film transistor 71b of the first thin film transistor 71a and the second thin film transistor 71b constituting the first switching unit 71 is the next scan line G2. In the fourth embodiment of the present invention, the gate of the first thin film transistor 71a is configured to be connected to the next scan line G2.

That is, the first switching unit 71 according to the fourth embodiment of the present invention includes a first thin film transistor 71a having a source or a drain connected to the data line D1 and a gate connected to the next scan line G2; The second thin film transistor 71b is connected in series with the first thin film transistor 71a and has a gate connected to the corresponding scan line G2.

Accordingly, when the driving signal is applied to the scan line as shown in FIG. 10B, the image signal may be selectively applied to the left and right sides of the data line D1.

The image is displayed while moving from the top to the bottom of the liquid crystal panel.

Next, FIG. 11A is a block diagram of a liquid crystal display according to a fifth exemplary embodiment of the present invention, and FIG. 11B shows a waveform of a driving signal applied to a scan line.

The fifth embodiment differs from the configuration of the first to fourth embodiments in the position where the thin film transistors constituting the first and second switching units are formed.

That is, in the first to fourth embodiments of the present invention, the data lines D1, D2, ... Dn-1, Dn and the scan lines G1, G2, ... Gn-1, Gn A thin film transistor and a pixel electrode are formed at the intersection of), and are sequentially formed at the intersection with the second, third, and n-1 th scan lines from the intersection with the first scan line.

The thin film transistor and the pixel electrode are not formed at the intersection of the data line and the nth scan line.

However, in the fifth exemplary embodiment of the present invention, the thin film transistor and the pixel electrode are not formed at the point where the first scan line intersects the data line, and the third, fourth, fourth, fourth, and second from the second scan line are not formed. The thin film transistor and the pixel electrode are formed at the intersection of the first scan line.

In the first to fourth embodiments of the present invention, any one of the four thin film transistors formed at the intersection of the scan line and the data line is connected to the next scan line. In the fifth embodiment, four thin film transistors are connected. Any one of them has a structure connected to the previous scan line.

In the case of the fifth embodiment of the present invention, as shown in FIG. 11B, when a driving signal is applied to the scan line, an image is displayed while moving from the lower side to the upper side of the liquid crystal panel.

As shown in Fig. 11B, by applying a drive signal to the scan line by dividing one horizontal period into two sections (a, b), the left and right sides of the data line can be selectively applied to the pixel region. .

This will be described in more detail as follows.

As shown in FIG. 11A, a plurality of scan lines G1, G2, ... Gn-1, Gn are formed in one direction, and data lines D1, D2, .. in a direction crossing each scan line. .Dn-1, Dn) are formed.

The first switching unit 71 is configured on the left side of each data line D1, D2,.... Dn-1, Dn, and the second switching unit 73 is configured on the right side.

The first switching unit 71 and the second switching unit 73 are formed of a thin film transistor, and the thin film transistor is composed of an N type thin film transistor or a P type thin film transistor.

The gate of the second thin film transistor 71b of the first switching unit 71 formed on the left side of the data line D1 is connected to the previous scan line Gn-1, and the gate of the first thin film transistor 71a is It is connected to the scanning line Gn.

The second switching unit 73 formed on the right side of each of the data lines D1, D2,... Dn-1, Dn includes two thin film transistors and the two thin film transistors (third and fourth The gates of the thin film transistors are all connected to the corresponding scan line Gn.

Here, the second switching unit 73 may be configured as one thin film transistor.

This will be described in more detail with reference to the 'X' part of FIG. 11A.

As shown in FIG. 11B, a high signal is applied to the corresponding scan line during one horizontal period, and a high signal is applied only to the previous scan line Gn-1 only during the first period a.

Therefore, in the period in which the scan line Gn and the previous scan line Gn-1 are both high, all the thin film transistors constituting the first and second switching units 71 and 73 are turned on. The image signal is transmitted to the first and second pixel electrodes 71c and 73c.

Subsequently, when the low signal is applied to the previous scan line Gn-1 during the second period b, the second thin film transistor 71b constituting the first switching unit 71 is turned off to be turned off. No image signal is transmitted to the one pixel electrode 71c.

On the other hand, since the second switching unit 73 on the right side of the data line is still turned on, the image signal is transmitted only to the second pixel electrode 73c.

In this way, image signals can be selectively transmitted from the left and right sides around the data line D1, so that the fifth embodiment can also reduce the number of data lines by half.

12A is a configuration diagram of a liquid crystal display according to a sixth embodiment of the present invention, and FIG. 12B is a waveform diagram of a driving signal applied to a scanning line of the liquid crystal display according to the sixth embodiment of the present invention.

In the liquid crystal display device according to the sixth embodiment of the present invention, the gate connection between the first thin film transistor 71a and the second thin film transistor 71b constituting the first switching unit 71 is compared with the fifth embodiment of the present invention. It can be seen that the sites are different.

That is, in the fifth embodiment of the present invention, the gate of the first thin film transistor 71a is connected to the corresponding scan line Gn and the gate of the second thin film transistor 71b is connected to the previous scan line Gn-1. In the sixth embodiment of the present invention, the gate of the first thin film transistor 71a is connected to the previous scan line Gn-1 and the gate of the second thin film transistor 71b is connected to the corresponding scan line Gn.

At this time, the second switching unit 73 is the same as the configuration of the fifth embodiment.

In this way, when the driving signal is applied to the scan line as shown in FIG. 12B, the image signal can be selectively transmitted to the left and right sides of one data line.

As in the fifth embodiment, an image is displayed while moving from the lower side to the upper side of the liquid crystal panel.

13A is a configuration diagram of a liquid crystal display according to a seventh embodiment of the present invention, and FIG. 13B is a waveform diagram of a driving signal applied to a scan line.

As shown in FIG. 13A, the liquid crystal display according to the seventh exemplary embodiment of the present invention includes a first switching unit on the right side and a second switching unit on the left side of the data line.

As shown in FIG. 13A, scan lines G1, G2,..., Gn-1, Gn formed in one direction and data lines D1, D2,... Formed in a direction crossing the scan lines. .Dn-1, Dn), and the first switching unit 71 and the first to be formed on both sides of the data line in the designation where each of the scan line and the data line intersect and controlled by the corresponding scan line and the previous scan line And a second switching unit 73, a first pixel electrode 71c connected to the first switching unit 71, and a second pixel electrode 73c connected to the second switching unit 73. do.

This will be described in more detail with reference to the 'X' part of FIG. 13A as follows.

The first switching unit 71 is in series with the first thin film transistor 71a and the first thin film transistor 71a having a source or a drain connected to the data line D1 and a gate connected to the corresponding scan line Gn. And a second thin film transistor 71b connected to the previous scan line Gn-1.

The second switching unit 73 includes a third thin film transistor 73a having a source or a drain connected to the data line D1 and a gate connected to the corresponding scan line Gn, and the third thin film transistor 73a. The fourth thin film transistor 73b is connected in series and has a gate connected to the corresponding scan line Gn.

The second switching unit 73 may constitute only the third thin film transistor 73a.

When the driving signal is applied to the scan line of the liquid crystal display device configured as described above as shown in FIG. This is the same as the fifth and sixth embodiments described above.

14A is a block diagram of a liquid crystal display according to an eighth embodiment of the present invention, and FIG. 14B is a waveform diagram of a driving signal applied to a scan line.

In the eighth embodiment of the present invention, the gate connection portion of the first thin film transistor 71a and the second thin film transistor 71b constituting the first switching unit differ from each other in the seventh embodiment.

That is, the first switching unit 71 according to the eighth embodiment of the present invention has a first thin film transistor 71a having a source or a drain connected to the data line D1 and a gate connected to the previous scan line Gn-1. And a second thin film transistor 71b connected in series with the first thin film transistor 71a and having a gate connected to the corresponding scan line Gn.

Here, the second switching unit 73 has the same configuration as the second switching unit 73 according to the seventh embodiment.

When the driving signal is applied to the scan line of the liquid crystal display according to the eighth embodiment of the present invention as shown in FIG. 14B, an image is displayed while moving from the lower side to the upper side of the liquid crystal panel.

As described above, the liquid crystal display device of the present invention can reduce the number of data lines by half by allowing one data line to transmit an image signal to the left and right pixel areas.

In this way, the number of data lines can be reduced by half, so that the number of source drivers for applying driving signals to the data lines can be reduced by half.

Hereinafter, a driver for driving the liquid crystal display of the present invention will be described.

First, while the LCD of the present invention can reduce the number of data lines by half, the configuration of the source driver must be changed to satisfy this.

That is, the source driver for driving the liquid crystal display device of the present invention should be able to handle an image signal corresponding to a total of 768 lines if it is 384 lines of the data line.

For this purpose, the source driver can be configured as shown in FIG. 15A.

15A illustrates a first embodiment of a source driver according to the present invention.

The source driver shown in FIG. 15A has doubled the number of cells in the sampling latch portion compared to the source driver of the prior art.

This is because the source driver of the present invention drives 384 data lines, but it must handle substantially 784 image data.

As shown in Fig. 15A, the 384 clock shift register section 151 for shifting the horizontal synchronizing signal pulse by the source pulse clock HCLK to output the latch clock, and the latch clock output from the shift register section 151. Accordingly, the first sampling latch unit 152 for sampling and latching the digital R, G, and B data corresponding to the odd-numbered column line among the 768 column lines, and the digital R, G, and B data corresponding to the even-numbered column line The second sampling latch 152a for sampling and latching the data and the data stored in the first sampling latch unit 152 by the first load signal LDO are received and latched, and the second sampling latch 152a receives the second sampling latch 152a by the second load signal LDE. Odd number of times stored in the holding latch unit 153 for receiving and latching data stored in the sample latch unit 152a and receiving and latching data stored in the second sampling latch unit 152a by the second load signal LDE. Sun in the first column D / A converter unit 154 for converting digital R, G, B data or digital R, G, B data corresponding to even-numbered columns into analog data, and an odd number output from the D / A converter unit 154. The amplification unit 155 is configured to amplify the current of the analog R, G, B data corresponding to the first column or the analog R, G, B data corresponding to the even column.

As described above, the source driver according to the first embodiment of the present invention corresponds to the first sampling latch unit 152 and the even-numbered column lines, which sample and latch image data corresponding to the odd-numbered column lines among the total 768 column lines. And a second sampling latch portion 152a for sampling and latching image data.

That is, by dividing one horizontal period into two sections, the first sampling latch unit 152 receives R, G, and B data corresponding to odd-numbered column lines during about 1/2 horizontal period (not necessarily exactly 1/2). In the second half horizontal period, the second sampling latch unit 152a samples and latches R, G, and B data corresponding to even-numbered column lines.

Therefore, R, G, and B data corresponding to a total of 768 column lines can be sampled.

In this way, the digital image signals which are divided and latched into the first sampling latch unit 152 and the second sampling latch unit 152a are sequentially transmitted to the holding latch unit 153.

That is, the image data stored in the first sampling latch unit 152 by the first load signal LDO is loaded into the holding latch unit 153, and the second sampling latch unit 152a is loaded by the second load signal LD. The image data stored in is loaded into the holding latch unit 153.

The R, G, and G digital data loaded in the holding latch unit 153 are converted into analog signals by the D / A converter unit 154, and the R, G, and B data converted into analog signals are transferred by the amplifier unit 155. The current is amplified.

The R, G, and B data in the odd-numbered columns are applied to the panel during the 1/2 horizontal period, and the R, G, and B data corresponding to the even-numbered column lines are displayed on the panel during the remaining 1/2 horizontal period. Is applied and displayed.

15B illustrates an operation waveform diagram of the source driver of FIG. 15A, in which digital data sampling odd-numbered column lines and digital data sampling even-numbered column lines are loaded into the holding latch unit 153 during one horizontal period. Can be seen.

16A is a block diagram illustrating another embodiment of a source driver according to the present invention, and FIG. 16B is an operation waveform diagram of FIG. 16A.

The source driver shown in Fig. 16A is divided into odd-numbered column lines and even-numbered color lines during one horizontal period to apply sampling liquid crystal parts 162 and 162a, holding latch parts 163 and 162a, and DAC parts 164 and 164a to apply them to the liquid crystal panel. ) And two amplification units 165 and 165a, respectively.

A switching unit 166 is further configured to selectively transfer the outputs of the two amplifiers 165 and 165a to the data line.

Accordingly, the first sampling latch unit 162 samples the image signal corresponding to the odd column line, and the second sampling latch unit 162a samples the image signal corresponding to the even column line.

The image signal corresponding to the odd column line latched by the first sampling latch unit 162 is transferred to the first holding latch unit 163 which stores the image signal corresponding to the odd column line by the load signal LD. Loaded.

The image signal corresponding to the even-numbered column line latched by the second sampling latch unit 162a is also loaded by the second holding latch unit 163a which stores the image signal corresponding to the even-numbered column line by the load signal LD. do.

Thereafter, the digital image signal stored in the first holding latch unit 163 is converted into an analog signal in the first D / A converter unit 164 and the image signal stored in the second holding latch unit 163a is converted into the second D / A. The converter A 164a converts the signal into an analog signal.

Here, the first D / A converter unit 164 converts the digital image signal corresponding to the odd-numbered column into an analog signal, and the second D / A converter unit 164a converts the digital image signal corresponding to the even-numbered column into an analog signal. Convert to a signal.

The image signal corresponding to the odd-numbered and even-numbered columns converted to the analog signal is amplified again by a predetermined width. The amplifying unit also amplifies the analog signal corresponding to the odd-numbered column and the first amplifying unit 165 and the even-numbered column And a second amplifier 165a for amplifying the analog signal corresponding thereto.

Accordingly, an analog image signal corresponding to an odd color line is applied to the data line during the 1/2 horizontal period, and an analog column signal corresponding to the even column line is applied to the data line during the remaining 1/2 horizontal period. An analog image signal is applied to the data line.

Here, the switching unit 166 electrically connects the output of the first amplifying unit 165 and the data lines D1, D2,... During the horizontal period, the output of the second amplifier 165a and the data lines D1, D2, ... Dn-1, Dn are electrically connected.

As described above, the source driver according to another embodiment of the present invention comprises two sampling latch sections, a holding latch section, a D / A converter section, and two amplification sections, so that n image lines correspond to 2 n column lines with n column lines. Can be applied to the liquid crystal panel.

Hereinafter, a gate driver according to the liquid crystal display device of the present invention will be described.

17A shows a first embodiment of a gate driver according to the present invention.

As shown in Fig. 17A, the shift register section 171, the logic circuit section 172, the level shifter section 173, and the output buffer section 174 are large.

The shift register unit 171 shifts the vertical synchronization signal pulse VSYNC by the gate pulse clock VCLK.

The logic circuit unit 172 is composed of three input oragates OR1, OR2,... ORn, and each of the oragates performs logical operation by selectively inputting three outputs of the shift register unit 171.

According to the exemplary embodiment of the present invention, the first OR gate among the three input orifices OR1 receives S1, S3, and S4 of the outputs S1-S2 of the shift resister 171.

The second ora gate OR2 inputs S3, S5 and S6, and the third ora gate OR3 inputs S5, S7 and S8.

Continue to the fourth, fifth, ..... last.

The level shifter 173 sequentially shifts a signal applied to the scan line and outputs the signal to the output buffer unit 174.

Accordingly, the plurality of scan lines connected to the output buffer unit 174 are sequentially enabled.

The operation of the gate driver according to the first embodiment of the present invention will be described with reference to the waveform diagram shown in FIG. 17B.

As shown in FIG. 17B, an output waveform of the first oragate OR2 is applied to the first scan line G1.

In this way, the first scan line is sequentially enabled from the last scan line.

Here, the signals applied to the scan lines G1, G1, ... Gn-1, Gn repeat a high state and a low state for one horizontal period, which is shown in FIGS. 7B-10B. It can be seen that the waveform is the same as the waveform of the driving signal applied to one scan line.

Meanwhile, the input of the OR gate shown in FIG. 17A may be different. For example, S1 and S2 may be input to the first OR gate, and S1, S3 and S4 may be input to the second OR gate. In addition, the third ora gate (OR3) may be input regularly to the last ora gate, such as S3, S5, and S6.

When the input of the OR gate is changed as described above, the driving signal applied to the scan line has waveforms such as G1 ', G2', and G3 'shown in the lower part of FIG.

As described above, according to the liquid crystal display device of the present invention, which constitutes a gate driver and a source driver and transmits an image signal to two pixel regions during one horizontal period, the number of data lines can be reduced, thereby allowing the source driver. Can also be reduced.

In this case, since image signals must be transmitted to two pixel areas during one horizontal period, the line time transmitted to each pixel area is reduced, thereby causing a problem of twice as fast as an analog circuit. do.

This problem is prominent in dot inversion, so that an image signal is written to the pixel electrode in the same manner as in FIG.

18 is a diagram showing an image signal writing procedure according to the liquid crystal display device of the present invention, in which the image signal writing order is in the numerical order shown in FIG.

Since ① and ② are mode (+) polarity signals, ② is precharged at the moment ① is written, so there is no big problem in the charging time even for half a period of one horizontal cycle.

In (3) and (4), since the polarity of the image signal is changed, it takes a long time to charge and discharge. Therefore, the charging and discharging time is reduced by data line precharge or charge sharing of the data line during the blanking time between ①, ② and ③, ④.

On the other hand, ④ is precharged during the writing of ③, so there is no problem in the writing time, but it may be a problem in the writing of ③. Therefore, the high section (a) and the low section ( b) This value can be adjusted to ensure the write time of ③.

As described above, the gate driver of the liquid crystal display device of the present invention has the following effects.

First, since one data line can selectively transmit an image signal to two pixel areas on the left and right sides thereof, the number of data lines can be reduced by half, so the number of gate drivers can be reduced by half.

Second, the size of the device can be reduced and the cost can be reduced at the same time.

Third, since more images can be displayed at the same size, high resolution can be realized.

Claims (3)

A gate driver for applying a driving signal to a scan line of a liquid crystal display device including a first substrate, a second substrate, and a liquid crystal enclosed therebetween, A shift register section for shifting the vertical synchronizing signal pulse by a gate pulse clock; A logic circuit unit configured to selectively input a plurality of output signals from the output signals of the shift register unit and then output the logic operation; A level shifter unit configured to shift the output of the logic circuit unit to a predetermined level and sequentially output the same; And And an output buffer unit for sequentially applying the level shifted signal to the scan line. The gate driver of claim 1, wherein the logic circuit unit comprises OR gates. 3. The gate driver of claim 2, wherein the ora gates are three input ora gates.