KR100279263B1 - SOHI semiconductor device and its manufacturing method - Google Patents

Abstract

The present invention discloses an SOI semiconductor device capable of preventing punch through without increasing the silicon layer concentration of the SOI substrate and a method of manufacturing the same. The disclosed invention provides a SOI substrate in which a handling substrate, a first insulating film, a buffer layer, a second insulating film, and a silicon layer are sequentially stacked, forming a field oxide film on a predetermined portion of the silicon layer, and the buffer layer. Forming a silicon germanium region of a first conductivity type in a predetermined portion of the semiconductor layer, forming a gate electrode in a predetermined portion of the silicon layer, and a source and a drain having a second impurity type in the silicon layers on both sides of the gate electrode Forming a region.

Description

SOHI semiconductor device and its manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon on insulator (SOI) semiconductor device and a method for manufacturing the same, and more particularly, to an SOI semiconductor device and a method for manufacturing the same, which can prevent punch-through without increasing the substrate concentration. .

In general, a silicon on insulator (SOI) substrate is provided as a substrate for forming devices of low power and high speed by preventing RC delay time due to parasitic capacitance of a semiconductor device and leakage current in a junction region.

Such an SOI substrate is manufactured by a device wafer having an insulating film, a method of attaching a handling wafer, and a SIMP (seperation by implanted oxygen) method in which oxygen ions are deeply implanted into a silicon wafer and formed.

As shown in FIG. 1, an SOI substrate 100 composed of a handling substrate 1, an embedded oxide film 2, and a silicon layer 3 on which a device is formed is provided. Here, the silicon layer 3 is a layer doped with impurities of the first conductivity type. A field oxide film 4 for defining an active region in a predetermined portion of the silicon layer 3 is formed by a known LOCOS method. Here, the lower part of the field oxide film 4 is in contact with the buried oxide film 2, so that the active region where the element is formed is completely separated. The gate oxide film 5 and the polysilicon film are sequentially formed on the silicon layer 3, and the gate oxide film 5 and the polysilicon film are patterned to form a gate electrode 6. The source / drain regions 7 are formed by ion implantation of impurities of the second conductivity type in the silicon layer 3 between the gate electrode 6 and the field oxide film 4. Here, the source / drain region 6 is in contact with the buried oxide film 2, so that the junction capacitance and the leakage current do not occur. Thereafter, the interlayer insulating film 8 is deposited to a predetermined thickness over the entire structure, and is etched so that the source / drain regions 7 are exposed, and then a metal wiring 9 is formed in contact with the source / drain regions.

However, as the degree of integration of semiconductor devices increases, a punch through phenomenon caused by a short channel phenomenon occurs in the SOI semiconductor device as well as the bulk semiconductor device.

In order to solve such a punch-through problem, the concentration of the silicon layer in which the semiconductor device is formed is increased in the related art, but when the concentration of the silicon layer is increased in this way, the carrier mobility is significantly reduced. This phenomenon is particularly severe when low voltage is applied.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide an SOI semiconductor device capable of preventing punch through without increasing the silicon layer concentration of the SOI substrate.

Another object of the present invention is to provide a method for manufacturing the SOI semiconductor device.

1 is a cross-sectional view of a typical SOI semiconductor device.

2A to 2H are cross-sectional views of respective processes for explaining a method of manufacturing an SOI device according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10-handling substrate 11-first insulating film

12-epitaxial layer 20-device substrate

21-second insulating film 22-silicon layer

23-Field Oxide 24,29-Resist Pattern

25-High concentration P-type silicon germanium region

26-germanium ion layer 27-gate insulating film

28-gate electrode 30-interlayer insulating film

31-metal wiring

In order to achieve the above object of the present invention, in accordance with one aspect of the present invention, a silicon handling substrate, a first insulating film, a buffer layer, a second insulating film and a silicon layer sequentially stacked SOI substrate, the silicon layer of the SOI substrate A field oxide film formed in a predetermined portion of the SOI substrate to define an active region, a gate electrode formed in a silicon layer active region of the SOI substrate, a source drain region formed in a silicon layer active region on both sides of the gate electrode, and the source, And a silicon germanium region having an impurity type opposite to that of the source and drain regions formed in the buffer layer under the channel formation space between the drain regions.

According to another aspect of the present invention, there is provided a SOI substrate in which a handling substrate, a first insulating film, a buffer layer, a second insulating film, and a silicon layer are sequentially stacked, and forming a field oxide film on a predetermined portion of the silicon layer. Forming a silicon germanium region of a first conductivity type in a predetermined portion of the buffer layer, forming a gate electrode in a predetermined portion of the silicon layer, and forming a second impurity type in the silicon layers on both sides of the gate electrode. Forming a source, a drain region having a.

According to the present invention, punch-through can be prevented by forming a silicon germanium region of a type opposite to the channel controlling the increase of the depletion layer of the drain region under the portion where the channel is formed in the SOI substrate.

Accordingly, it is not necessary to increase the substrate concentration in order to prevent the punch-through phenomenon, so that the mobility of the MOS transistor can be improved.

Further, the mobility can be further improved by ion implantation of germanium ions into the silicon layer so as to trap holes in the substrate (silicon layer) before forming the source and drain regions.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views of respective processes for explaining a method of manufacturing an SOI device according to an embodiment of the present invention.

First, referring to FIG. 2A, a silicon handling substrate 10 in which the first insulating film 11 and the epitaxial silicon layer 12 are sequentially stacked with a thickness of about 90 to 110 GPa, and the second insulating film 21 on the surface thereof, are described. The device substrate 20 formed to the thickness of about 5-15 micrometers is prepared. In this case, a polysilicon layer may be used instead of the epitaxial silicon layer 12.

Subsequently, as shown in FIG. 2B, the epitaxial silicon layer 12 of the handling substrate 10 and the second oxide film 21 are bonded to each other so that the device substrate 20 remains about 5 to 15 mm. Backgrinding is performed to form the silicon layer 22. In this case, the SOI structure may be formed by a junction method as described above, or the SOI structure may be formed by a separation by implanted OXygen (SIMOX) method by implanting oxygen ions in two steps.

Thereafter, as shown in FIG. 2C, the field oxide film 23 is formed in a predetermined portion of the silicon layer 22 using a known LOCOS method, a trench method, or the like. Here, the bottom surface of the field oxide film 23 is formed in contact with the second oxide film 21 to provide a completely insulated and separated element formation layer (silicon layer 22).

Then, as shown in FIG. 2D, a resist pattern 24 is formed over the field oxide film 23 and the silicon layer 22 so that a predetermined portion of the silicon layer 22 is exposed. Thereafter, a high concentration of P-type impurities and germanium (Ge) ions are simultaneously injected into the epitaxial layer 12 under the exposed silicon layer 22 to form a high concentration of P-type silicon germanium region 25. At this time, boron (B) ions are used as the P-type impurities. At this time, the use of boron ions as a P-type impurity is because a stress difference hardly occurs between silicon and germanium. Here, the second insulating film 21 serves to prevent diffusion between the high concentration P-type silicon germanium region 25 and the silicon layer 22, for example, a silicon oxide film, a silicon nitride film, or a silicon oxide film / silicon. It is used as a laminated film of a nitride film.

Then, as illustrated in FIG. 2E, without removing the resist pattern 24, germanium (Ge) ions are ion implanted into the edge portion of the source and drain regions to be formed later. At this time, the germanium ion is preferably tilted by about 7 to 45 ° and ion implanted. Here, the germanium ion layer 26 is implanted to prevent the floating body effect, and the germanium ions form a recombination center to form holes generated in the body, that is, the silicon layer 22. Remove Accordingly, it is possible to improve the mobility characteristics of the MOS transistor to be formed later.

Then, as shown in FIG. 2F, a gate oxide film 27 and a conductor film, for example, a high concentration N-type silicon germanium layer (N ⁺ SiGe: 28) are formed on the silicon layer 22, and then a predetermined portion is formed. Patterning is performed to form a gate electrode.

Then, as shown in FIG. 2G, a resist pattern 29 is formed on the field oxide film 23 and the gate electrode 28 by a known method, and then the source and drain on the exposed silicon layer 22 are formed. The impurity impurities are ion implanted to form the source and drain regions 30.

Then, as shown in FIG. 2H, the resist pattern 29 is removed, and then an interlayer insulating film 31 is formed on the resultant. Subsequently, a predetermined portion of the interlayer insulating layer 31 is etched to expose the gate electrode 28, the source, and the drain region 30 to form a contact hole. Next, the metal wiring 32 is formed to contact the exposed gate electrode 28 and the source and drain regions 30, respectively.

In the present invention having such a configuration, the epitaxial silicon layer 12 is interposed between the buried insulating films 11 and 21 of the SOI substrate, and the high concentration P-type silicon germanium is disposed in the predetermined portion of the epitaxial silicon layer 12. Region 25 is formed. At this time, the high concentration P-type silicon germanium region 25 prevents an increase in the depletion layer of the drain region by increasing a band gap difference between the n-type source and drain region 30. As a result, the punch-through characteristics are improved, so that the doping concentration of the substrate (silicon layer) does not have to be increased, thereby improving mobility characteristics.

Furthermore, by implanting germanium ions into the silicon layer 12 so as to trap holes in the substrate (silicon layer) before forming the source and drain regions, the mobility can be further improved.

As described in detail above, according to the present invention, punch throughs can be prevented by forming a silicon germanium region of a type opposite to the channel controlling the increase of the depletion layer of the drain region under the portion where the channel is formed in the SOI substrate. Can be.

Accordingly, it is not necessary to increase the substrate concentration in order to prevent the punch-through phenomenon, so that the mobility of the MOS transistor can be improved.

Further, the mobility of germanium ions can be improved by ion implantation into the silicon layer so as to trap holes in the substrate (silicon layer) before forming the source and drain regions.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (11)

An SOI substrate in which a silicon handling substrate, a first insulating film, a buffer layer, a second insulating film, and a silicon layer are sequentially stacked; A field oxide film formed on a predetermined portion of a silicon layer of the SOI substrate and defining an active region; A gate electrode formed in the silicon layer active region of the SOI substrate; A source drain region formed in the silicon layer active region on both sides of the gate electrode; And And a silicon germanium region having an impurity type opposite to that of the source and drain regions formed in the buffer layer under the channel formation space between the source and drain regions. The SOI semiconductor device of claim 1, wherein the silicon germanium region contains boron ions. The SOI semiconductor device according to claim 1, wherein the second insulating film is formed of a silicon oxide film, a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film. The SOI semiconductor device of claim 1, wherein the buffer layer is an epitaxial silicon layer or a polysilicon layer. Providing an SOI substrate in which a handling substrate, a first insulating film, a buffer layer, a second insulating film, and a silicon layer are sequentially stacked; Forming a field oxide film on a predetermined portion of the silicon layer; Forming a silicon germanium region of a first conductivity type in a portion of the buffer layer; Forming a gate electrode on a predetermined portion of the silicon layer; And And forming a source and a drain region having a second impurity type in the silicon layers on both sides of the gate electrode. The method of claim 5, wherein the buffer layer is formed of an epitaxial silicon layer or a polysilicon layer. The method of claim 6, wherein the forming of the silicon germanium region of the first impurity type comprises: forming a resist pattern to expose a predetermined portion of the channel region between the source and drain regions; And implanting P-type impurities and germanium ions into an epitaxial silicon layer or a polysilicon layer below the predetermined portion of the exposed channel region. 8. The method of manufacturing a SOI semiconductor device according to claim 7, wherein said P-type impurity is boron ion. 8. The SOI semiconductor according to claim 7, wherein germanium ions are additionally implanted into portions corresponding to edges of the source and drain regions between the forming of the silicon germanium region and the forming of the gate electrode. Method of manufacturing the device. The method of claim 9, wherein in the implanting the germanium ions, the ion implantation is performed by tilting at an angle of 7 to 45 ° without removing the mask pattern exposing the channel predetermined region. Way. The method of claim 5, wherein the providing of the SOI substrate comprises: preparing a device substrate including a handling substrate on which the first insulating layer and the buffer layer are sequentially stacked and a second insulating layer; Bonding the buffer layer of the handling substrate and the second insulating layer of the device substrate to be in contact with each other; And back-grinding the device substrate to a predetermined thickness to form a silicon layer.