KR100275949B1 - A method of fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, after forming a pad metal pattern, a plurality of passivation layers are formed thereon, and then a predetermined passivation layer is formed so that the surface of the passivation layer and the surface of the metal pad are coplanar. The present invention relates to a bump manufacturing method of a semiconductor device in which bumps are formed after removing a portion to remove a step of an upper surface of the bumps, thereby improving product yield and device characteristics.

To this end, the present invention comprises the steps of forming a first metal layer pattern on the semiconductor substrate, sequentially forming a first passivation layer and a second passivation layer on the surface of the semiconductor substrate including the first metal layer pattern, And planarizing the surface, the surface of the second passivation layer, and the surface of the exposed first passivation layer, and forming a second metal layer pattern on the exposed first metal layer pattern.

Description

A method of fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, after forming a pad metal pattern, a plurality of passivation layers are formed thereon, and then a predetermined passivation layer is formed so that the surface of the passivation layer and the surface of the metal pad are coplanar. The present invention relates to a bump manufacturing method of a semiconductor device in which bumps are formed after removing a portion to remove a step of an upper surface of the bumps, thereby improving product yield and device characteristics.

The role of bumps made of gold is to form a thick gold in a pad portion of a wafer in order to proceed with a tape carrier package, which is a kind of package method. Proceed with the package process without using. At this time, the role of the gold bump is the same as the role of wire bonding, but for this purpose, IEL (Inner lead bonding) is performed during the package process. ILB technology is a technology that connects the lead of the film carrier and the electrode of the device through the bump, and TPC technology connects the chip and package leads by simultaneously attaching leads of various shapes designed on the tape onto the chip. It is a technology that connects directly.

Since the gold bump process is one of the pad forming methods, a description of the entire manufacturing process of the semiconductor device will be omitted and the pad forming method will be described.

1A to 1D are cross-sectional views illustrating a method of plating gold bumps during a manufacturing process of a semiconductor device according to the related art.

Referring to FIG. 1A, a first metal layer pattern 1 formed of aluminum by depositing a first metal layer 1 on a surface of a substrate 10 by a sputtering method and then performing a photolithography process again is performed. ) To form a pad.

Forming by depositing an interlayer dielectric layer with the first passivation layer 2 on the entire surface of the substrate 10 including the surface of the first metal layer pattern 1 and then again to open a predetermined portion of the pad A photolithography process is performed to remove a predetermined portion of the first passivation layer 2 to expose the surface of the first metal layer pattern 1. The pad opening mask used at this time is smaller than the mask for forming the first metal layer pattern 1.

Referring to FIG. 1B, a second metal layer 3 is formed on the entire surface of the substrate 10 by sputtering with TiW, and thereafter, seed gold is also sputtered onto the third metal layer ( 4) form.

Referring to FIG. 1C, after the photoresist is applied on the third metal layer 4, a photo process using a mask having a larger exposure area than that of the pad forming mask is performed to form a third metal layer disposed on the upper part including the exposed pad part ( 4) A photoresist pattern 5 that opens the surface is defined.

In FIG. 1D, the fourth metal layer 6 is thickly formed on the third metal layer 4 which is not protected by the photoresist pattern by performing gold plating. The pattern of the fourth metal layer 6 formed at this time becomes a part of the bump, and the center portion thereof is recessed due to the topography of the pad opening portion located at the lower portion thereof, thereby causing a surface step.

Next, the photoresist pattern 5 is removed, and then, the fourth metal layer 6 is etched using an etching mask to remove predetermined portions of the third metal layer 4 and the second metal layer 3, thereby remaining. The bumps 3, 4 and 6 are formed by forming a pattern composed of (3), third (4) and fourth metal layers 6.

Although not shown in the drawings, in the subsequent process, the gold bumps 6 are connected to the leads.

However, in the case of forming the gold bumps according to the above-described prior art, due to the topography difference of the pad portions, the center portions of the gold bumps are formed in recesses in comparison with the corner portions thereof, so that the defective contact during the inspection of the wafer and the IEL process of the TPC. In addition, there is a problem in that the device becomes a defective product due to an increase in contact resistance, and the area that can be in contact with the lead is smaller than that in the case where the topography is good, thereby causing instability of the device and weakening reliability.

Accordingly, an object of the present invention is to expose the exposed pad surface and the passivation layer in order to improve the problems caused by the surface step during the inspection and packaging process of the device during the manufacturing process of the semiconductor device adopting the gold bump process using gold. The present invention provides a method of improving the level difference of the bump upper surface by forming a bump after placing the surface on the same plane.

The present invention for achieving the above object is formed by forming an aluminum layer on a semiconductor substrate and then patterning the aluminum layer to form a first metal layer pattern defined in a predetermined shape, and the semiconductor substrate comprising the first metal layer pattern Forming a first passivation layer and a second passivation layer on the surface by sequentially depositing a passivation film and a nitride film, and forming a surface of the second passivation layer on the second passivation layer corresponding to the upper surface of the first metal layer pattern. Forming an exposed etch mask, removing the second passivation layer of the portion that is not protected by the etch mask, removing the etch mask, remaining with the exposed first passivation layer surface The surface of the first metal layer pattern is etched by etching back the surface of the second passivation layer. Output step of, and comprises the step of forming a bump in the second metal layer pattern on the exposed first metal layer pattern.

According to another aspect of the present invention, there is provided a method of forming an aluminum layer on a semiconductor substrate and then patterning the aluminum layer to form a first metal layer pattern defined in a predetermined shape, and the first metal layer pattern. Depositing a first passivation layer and a second passivation layer on the surface of the semiconductor substrate including a nitride film and a PS film in order, respectively, and forming a sacrificial layer by applying an SG layer on the second passivation layer; And etching back to expose the surface of the first passivation layer on the first metal layer pattern, and remaining on the second passivation layer leaving a first etch mask exposing a top surface of the exposed first passivation layer. Forming the first and second portions of the portion not protected by the first etching mask; Etching back the passivation layer to expose the top surface of the first metal layer pattern and simultaneously planarizing the surface of the first passivation layer and the surface of the first metal layer pattern to be on the same plane; Forming a second metal layer on the exposed first and second passivation layers including a patterned top surface, and exposing a bump forming portion of the top surface of the second metal layer corresponding to the top of the first metal layer pattern; Forming a layer, forming a bump by forming a third metal layer with gold plating only on the exposed second metal layer surface, removing the mask layer, and using the third metal layer as an etching mask. Removing the second metal layer that is not protected by the third metal layer.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 3A to 3E are cross-sectional views illustrating a manufacturing method of a semiconductor device in accordance with another embodiment of the present invention. to be.

2A to 2D are cross-sectional views illustrating a process of forming gold bumps in a pad part of a method of manufacturing a semiconductor device according to the present invention.

In FIG. 2A, a first metal layer pattern 21 made of aluminum is formed by depositing a first metal layer 21 on a surface of a substrate 20 by sputtering and then performing a photolithography process again. Form a pad.

The PSG layer 22 is deposited on the entire surface of the substrate 20 including the surface of the first metal layer pattern 21 with the first passivation layer 22 to form a thin layer, and then again formed thereon. The second passivation layer 23 is formed by depositing the nitride film 23.

The photoresist pattern 24 is defined by applying a photoresist on the second passivation layer 23 and then performing a photolithography process using a mask having a size that sufficiently includes a pad window.

Referring to FIG. 2B, the second passivation layer 23 of the portion not protected by the photoresist pattern 24 is removed by wet etching using phosphoric acid. At this time, the phosphoric acid is planarized by using the etching ratio of the PS layer and the nitride layer to form the first passivation layer and the second passivation layer. Then, the photoresist pattern is removed.

Referring to Figure 2c, one with respect to the PS resin and the nitride film on the exposed surface of the first passivation layer 22 and second passivation layer 23: a blanket etch (blanket etch) having an etching ratio of 1 CHF ₃ / Topo located on the same plane as the surfaces of the first (22) and second passivation layers (23) while exposing the surface of the first metal layer (21), which is finally a pad, by etching with CF ₄ / O ₂ . Form graphy.

Referring to FIG. 2D, a method of sputtering a second metal layer 24 in TiW on a front surface of a substrate 20 including a surface of a first metal layer 21 and a surface of a first 22 and a second passivation layer 23. After the deposition to form a third metal layer (25) by sputtering also seed gold (seed Au) on the (24).

After the photoresist is applied on the third metal layer 25, a photoresist pattern using a mask having a smaller exposure area than that of the pad forming mask is performed to open the surface of the third metal layer 25 located on the exposed pad area. Define (not shown).

Gold plating is performed to form the fourth metal layer 26 with gold so as not to exceed the thickness of the photoresist pattern on the third metal layer 25 which is not protected by the photoresist pattern. The pattern of the fourth metal layer 26 formed at this time becomes a part of the bump, and the center step is removed because of the planarized topography of the pad opening located at the bottom thereof.

Next, the photoresist pattern is removed, followed by etching using the fourth metal layer 26 pattern using an etch mask to remove predetermined portions of the third metal layer 25 and the second metal layer 24 to retain the second (24). The bumps 24, 25, and 26 are formed by forming patterns formed of the third (25) and fourth metal layers (26).

Although not shown in the drawings, in the subsequent process, the gold bumps 26 are connected to the leads.

3A to 3E are cross-sectional views illustrating a process of forming gold bumps in a pad part according to another embodiment of the method of manufacturing a semiconductor device according to the present invention.

In FIG. 3A, a first metal layer pattern 31 formed of aluminum is formed by depositing a first metal layer 31 on a surface of the substrate 30 by a sputtering method and then performing a photolithography process again. To form. At this time, the first metal layer pattern is formed sufficiently smaller than the pad.

The nitride film 32 is formed by depositing the first passivation layer 32 on the entire surface of the substrate 30 including the surface of the first metal layer pattern 31, and then, on the 32, the second passivation layer 33 is formed. ) Is formed by depositing the PS layer 33 relatively thinly compared with the nitride film.

Then, on the second passivation layer 33, a sacrificial layer 34 is applied to the saoji layer 34 to a sufficient thickness.

Referring to FIG. 3B, the etching gas is composed of CHF ₃ / CF ₄ / O ₂ such that the etch ratio of the SG layer 34 as the sacrificial layer and the PS layer 33 as the second passivation layer 33 is about 1: 2. An etch back process is performed to expose the surface of the first passivation layer 32 positioned on the first metal wiring layer 31. As a result of the etch back at this time, the surface step of the upper portion of the first metal wiring layer 31 is minimized.

Then, after the photoresist is applied on the exposed first 32 and second passivation layers 33, a photo process using a mask exposing a wider portion than the first metal wiring layer 31 is performed to perform the first photoresist. The pattern 35 is formed.

Referring to FIG. 3C, the etching ratio of the PSI layer and the nitride layer is about 1: 1 with respect to the second passivation layer 33 and the first passivation layer 32 of the portion not protected by the first photoresist pattern 35. The surface of the first metal layer pattern 31 is exposed by etching using a phosphorus etchant. In this case, the exposed surface of the first metal layer pattern 31 and the surface of the first passivation layer 32 are formed such that a step is hardly generated.

Referring to FIG. 3D, after removing the first photoresist pattern, the second metal layer is disposed on the entire surface of the substrate 30 including the surface of the first metal layer 31 and the surfaces of the first 32 and second passivation layers 33. (36) is deposited by sputtering with TiW, and then a third metal layer (37) is also formed on the 36 by seeding Au.

After the photoresist is applied on the third metal layer 37, a photo process is performed using a mask that sufficiently covers the upper portion of the second passivation layer 33 remaining. A second photoresist pattern 38 that opens the surface of the third metal layer 37 is defined.

Referring to FIG. 3E, the second metal photoresist pattern (gold) is formed on the third metal layer 37 which is not protected by the second photoresist pattern 38 by performing gold plating. It is formed so as not to exceed the thickness of 38). The pattern of the fourth metal layer 38 formed at this time becomes a part of the bump, and the center portion thereof is removed due to the planarized topography of the pad opening located at the bottom thereof. In addition, the width of the fourth metal layer pattern 39 formed at this time sufficiently covers the surface of the first metal layer pattern 31.

Next, the second photoresist pattern 38 is removed, and then the fourth metal layer 39 is etched using an etching mask to remove predetermined portions of the third metal layer 37 and the second metal layer 36. The bumps 36, 37, and 39 are formed by forming a pattern composed of the second 36, the third 37, and the fourth metal layer 39.

Although not shown in the drawings, in the subsequent process, the gold bumps 39 are connected to the leads.

Therefore, the present invention uses gold bumps in the method of electrically connecting the pad portion and the lead, and in forming such gold bumps, the upper surface of the bumps is formed to be flattened, so that the probe test and the TBI's IELB are formed. During the process, it is possible to prevent the occurrence of poor contact with the electrode of the contact hole or the conductor of the via hole, and there is an advantage of improving the reproducibility and reliability of the device by preventing such contact failure.

Claims (9)

Forming an aluminum layer on the semiconductor substrate and then patterning the aluminum layer to form a first metal layer pattern defined in a predetermined shape; Depositing a first passivation layer and a second passivation layer on the surface of the semiconductor substrate including the first metal layer pattern by sequentially depositing a PS layer and a nitride film, respectively; Forming an etch mask on the second passivation layer exposing the surface of the second passivation layer corresponding to the top surface of the first metal layer pattern; Removing the second passivation layer of the portion not protected by the etch mask; Removing the etching mask; Etching the exposed surface of the first passivation layer and the remaining surface of the second passivation layer to expose a surface of the first metal layer pattern to be a bump forming region; Forming a bump on the exposed first metal layer pattern with the second metal layer pattern. The method of claim 1, wherein the second passivation layer is formed to be relatively thicker than the first passivation layer. The method according to claim 1, wherein the removal of the second passivation layer is made of phosphoric acid. The method of claim 1, wherein the etching back is performed using an etchant having an etch ratio of about 1: 1 in the first passivation layer and the second passivation layer. The method of claim 1, wherein the second metal layer pattern is formed of a barrier metal / seed metal / bump metal. Forming an aluminum layer on the semiconductor substrate and then patterning the aluminum layer to form a first metal layer pattern defined in a predetermined shape; Depositing a first passivation layer and a second passivation layer on the surface of the semiconductor substrate including the first metal layer pattern by sequentially depositing a nitride film and a PS layer; Forming a sacrificial layer on the second passivation layer by applying an sedge layer; Etching back to expose the surface of the first passivation layer on the first metal layer pattern; Forming a first etch mask on the remaining second passivation layer exposing the exposed top surface of the first passivation layer; The first and second passivation layers of the portion not protected by the first etching mask are etched back to expose the upper surface of the first metal layer pattern, and at the same time the surface of the first passivation layer and the first metal layer pattern Planarizing the surface to be on the same plane, Forming a second metal layer on the exposed first and second passivation layers comprising an exposed first metal layer pattern upper surface; Forming a mask layer exposing a bump forming portion of the upper surface of the second metal layer corresponding to an upper portion of the first metal layer pattern; Forming a bump by forming a third metal layer by gold plating only on the exposed surface of the second metal layer; Removing the mask layer; Removing the second metal layer that is not protected by the third metal layer by using the third metal layer as an etching mask. The method of claim 6, wherein the etching back is performed using an etching gas including CHF ₃ / CF ₄ / O ₂ such that an etching ratio of the sacrificial layer and the second passivation layer is about 1: 2. . The method of claim 6, wherein the etching back is performed such that an etching ratio between the second passivation layer and the first passivation layer is about 1: 1. The method of claim 6, wherein the second metal layer is formed of a barrier metal / bump seed metal.