KR100275714B1 - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing method Download PDFInfo
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- KR100275714B1 KR100275714B1 KR1019920023812A KR920023812A KR100275714B1 KR 100275714 B1 KR100275714 B1 KR 100275714B1 KR 1019920023812 A KR1019920023812 A KR 1019920023812A KR 920023812 A KR920023812 A KR 920023812A KR 100275714 B1 KR100275714 B1 KR 100275714B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/311—Etching the insulating layers by chemical or physical means
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
본 발명은 반도체장치 및 그 제조방법에 관한 것으로, 특히 반도체기판 상에 제1전도라인이 형성되고 그 위에 절연막이 적층 형성되어 상기 절연막에 도전접촉을 위한 콘택홀을 형성하는 반도체장치의 제조방법에 있어서, 상기 절연막과 식각선택비가 다른 물질층을 형성하는 제1공정, 사진공정을 통해 콘택홀영역이 오픈된 감광막패턴을 형성하는 제2공정, 감광막패턴을 이용하여 상기 물질층과 소정두께의 절연막을 순차로 식각하는 제3공정, 트랜치된 상기 절연막 측벽에 스페이서를 형성하는 제4공정, 잔류절연막을 제거시키는 제5공정을 구비하여 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a semiconductor device in which a first conductive line is formed on a semiconductor substrate and an insulating film is laminated thereon to form contact holes for conductive contact in the insulating film. A first step of forming a material layer having a different etching selectivity from the insulating film, and a second step of forming a photoresist pattern having an open contact hole region through a photo process, and an insulating film having a predetermined thickness using the photoresist pattern. And a fourth step of sequentially etching the fourth step, a fourth step of forming a spacer on the trenched insulating sidewall, and a fifth step of removing the residual insulating film.
따라서 상기한 본 발명의 방법에 의하면 사진공정 한계미만의 작은 크기로 콘택홀을 자기정합적으로 형성할 수 있으며, 공정상 미스얼라인이 발성해도 스페이서 두께만큼의 공정상 마진을 안정적으로 확보할 수 있을 뿐만아니라 콘택홀을 역사다리꼴 모양의 테이퍼형태를 갖게함으로써 단차피복성을 개선시켜 반도체장치의 수율 및 신뢰성을 크게 향상시킬 수 있다.Therefore, according to the method of the present invention, it is possible to form contact holes self-aligning with a small size less than the limit of the photo process, and to secure a process margin equal to the spacer thickness even if misalignment occurs during the process. In addition, the contact hole has a tapered shape of an inverted trapezoidal shape, thereby improving step coverage and greatly improving the yield and reliability of the semiconductor device.
Description
제1도 내지 제5도에 종래의 반도체장치의 콘택홀 형성방법을 제조공정 순서에 따라 단면형상을 도시하였고,1 through 5 illustrate a cross-sectional shape of a conventional method for forming a contact hole in a semiconductor device according to a manufacturing process sequence.
제6도는 종래 반도체장치의 콘택홀의 부분확대 단면도이고,6 is a partially enlarged cross-sectional view of a contact hole of a conventional semiconductor device,
제7도 내지 제11도에는 본 발명의 반도체장치의 콘택홀 형성방법을 제조공정 순서에 따라 단면형상을 도시하고 있으며,7 to 11 illustrate a cross-sectional shape of a method for forming a contact hole in a semiconductor device of the present invention according to a manufacturing process sequence.
제12도는 본 발명의 반도체장치의 콘택홀을 부분적으로 확대한 단면도이고,12 is a partially enlarged cross-sectional view of a contact hole of a semiconductor device of the present invention,
제13도 내지 제16도는 본 발명을 지지하고 식각 마스크층의 프로파일에 따라 에치백공정시 테이퍼식각되는 형상을 실험적으로 나타내고 있는 단면 SEM사진이다.13 to 16 are cross-sectional SEM photographs experimentally showing the shape of the tapered etching during the etch back process according to the profile of the etching mask layer to support the present invention.
본 발명은 반도체장치 및 그 제조방법에 관한 것으로, 특히 도전 콘택(contact)을 위한 콘택홀(contact hole) 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a contact hole for a conductive contact and a method for forming the same.
최근, 반도체장치의 고밀도화로 소자의 집적도가 증가함에 따라 설계치수가 써브미크론(submicron) 이하로 축소되어 소자면적의 축소와 더불어 반도체기판 상에 형성되는 구조물의 입체적 축소가 불가피 해지고 있다. 특히, 설계치수가 0.3㎛-0.4㎛정도의 64Mb DRAM(Dynamic Random Access Memory)장치에서는 콘택홀을 0.5㎛정도의 피쳐사이즈(feature size)로 형성하더라도 마스크(mask)의 미스얼라인(misalign) 등에 의해 주변구조물, 즉 게이트(gate)전극이나 비트라인(bit line) 등의 노출이 빈번하게 발생되어 게이트전극과 스토리지(storage)전극, 비트라인과 스토리지전극의 단락(short)을 유발시키기 때문에 반도체장치의 수율(yield) 및 신뢰성을 크게 저하시키는 요인으로 작용하였다.In recent years, as the integration of devices increases due to the higher density of semiconductor devices, the design dimension is reduced to submicron or less, and the area of the structure formed on the semiconductor substrate is reduced along with the reduction of the device area. Particularly, in a 64 Mb dynamic random access memory (DRAM) device having a design dimension of 0.3 μm to 0.4 μm, even if a contact hole is formed with a feature size of about 0.5 μm, the mask is misaligned. Semiconductor devices are exposed because of frequent exposure of peripheral structures, that is, gate electrodes or bit lines, to cause short-circuits of gate electrodes, storage electrodes, bit lines and storage electrodes. It acted as a factor to greatly reduce the yield (yield) and reliability of the.
따라서, 마스크의 미스얼라인 등에 의한 주변구조물의 노출이 없으면서도 콘택홀의 미소화를 신뢰성 있게 달성하기 위한 많은 방법들이 연구되고 있는데 그 중 한가지가 자기정합적(self-align)으로 형성하는 콘택홀이다.Therefore, many methods for reliably achieving miniaturization of a contact hole without exposure of a peripheral structure by a misalignment of a mask, etc., have been studied. One of them is a contact hole that forms a self-alignment. .
자기정합적인 콘택홀의 형성방법은 주변구조물의 단차를 이용하여 콘택홀을 형성하는 방법으로 주변구조물의 높이, 콘택홀이 형성될 절연물질의 두께 및 식각방법 등에 의해 다양한 크기의 콘택홀을 형성할 수 있기 때문에 고집적화에 의해 미세화되어가는 반도체장치의 실현을 위한 적합한 방법으로 채용되고 있다.The method of forming a self-aligning contact hole is a method of forming a contact hole by using a step of the surrounding structure. The contact hole of various sizes can be formed by the height of the surrounding structure, the thickness of the insulating material on which the contact hole is to be formed, and the etching method. Therefore, it is adopted as a suitable method for realizing a semiconductor device which is miniaturized by high integration.
그러나, DRAM의 경우, 커패시터는 트랜지스터가 형성되어 있는 반도체기판 상에 형성되기 때문에 상기 트랜지스터 또는 임의구조물(예컨대, 비트라인)에 의해 굴곡이 생긴 표면상태에서 상기 커패시터를 제조하기 위한 공정이 진행되는데, 이는 굴곡부의 모서리에 스트링거(sringer) 등의 도전물질 찌꺼기를 형성시키고, 굴곡부에서 도전물질의 물질이동에 의한 단서 유발의 원인이 되어 반도체장치의 전기적 특성을 저하시키는 요인이 되고 있다.However, in the case of DRAM, since the capacitor is formed on the semiconductor substrate on which the transistor is formed, a process for manufacturing the capacitor in the surface state bent by the transistor or an arbitrary structure (for example, a bit line) is performed. This results in the formation of conductive material residues such as stringers at the corners of the bent portion, and causes the clues caused by the movement of the conductive material in the bent portion, thereby deteriorating the electrical characteristics of the semiconductor device.
이와같이 상기한 문제들을 포함하는 종래 반도체장치의 콘택홀의 형성 방법을 첨부도면을 참조하여 살펴보자.As described above, a method of forming a contact hole in a conventional semiconductor device including the above problems will be described with reference to the accompanying drawings.
먼저, 반도체기판(100)상에 제1전도성 라인(예컨대, 폴리실리콘으로 이루어진 게이트라인)(11)을 형성한 후, 그 상부에 일정두께 이상의 절연막(12)을 증착하고(제1도), 감광막을 도포한 다음, 사진 및 현상공정으로 패터닝하여 감광막패턴(13)을 형성한다(제2도).First, a first conductive line (eg, a gate line made of polysilicon) 11 is formed on the semiconductor substrate 100, and then an insulating film 12 having a predetermined thickness or more is deposited thereon (FIG. 1). After the photoresist film is applied, it is patterned by a photograph and a developing process to form the photoresist pattern 13 (FIG. 2).
이어서, 콘택홀의 단차피복성(step coverage)을 개선하기 위해 습식식각 방식으로 상기 절연막(12)을 등방성식각을 하고(제3도), 계속해서 상기 콘택홀 감광막패턴(13)을 이용하여 나머지 절연막을 이방성식각함으로써 반도체기판(100) 및 제1전도라인(11)에 도전접촉을 위한 콘택홀(15)을 형성시키게 된다(제4도). 그 다음, 상기 구조물의 기판 전면에 전도성물질(14)을 증착한 후, 사진식각공정을 통해 제2전도라인을 패터닝함으로써 콘택홀에 도전라인을 접촉시키게 된다(제5도).Subsequently, in order to improve step coverage of the contact hole, the insulating film 12 is isotropically etched by a wet etching method (FIG. 3), and the remaining insulating film is then formed using the contact hole photoresist pattern 13. By anisotropically etching, the contact hole 15 for conductive contact is formed in the semiconductor substrate 100 and the first conductive line 11 (FIG. 4). Then, after depositing the conductive material 14 on the entire surface of the substrate of the structure, the conductive line is brought into contact with the contact hole by patterning the second conductive line through a photolithography process (FIG. 5).
상기한 종래 방식의 콘택홀에 의하면 제6도에서 보는바와 같이 사진공정 한계(A영역) 이하의 작은 크기의 콘택홀(B영역)의 형성이 어렵고(습식식각으로 절연막이 식각된 C, D영역 참조), 미스얼라인(misalign) 발생시에 도전라인 사이의 콘택이 오픈(open), 또는 단락(short)되어 도전접촉의 실패(failure)를 유발할 수 있으며, 콘택홀의 수직한 프로파일(profile)로 인해 단차피복성이 불량해지고 이를 개선하기 위해서는 습식방식에 의한 식각공정이 추가되어야 하므로 제조단가가 증가되는 문제가 있다.According to the conventional contact hole described above, as shown in FIG. 6, it is difficult to form a small contact hole (region B) below the photo process limit (region A) (C and D regions where the insulating film is etched by wet etching). In the event of a misalignment, the contact between the conductive lines may be open or shorted, causing failure of the conductive contact, and due to the vertical profile of the contact hole. Since the step coverage is poor and the etching process by the wet method has to be added in order to improve this, there is a problem that the manufacturing cost is increased.
따라서, 본 발명에서는 상기한 종래기술의 문제점을 해결할 수 있도록 콘택홀의 단면 프로파일 형상을 개선한 반도체장치를 제공한다.Accordingly, the present invention provides a semiconductor device having an improved cross-sectional profile shape of a contact hole in order to solve the above problems of the prior art.
또, 본 발명에서는 상기한 종래기술의 문제점을 해결할 수 있도록 단면 프로파일 형상 및 제조공정이 개선된 반도체장치의 콘택홀 형성방법을 제공하는데 그 목적이 있다.Another object of the present invention is to provide a method for forming a contact hole in a semiconductor device in which a cross-sectional profile shape and a manufacturing process are improved to solve the problems of the prior art.
상기한 목적을 달성하기 위한 본 발명의 바람직한 일실시예는 반도체기판 상에 제1전도라인이 형성되고 그 위에 절연막이 적층 형성되어 상기 절연막에 도전접촉을 위한 콘택홀을 통해서 상기 제1도전라인과 상기 절연막 상기 형성된 제2도전라인을 구비한 반도체장치에 있어서, 상기 콘택홀은 상기 절연막의 표면으로부터 소정의 깊이까지 제1직경을 가진 측벽에 형성된 측벽스페이서로 둘러쌓인 상측공간부와 상기 상측공간부로부터 제1도전라인의 표면까지 상기 상측공간부의 내경과 동일한 제2직경으로부터 역사다리꼴의 테이퍼형상의 측벽으로 둘러쌓인 하측공간부로 이루어지는 것을 특징으로 한다.In accordance with another aspect of the present invention, a first conductive line is formed on a semiconductor substrate, and an insulating film is stacked on the semiconductor substrate so that the first conductive line is connected to the insulating film through a contact hole for conductive contact. In the semiconductor device having the second conductive line formed with the insulating film, the contact hole is an upper space portion and the upper space portion surrounded by a sidewall spacer formed on the sidewall having a first diameter from the surface of the insulating film to a predetermined depth And a lower space portion surrounded by an inverted trapezoidal sidewall from a second diameter equal to the inner diameter of the upper space portion from the surface to the surface of the first conductive line.
상기한 목적을 달성하기 위한 본 발명의 또 다른 일실시예는 반도체기판 상에 제1전도라인이 형성되고 그 위에 절연막이 적층 형성되어 상기 절연막에 도전접촉을 위한 콘택홀을 형성하는 반도체장치의 제조방법에 있어서, 상기 절연막과 식각선택비가 다른 물질층을 형성하는 제1공정, 사진공정을 통해 콘택홀영역이 오픈된 감광막패턴을 형성하는 제2공정, 감광막패턴을 이용하여 상기 물질층과 소정두께의 절연막을 순차로 식각하는 제3공정, 트랜치된 상기 절연막 측벽에 스페이서를 형성하는 제4공정, 잔류절연막을 제거시키는 제5공정을 구비하여 이루어지는 것을 특징으로 한다.Another embodiment of the present invention for achieving the above object is the manufacturing of a semiconductor device in which a first conductive line is formed on a semiconductor substrate and an insulating film is laminated thereon to form contact holes for conductive contact in the insulating film. In the method, the first step of forming a material layer having a different etching selectivity from the insulating film, the second step of forming a photoresist pattern with an open contact hole region through a photo process, and the predetermined thickness using the photoresist pattern And a third step of sequentially etching the insulating film, a fourth step of forming a spacer on the trenched sidewall of the insulating film, and a fifth step of removing the residual insulating film.
상기한 본 발명의 제조방법에 의하면 사진공정 한계미만의 작은 크기로 콘택홀을 자기정합적으로 형성할 수 있으며, 공정상 미스얼라인이 발생해도 스페이서(spacer) 두께만큼의 공정상 마진(margin)을 안정적으로 확보할 수 있을 뿐만 아니라 콘택홀을 역사다리꼴 모양의 테이퍼(taper)형태를 갖게함으로써 단차피복성을 개선할 수 있다.According to the above-described manufacturing method of the present invention, the contact holes can be formed in a self-aligning manner with a small size less than the limit of the photo process, and the process margin as much as the spacer thickness even if misalignment occurs in the process. It is possible not only to secure stably but also to improve the step coverage by giving the contact hole a tapered shape in the inverted trapezoid shape.
이하, 첨부된 도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
제7도 내지 제11도에 본 발명의 반도체장치의 콘택홀 형성방법을 제조공정 순서에 따라 단면형상을 도시하였다.7 to 11 illustrate a cross-sectional shape of a method for forming a contact hole in a semiconductor device of the present invention according to a manufacturing process sequence.
먼저, 제7도를 보면, 반도체기판(200) 상에 제1전도라인(21)을 형성하고, 절연막(22)을 증착한 후에 상기 절연막(22)과의 식각선택비가 큰 물질층으로써 예컨대, 언도프드 폴리실리콘(undoped polysilicon)(23)을 상기 절연막(22)상에 증착시킨다.First, referring to FIG. 7, the first conductive line 21 is formed on the semiconductor substrate 200, the insulating layer 22 is deposited, and then, as the material layer having a large etching selectivity with the insulating layer 22. An undoped polysilicon 23 is deposited on the insulating film 22.
그 다음, 제8도를 참조하면, 상기 언도프드 폴리실리콘(23)상에 감광막을 도포하고, 사진현상공정을 통해 콘택홀 영역을 패터닝하여 감광막패턴(24)을 형성시킨 다음, 상기 감광막패턴(24)을 마스크로 식각시간을 조정하여 상기 절연막(22)을 소정의 깊이만큼 건식방식으로 제1차식각하여 층간트랜치(25)를 형성시킨다. 이때, 상기 제1차 식각시 반도체기판이나 제1전도라인이 노출되어도 후속공정의 일부를 제외하면 본 발명의 목적 달성을 이룰 수 있다. 즉,Next, referring to FIG. 8, a photoresist film is coated on the undoped polysilicon 23, and a contact hole region is patterned through a photolithography process to form a photoresist pattern 24, and then the photoresist pattern ( The etching time is adjusted using 24 as a mask to firstly etch the insulating film 22 in a dry manner to a predetermined depth to form the interlayer trench 25. At this time, even when the semiconductor substrate or the first conductive line is exposed during the first etching, the object of the present invention may be achieved except for a part of the subsequent process. In other words,
그 다음, 제9도를 참조하여 보면, 상기 감광막패턴(24)을 제거하고, 상기 언도프드 폴리실리콘(23)과 식각선택비가 큰 물질층으로 예컨대, 질화막 또는 고온 열산화막을 증착한 후, 상기 언도프드 폴리실리콘(23)을 식각최종점으로 에치백하여 상기 트랜치(25)내에 스페이서(26)를 형성시킨다.Next, referring to FIG. 9, the photoresist layer pattern 24 is removed, and the nitride layer or the high temperature thermal oxide layer is deposited with the undoped polysilicon 23 and the material layer having a high etching selectivity. The undoped polysilicon 23 is etched back to the etch end point to form spacers 26 in the trench 25.
이어서, 제10도를 보면, 상기 언도프드 폴리실리콘(23) 및 스페이서(26)를 이용하여 상기 절연막(22)의 제1차 식각조건과 동일한 제2식각 공정으로 잔류절연막 제거를 위한 전면 에치백을 실시하여 스페이서(26)의 프로파일에 따르는 역사다리꼴의 테이퍼형태의 작은 크기의 콘택홀(27)을 형성시킨다. 이때, 상기 에치백공정에 의한 테이퍼형태의 콘택홀 형상은 제13도 및 제14도의 실험결과에서와 같이 절연막의 제1식각 형상과 스페이서 형성 후의 절연막의 제2식각 형상을 보면 상기 제2식각공정시 테이퍼 프로파일의 전사가 이루어짐을 알 수가 있다. 도면에 기재된 수치의 단위는 ㎛이고, 2500Å 깊이의 트랜치 내부거리를 측정해 본 결과 도면에 나타낸 바와 같이 상단과 하단의 거리차이는 1200Å이고, 6000Å 깊이의 트랜치의 경우에는 상단과 하단의 거리차이가 2200Å으로 하부로 향할수록 트랜치폭이 줄어들어 테이퍼식각되어짐을 알수 있다. 또, 제15도 및 제16도에서 보는 바와같이 식각가스(etch gas)의 조건에 따라 테이퍼 프로파일을 강화(제15도; 식각각스인 H2O2비율을 예컨대, 12sccm으로 증가)시키거나 약화(제16도;식각가스인 H2O2비율을 예컨대, 4sccm으로 감소)시킬 수도 있으나, 구조적으로는 마스크층에 따른 프로파일의 전사에는 변함이 없다.Next, referring to FIG. 10, using the undoped polysilicon 23 and the spacers 26, the front etch back for removing the residual insulating layer may be subjected to the same etching process as the first etching condition of the insulating layer 22. The contact hole 27 of the small size of the inverted trapezoidal taper shape according to the profile of the spacer 26 is formed. In this case, the tapered contact hole shape by the etch back process is the second etching process when the first etching shape of the insulating film and the second etching shape of the insulating film after the spacer are formed, as shown in the experimental results of FIGS. 13 and 14. It can be seen that the transfer of the seam taper profile is achieved. As shown in the figure, the distance difference between the top and the bottom is 1200Å, and in the case of the trench of 6000Å, the distance difference between the top and the bottom is As you go down to 2200 하부, the trench width decreases and you can see that it is tapered etched. Further, as shown in FIGS. 15 and 16, the taper profile may be strengthened according to the conditions of the etch gas (FIG. 15; increasing the ratio of etch H 2 O 2 to, for example, 12 sccm) or Although it is possible to weaken (FIG. 16; reduce the etching gas H 2 O 2 ratio to 4 sccm, for example), structurally, there is no change in the transfer of the profile along the mask layer.
그 다음으로 제11도에서와 같이 도전층으로 예컨대, 폴리실리콘 또는 금속(28)을 상기 구조물의 기판에 증착하여 사진식각 공정으로 제2도전라인을 패턴형성시키면 상기 콘택홀에 원하는 도전접촉을 이룰수 있다.Next, as shown in FIG. 11, when the second conductive line is patterned by using a photolithography process by depositing polysilicon or metal 28 on the substrate of the structure, a desired conductive contact can be achieved in the contact hole. have.
상기한 본 발명을 제12도를 참조하여 상세히 살펴보면, 도전패턴(21) 사이(c영역)에 콘택홀을 형성할 때 a영역만큼의 감광막패턴을 가지고 절연막(22)을 소정의 깊이(d)를 갖도록 제1차 트랜치식각하고, 스페이서(26)를 형성함으로써 이로인해 제2차식각 공정인 에치백공정시 테이퍼형태로 프로파일을 전사시켜 a영역 보다 작은 크기의 콘택홀을 자기정합적으로 만들수 있으며, 상기 감광막패턴 형성을 위한 사진공정시 미스얼라인이 발생할 경우에도 스페이서(26) 두께만큼의 공정마진이 있으므로 제조 실패율을 줄일 수 있다.The present invention will be described in detail with reference to FIG. 12. When forming a contact hole between the conductive patterns 21 (region c), the insulating film 22 has a predetermined depth d having a photoresist pattern corresponding to region a. The first trench is etched so as to have a shape, and the spacer 26 is formed to transfer the profile in a taper shape during the etch back process, which is the second etching process, so that a contact hole having a size smaller than a region can be made self-aligning. In addition, even when a misalignment occurs in the photolithography process for forming the photoresist pattern, a manufacturing failure rate may be reduced since there is a process margin equal to the thickness of the spacer 26.
또, 상기 제8도의 제1차 식각시 반도체기판이나 제1전도라인이 노출되어도 후속공정의 일부를 제외하면 본 발명의 목적 달성을 이룰수 있다. 즉, 상기 본 발명의 콘택홀 제조공정에서 잔류절연막 제거공정을 제외하면 스페이서로 인해 사진공정 한계미만의 작은 크기로 콘택홀을 자기정합적으로 형성할 수 있으며, 공정상 미스얼라인이 발생해도 스페이서 두께만큼의 공정상 마진을 안정적으로 확보할 수 있다.In addition, even if the semiconductor substrate or the first conductive line is exposed during the first etching of FIG. 8, the object of the present invention may be achieved except for a part of the subsequent process. That is, except for the removal of the residual insulating film in the contact hole manufacturing process of the present invention, the contact hole can be formed in a self-aligned manner with a small size less than the limit of the photo process due to the spacer, even if a misalignment occurs in the process, the spacer By the thickness process margin can be secured.
상기한 본발명의 콘택홀 형성방법은 DRAM 반도체장치의 제조에 있어서 트랜지스터의 게이트와 게이트 사이의 데이타(data) 전송라인인 비트라인과 반도체기판과의 다이렉트 콘택(direct contact) 등의 자기정합적인 작은 크기의 콘택홀 형성에 이용할 수 있다.The above-described contact hole forming method of the present invention is a self-aligned small contact such as a direct contact between a bit line, which is a data transfer line between a gate and a gate of a transistor, and a semiconductor substrate in the manufacture of a DRAM semiconductor device. It can be used to form contact holes of size.
따라서 상기한 본 발명의 방법에 의하면 사진공정 한계미만의 작은 크기로 콘택홀을 자기정합적으로 형성할 수 있으며, 공정상 미스얼라인이 발생해도 스페이서 두께만큼의 공정상 마진을 안정적으로 확보할 수 있을 뿐만아니라 콘택홀을 역사다리꼴 모양의 테이퍼형태를 갖게함으로써 단차피복성을 개선시켜 반도체장치의 수율 및 신뢰성을 크게 향상시킬 수 있다.Therefore, according to the method of the present invention, it is possible to form contact holes in a self-aligning manner with a small size less than the limit of the photo process, and to secure process margins as much as the thickness of the spacer even if misalignment occurs in the process. In addition, the contact hole has a tapered shape of an inverted trapezoidal shape, thereby improving step coverage and greatly improving the yield and reliability of the semiconductor device.
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