KR100275269B1 - Inverse-quantizer - Google Patents

Abstract

PURPOSE: An inverse quantization device is provided to be capable of preventing time-delay from being generated in a data processing step. CONSTITUTION: An address generating part(100) receives an end signal(E) to output a read address signal(R) according to a scan type. The first memory part(200) records variable length decoded data by a block unit and outputs the recorded variable length decoded data in response to the read address signal. The multiplication part(300) multiplies a weighted matrix and a quantization step size parameter to output the first multiplication value. The second multiplication part(400) multiplies the variable length decoded data and the first multiplication value. The second memory part(500) records the weighted matrix and outputs the recorded weighted matrix in response to a start signal(S). A buffer part(600) temporarily records the quantization step size parameter and outputs the quantization step size parameter in response to the start signal. A controller(700) starts to count a variable length decoded data number from the first memory part(200) in response to a block start signal(BS). The controller(700) outputs the start signal when the counted value is equal to the first value(T1) and outputs the end signal when the counted value is equal to the second value(T2). The controller(700) is reset when the second value is outputted.

Description

Inverse quantizer

Figure is a block diagram for explaining the operation of the inverse quantizer according to the present invention.

* Explanation of symbols for main parts of the drawings

100: address generator 200: block memory

300: first multiplier 400: second multiplier

500: RAM 600: buffer portion

700: control unit

The present invention relates to a dequantizer, and more particularly, to an inverse quantizer in which time-delay hardly occurs during data processing due to an improved structure.

In a high definition image system, decoding is to restore the encoded image data received from the coding stage to the original image data through a series of processes. Here, a series of processes are inverse processes of encoding, specifically, variable length decoding (VLD), run length decoding (RLD), and inverse quantization (IQ).

In this case, the inverse quantization is a multiplication process of two steps. The first step is a multiplication step of a predetermined weighted matrix and a quantization step size parameter (QS), and the second step is a first step. The multiplication value obtained from the step and the variable length decoded data. Here, the quantization step size parameter (QS) is transmitted together with the image data encoded as additional information from the encoding end. In the decoding end, the transmitted quantization step size parameter (QS) is temporarily recorded in the buffer unit, and then at a constant rate. Output and multiply by weight matrix.

However, in general, the multiplication process is a very complicated process, and according to the internal structure of the multiplier, some time-delay inevitably occurs in the data processing. Therefore, the conventional inverse quantizer has to multiply the variable length decoded data with the value obtained from the first multiplication step in the second multiplication step. Therefore, when the weight matrix, the quantization step size parameter (QS), and the variable-length decoded data are provided at the same point in time, the time delay occurring in the first multiplication step delays the start of performing the second multiplication step, and thus inverse quantization as a whole. There has been a big problem with the process causing serious time delays.

Accordingly, an object of the present invention is to provide an inverse quantizer in which time-delay hardly occurs during data processing due to the improved structure.

In order to achieve the above object, the inverse quantizer for dequantizing and outputting variable length decoded data inputted in units of blocks, starting with the block start signal BS, is an end signal. In response to (E), an address generator for outputting a read address signal (R) according to a preset scan method, the variable length decoded data is received and written in block units, and a read provided from the address generator is provided. In response to an address signal R, a first memory unit for outputting the recorded variable length decoded data, a predetermined weight matrix and a quantization step size parameter (QS) are received. A multiplier for multiplying and as a result outputting a first multiplication value, variable length decoded data provided from the first memory section, and A second multiplier for multiplying and outputting a first multiplication value provided from a first multiplier; and a second weighting unit for recording the predetermined weight matrix and outputting the recorded weight matrix in response to a start signal S A memory unit and a buffer unit for receiving and temporarily recording the quantization step size parameter QS transmitted from the encoding end, and outputting the recorded quantization step size parameter QS in response to the start signal S. And, in response to the block start signal BS, counting of the variable length decoded data number input to the first memory unit 200 is started, counting is continued, and the counting value is the first preset value T1. Outputs a start signal (S) when it is equal to, and outputs and terminates the reset signal (E) when the counting value is equal to the second preset value (T2). NXN data, where N is any positive integer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram schematically illustrating an operation of an inverse quantizer according to an exemplary embodiment of the present invention. The address generator 100, the block memory 200, the first multiplier 300, and the second multiplier 400 are shown in FIG. , The RAM 500, the buffer unit 600, and the controller 700.

The address generator 100 outputs the read address signal R according to a preset scan method in response to the end signal E. FIG.

The block memory unit 200 writes the variable length decoded data provided from the variable length decoding unit (not shown) in units of blocks, and in response to the input read address signal R, the recorded variable length decoded data is decoded. Print the data.

The first multiplier 300 multiplies a weighted matrix provided from the RAM 500 and a quantization step size parameter (QS :) provided from the buffer unit 600, As a result, the first multiplication value is output.

The second multiplier 400 multiplies the variable-length decoded data provided from the block memory 200 and the first multiplied value provided from the first multiplier 300 to output the multiplied value.

The RAM 500 records a preset weight matrix, and outputs the recorded weight matrix in response to the start signal S. FIG.

The buffer unit 600 receives and temporarily records the quantization step site parameter QS transmitted from the encoding end, and outputs the recorded quantization step site parameter QS in response to the start signal S.

In response to the block start signal BS, the control unit 700 starts counting the variable length decoded data number input to the block memory unit 200, continues counting, and the counting value is the first preset value T1. Output signal (S) when the same value as), and outputs and resets the start signal (S) when the counting value becomes equal to the second preset value (T2).

The blocks used below are exemplarily composed of 8 × 8 data.

The operation of the inverse quantizer according to the present invention configured as described above will be described in more detail.

The variable length decoding unit (not shown) carries a block start signal BS at the front and outputs variable length decoded data in units of blocks.

At this time, in response to the block start signal BS, the control unit 700 starts counting the variable length decoded data number input to the block memory unit 200, and the block memory unit 200 inputs the variable length decoding. Recorded data sequentially.

Meanwhile, the controller 700 continues counting and stops counting when the counting value is equal to the first preset value T1 and outputs the start signal S to the RAM 500 and the buffer unit 600. Here, the preset value T for determining the time point at which the control unit 700 generates the start signal S is considered in consideration of a time delay occurring in the multiplication process in the first multiplier 300. , Is calculated as in the following equation (1).

T = M-D

Here, M is a time taken to write all of the 8X8 block data in the block memory unit 200, and D is a time delay that occurs during the multiplication process in the first multiplication unit 300.

For example, if the time taken for all 8 × 8 block data to be written to the block memory unit 200 is 64 clocks, and the time delay occurring in the first multiplier 300 is 3 clocks, the control unit 700 may determine that the counting value is equal to. When 61, the start signal S is output.

In addition, the control unit 700 outputs an end signal E to the address generator 100 when the counting value becomes equal to the second preset value T2, and the second preset value T2 is the block memory unit 200. The time taken for all 8x8 block data to be written is equal to 64 clocks. Therefore, when the counting value is 64, the control unit 700 outputs the end signal (E). Subsequently, the RAM 500 and the buffer unit 600 output the weight matrix and the quantization step size parameter QS, which have been recorded, to the first multiplier 300 in response to the start signal S, respectively.

The first multiplier 300 outputs the first multiplication value obtained by multiplying the input weight matrix by the quantization step size parameter QS to the second multiplier 300.

On the other hand, after all 8x8 block data has been written, the block memory unit 200 responds to the read address signal R provided from the address generator 100 to multiply the block data recorded by the second multiplier 400. ) Here, the address generator 100 outputs the read address signal R according to a preset scan method in response to the end signal E provided from the controller 700.

Subsequently, the second multiplier 400 outputs a multiplication value obtained by multiplying the first multiplier value provided from the first multiplier 300 by the block data provided from the block memory unit 200.

Therefore, the start of the multiplication process in the second multiplier 400 is not delayed due to the time delay occurring in the first multiplier 300.

The inverse quantizer according to the present invention by the above-described process has the great advantage that the time-delay hardly occurs in the data processing process by the improved structure.

Claims (3)

In the inverse quantizer which dequantizes and outputs variable length decoded data input in units of blocks starting with the block start signal BS, An address generator 100 for outputting a read address signal R according to a preset scan method in response to the end signal E; A first memory that receives the variable length decoded data and writes the data in blocks, and outputs the recorded variable length decoded data in response to a read address signal R provided from the address generator 100. A part 200; A first multiplier 300 that receives a predetermined weighted matrix and a quantization step size parameter (QS) and multiplies the result, and outputs a first multiplied value as a result; A second multiplier 400 multiplying the variable length decoded data provided from the first memory unit 200 and a first multiplier value provided from the first multiplier 300; A second memory unit 500 for recording the predetermined weight matrix and outputting the recorded weight matrix in response to a start signal S; A buffer unit 600 which receives and temporarily records the quantization step size parameter QS transmitted from an encoding end, and outputs the recorded quantization step size parameter QS in response to a start signal S; ; In response to the block start signal BS, the variable length decoded data number counting input to the first memory unit 200 is started, counting is continued, and the counting value is set to the first preset value T1. A control unit 700 which outputs a start signal S when it is the same, and outputs and resets an end signal E when the counting value becomes equal to the second preset value T2, wherein the block includes NXN data. And N is an arbitrary positive integer. The method of claim 1, The first preset value T1 for determining a time point at which the control unit 700 generates the start signal S is represented by the following equation. T = M-D M is a time taken for all of one block data to be written to the first memory unit 200, and D is a time delay occurring in the multiplication process in the first multiplication unit 300. Inverse quantizer characterized in that. The method of claim 1, The second preset value T2 for determining when the control unit 700 generates the end signal E is the same value as the time taken for all of the block data to be written in the first memory unit 200. Inverse quantizer.