KR100272276B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to form a repeatable shallow junction region, by forming a transition metal silicide layer of a uniform thickness in a region for the shallow junction region regardless of variation of deposition thickness of a transition metal layer. CONSTITUTION: A field oxide layer(21) is formed on a semiconductor substrate(20). A gate oxide layer(22) and a gate(23) having an insulating on its upper portion are formed on the substrate having the field oxide layer. An oxide layer is deposited on the entire surface. The oxide layer is anisotropically blanket-etched to expose the substrate and to form an oxide layer spacer(25) on both sidewalls of the gate. A silicon layer is formed on the exposed substrate. The insulating layer is removed, and a transition metal layer is formed on the entire surface. The transition metal is reacted with silicon to form a transition metal silicide layer in the upper portion of the gate and on the substrate at both sides of the gate. The unreacted transition metal layer is removed. A predetermined cap oxide layer of a constant thickness is formed on the resultant structure. The first impurity ions are implanted into the transition metal silicide layer at both sides of the gate. The second impurity ions are implanted into the substrate under the transition metal silicide layer at both sides of the gate. A heat treatment is performed at a predetermined temperature to diffuse the implanted first and second impurity ions.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a silicide layer to form a shallow junction region.

With the high integration of semiconductor devices, research has continued on devices capable of maintaining reliability under high current while shortening the channel length between the source and the drain of the MOS device. On the other hand, in a MOS device with a short channel length, as the drain voltage increases, punch-through occurs rather than pinch-off, so determining the electrical potential and the electric field in the channel determines the characteristics of the device. It will depend. In order to prevent device deterioration due to such a short channel effect, a method of forming a shallow junction depth between the source and the drain has been proposed. That is, since the side diffusion is proportional to the junction depth, the short channel effect is reduced by forming the junction depth shallower.

The shallow junction is formed by low energy ion implantation or diffusion using solid diffusion sources such as spin on source, polysilicon and silicide. Among these methods, a method of forming a shallow junction using silicide has been proposed in US Patent Application No. 5,268,317, in which a transition metal layer is deposited on the entire surface of the substrate after the formation of the gate and subjected to heat treatment to form the junction region on both sides of the gate. After the transition metal-silicide layer is formed on the substrate, As ion is implanted twice into the silicide layer. First, As ions are implanted only into the silicide layer at low ion implantation energy, and then ion implanted to penetrate the silicide layer at high ion implantation energy. Then, a predetermined heat treatment was performed to form a junction region of a high concentration impurity region and a low concentration impurity region having a shallow junction depth.

However, it is difficult to accurately control the deposition thickness when depositing the transition metal layer for forming the transition metal silicide layer. In other words, in the deposition of the transition metal layer, when a semiconductor device performing a single wafer processing processes several wafers, a uniformity difference with respect to the deposition thickness of the wafer to the wafer is generated by about 3 to 10%. Due to the thickness change of the transition metal silicide layer due to the change in the thickness of the transition metal layer, the depth of ion implantation is severely changed in the second ion implantation process of As ions. As a result, it is difficult to form a shallow junction region reproducibly.

Accordingly, the present invention has been made to solve the above-mentioned problems, and the thickness of the transition metal-silicide layer in the region where the shallow junction region is to be formed uniformly, regardless of the deposition thickness change of the transition metal layer, is reproducibly shallow. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a junction region.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a shallow junction region in accordance with an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

20: semiconductor substrate 21: field oxide film

22: gate oxide film 23: gate

24 nitride film 25 oxide film spacer

26 silicon film 27 titanium film

28 titanium-silicide layer 29 cap oxide film

30: non-member 31: personnel

32: low concentration impurity region 33: high concentration impurity region

In the semiconductor device manufacturing method according to the present invention for achieving the above object, a gate oxide film is interposed on a semiconductor substrate in which an active region is defined by an element isolation film, a predetermined protective insulating film is formed on the upper side, and oxide films on both sidewalls thereof. Forming a gate made of a doped polysilicon film having a spacer formed thereon; Forming a silicon film on the substrate on both sides of the spacer; Removing a protective insulating layer on the gate; Forming a transition metal film on the entire surface of the substrate; Reacting the transition metal with silicon to form a transition metal-silicide layer on the substrate above the gate and on both sides of the gate; Removing the unreacted transition metal film; And forming a junction region comprising a high concentration impurity region and a low concentration impurity region on the substrate on both sides of the gate and having a shallow junction depth.

Here, the silicon film may be selectively formed by using a vapor phase epitaxial growth method, and the vapor phase epitaxial growth method may be performed by using one gas selected from SiH ₄ , SiH ₂ Cl ₂ , SiHCl ₃ , and SiH ₄ . Proceed to substitution reaction. In addition, impurities are not implanted when the silicon film is grown by the vapor phase epitaxial growth method.

The transition metal film is a titanium film formed to a thickness of 100 to 300Å, the transition metal-silicide layer is formed to a thickness of 300 to 700Å by heat treatment at a temperature of 600 to 800 ℃.

The forming of the junction region may include forming a predetermined cap oxide film on the entire surface of the substrate after the transition metal film is removed; Implanting impurity ions into only the transition metal-silicide layers on both sides of the gate; Implanting impurity ions into the substrate under the transition metal-silicide layer on both sides of the gate; And diffusing the impurity ions.

According to the present invention described above, an epitaxial silicon film is selectively formed in a region where a shallow junction is to be formed, and a titanium silicide layer is formed from the silicon film and the titanium film, thereby irrespective of the thickness change generated during deposition of the titanium film. A titanium silicide film having a uniform thickness of can be easily formed. Accordingly, impurity ions that penetrate the titanium silicide film and are injected into the substrate can be easily implanted into a predetermined region of the substrate without changing the ion implantation depth, thereby making it possible to form a shallow junction region reproducibly and to improve the reliability of the semiconductor device. Can improve

(Example)

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

1A to 1F are cross-sectional views illustrating a method of manufacturing a MOS transistor having a shallow junction according to an embodiment of the present invention.

Referring to FIG. 1A, a field oxide film 21 for device isolation is formed on a semiconductor substrate 20 by a known LOCOS (LOCal Oxidation of Silicon) method to define an active region of a semiconductor device. Here, the semiconductor substrate 20 includes silicon. Then, the gate oxide film 22, the doped polysilicon film and the nitride film are deposited and patterned to form a gate 23 having the nitride film 24 formed thereon. The nitride film 23 protects the upper portion of the gate 23 during the subsequent epitaxial process. Then, an oxide film is deposited on the entire surface of the substrate, and the oxide film is anisotropically blanket-etched to expose the semiconductor substrate 1, thereby forming oxide spacers 25 on both sidewalls of the gate 23. A silicon film 26 is selectively formed on the exposed semiconductor substrate 1 by vapor phase epitaxial growth. At this time, in the vapor phase epitaxial growth method, the silicon film 26 is grown by substitution reaction of hydrogen atoms using one gas selected from SiH ₄ , SiH ₂ Cl ₂ , SiHCl ₃ , and SiH ₄ . In addition, when the silicon film 26 is grown by the vapor phase epitaxial growth method, impurities are not implanted to facilitate the formation of a shallow junction in consideration of a high temperature heat treatment for forming a silicide layer.

Referring to FIG. 1B, the nitride film 24 is removed with a phosphate solution at a temperature of 150 to 175 ° C., and a transition metal, preferably a titanium (Ti) film 27, is formed on the entire surface of the substrate to a thickness of about 100 to 300 μm. Heat treatment is carried out at a temperature of 600 to 800 ℃. At this time, by reaction of Ti + 2Si → TiSi ₂ , the silicon atoms of the silicon film 26 move to the titanium film 27, and the interface between the silicon film 26 and the titanium film 27, the gate 23 and the titanium At the interface of the film 27, silicon atoms and titanium atoms react with each other. Accordingly, a titanium silicide layer 28 having a thickness of 300 to 700 Å is formed on the substrates on the gate 23 and on both sides of the gate 23. In addition, the titanium silicide layer 28 is formed by the silicon film 26 to a desired uniform thickness irrespective of the thickness of the titanium film 27. Then, the titanium film 27 remaining unreacted on the field oxide film 21 and the oxide film spacer 25 is removed with a mixed solution of NH ₄ OH and H ₂ O ₂ . The structure at this time is as shown in Figure 1c.

Referring to FIG. 1D, a predetermined cap oxide film 29 is formed to a thickness of 20 to 50 microseconds on the structure of FIG. 1C. Then, arsenic (As) atoms 30 are implanted into the titanium silicide layer 28 on both sides of the gate 23 at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm 2 and a predetermined ion implantation energy. . At this time, the ion implantation is performed at a relatively low ion implantation energy, preferably 15 to 30 KeV, so that only the titanium silicide layer 28 is implanted.

Referring to FIG. 1E, phosphorus (P) atoms 31 are implanted into the semiconductor substrate 20 at both sides of the gate 23 at a concentration of 1 × 10 ¹³ to 1 × 10 ¹⁵ atoms / cm 2 and a predetermined ion implantation energy. do. At this time, the ion implantation is performed at a relatively high ion implantation energy, preferably 100 to 140 KeV, so that the phosphor 31 is injected into the semiconductor substrate 20 by passing through the titanium silicide layer 28. That is, by the titanium silicide layer 28 having a uniform thickness, the personnel 31 are easily injected into the predetermined region of the semiconductor substrate 20 without changing the ion implantation depth. Then, in order to diffuse the implanted arsenic atom 30 and the personnel 31, heat treatment is performed at a temperature of 850 to 950 ℃, as shown in Figure 1f, a low concentration impurity region having a shallow junction depth ( 32) and a junction region of the high concentration impurity region 33 is formed.

According to the above embodiment, an epitaxial silicon film is selectively formed in a region where a shallow junction is to be formed, and a titanium silicide layer is formed from the silicon film and the titanium film, thereby irrespective of the thickness change generated during the deposition of the titanium film. A titanium silicide film having a uniform thickness of can be easily formed. Accordingly, impurity ions that penetrate the titanium silicide film and are injected into the substrate can be easily implanted into a predetermined region of the substrate without changing the ion implantation depth, thereby making it possible to form a shallow junction region reproducibly and to improve the reliability of the semiconductor device. Can be improved.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (15)

Forming a gate oxide film and a gate having an insulating film formed thereon on the semiconductor substrate on which the field oxide film is formed; Depositing an oxide film on the entire surface of the substrate and anisotropic blankcat etching the oxide film to expose the substrate to form oxide spacers on both sidewalls of the gate; Forming a silicon film on the exposed semiconductor substrate; Forming a transition metal film on the entire surface of the substrate after removing the insulating film; Reacting the transition metal with silicon to form a transition metal silicide layer on the substrate above the gate and on both sides of the gate; Removing the unreacted transition metal film; Forming a predetermined thickness of the cap oxide film on the resultant material; Implanting predetermined first impurity ions into the transition metal silicide layers on both sides of the gate; Implanting second impurity ions into the substrate under the transition metal silicide layer on both sides of the gate; And heat treatment at a predetermined temperature to diffuse the implanted first and second impurity ions. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon film is selectively formed using a vapor phase epitaxial growth method. The semiconductor device according to claim 2, wherein the vapor phase epitaxial growth method is performed by a substitution reaction of hydrogen atoms using one gas selected from SiH ₄ , SiH ₂ Cl ₂ , SiHCl ₃ , and SiH ₄ . Manufacturing method. The method of manufacturing a semiconductor device according to claim 2, wherein impurity is not injected during growth of the silicon film by the vapor phase epitaxial growth method. The method of manufacturing a semiconductor device according to claim 1, wherein the transition metal is titanium. The method of claim 5, The titanium is a manufacturing method of a semiconductor device, characterized in that formed in a thickness of 100 to 300Å. The method of claim 1, The forming of the transition metal silicide layer is a method of manufacturing a semiconductor device, characterized in that the heat treatment at a temperature of 600 to 800 ℃. 8. The method of claim 7, wherein the transition metal-silicide layer is formed to a thickness of 300 to 700 GPa. The method of claim 1, The step of removing the unreacted transition metal is a semiconductor device manufacturing method, characterized in that the removal with a mixed solution of NH 4 OH and H 2 O 2. The method of claim 1, And the cap oxide film is formed to a thickness of 20 to 50 GPa. The method of claim 1, And the first impurity ion implants arsenic atoms at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm 2 and an energy of 15 to 30 KeV. The method of claim 1, And the second impurity ions are implanted with phosphorus atoms at a concentration of 1 × 10 ¹³ to 1 × 10 ¹⁵ atoms / cm 2 and energy of 100 to 140 KeV. The method of claim 1, The heat treatment is a method of manufacturing a semiconductor device, characterized in that the heat treatment at a temperature of 850 to 950 ℃. The method of claim 1, And said insulating film is a nitride film. The method of claim 15, The removing of the insulating film is a method for manufacturing a semiconductor device, characterized in that for removing with a pulling solution of 150 to 175 ℃ temperature.

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