KR100270798B1 - Video dccompression - Google Patents

Abstract

The present invention relates to an MPEG video decommissioning method and apparatus, which utilizes multiple stages interconnected by a two-wire interface equipped as a pipeline processing machine. The control token and the DATA token move on a single two-wire interface to move control and data in token form. A token decode circuit is arranged at any stage to recognize any token as a control token fixed to the stage and to convey an unrecognized control token along the pipeline. The reconstruction processing circuitry is disposed at the selected stage and responds to the recognized control token to reconstruct such stage to adjust the identified DATA token. A wide variety of unique supporting subsystem circuits and processing techniques have been disclosed and used to perform the system, including memory addressing, transform data using common processing blocks, time synchronization, asynchronous swing buffering, video information storage, parallel Huffman decoders, and more. Included.

Description

System for decoding a plurality of MPEG audio and video signals

1 is a data flow diagram through a preferred embodiment of the present invention.

2 is an illustration of a 13 bit word used to address 8 bit data in 64 x 32 RAM.

3 is a functional block diagram of a register file in the present invention.

4 is a data flow diagram of the register file shown in FIG.

5 is a block diagram illustrating decryption of a register file address in accordance with the present invention.

6 is a block diagram of a machine in microcoded state in accordance with the present invention.

7 is a fixed-width word diagram in accordance with the present invention used to address and to have address fields, alternate fields and alternate headers.

8 is a block diagram of an example of a computational core in accordance with the present invention.

9 shows the basic steps of a method for executing IDCT of input data according to the present invention.

10 is a block diagram showing a combined, simplified two-step design of IDCT in accordance with the present invention.

FIG. 11 is a simplified block diagram of integrated circuits that make up the major system elements of IDCT shown in FIG.

12 (a) and 12 (b) together show a block diagram of a preprocessing circuit according to one of the main system elements; These figures are referred to in conjunction with FIG. 12 for ease of explanation.

13 (a) and 13 (b) are time diagrams showing the relationship between timing and control signals in the proposed CT's IDCT system.

14 (a) and 14 (b) together show a block diagram of a common processing circuit in an IDCT system; These figures are referred to in conjunction with FIG. 14 for ease of explanation.

15 (a) and 15 (b) and 15 (c) together are referred to in conjunction with FIG. 15 as a block diagram of a subsequent processing circuit according to another main element of the system.

16 is a block diagram in accordance with the present invention showing IDCT with pair data flow and pre-RAM and improved buffer.

FIG. 17 is a block diagram showing more details of the 1-D IDCT system shown in FIG.

FIG. 18 is a block diagram showing more details of the conversion system shown in FIG. 17. FIG.

FIG. 19 is a block diagram showing more details of the input buffer shown in FIG. 18. FIG.

20 is a simplified block diagram of a preceding circuit PREC in accordance with the present invention.

21 is a block diagram showing a common processing circuit CBLK shown in IDCT.

22 is a block diagram of subsequent processing circuit POSTC.

FIG. 23 is another illustration of a processing circuit after that shown in FIG. 22;

24 is a block diagram illustrating an overall saturated block in accordance with the present invention.

25 is a block diagram of an output buffer in the present invention.

26 is a block diagram of a control shift register in accordance with the present invention.

27 is a block diagram of a control shift register decoder in the present invention.

28 is a diagram for a control shift register and an input control buffer.

29 is a control circuit diagram for a T2 data flow.

30 is a data diagram at the counter for the T1 data flow.

Figure 31 is a data diagram at the counter for the T2 data flow in the present invention.

32 is a timing diagram illustrating initialization and associated circuitry of IDCT.

33 is a timing diagram showing interleaving of T1 and T2 data.

34 is a timing diagram illustrating the loss and recovery of T2 data.

35 is a timing diagram illustrating the outflow process of IDCT and related circuitry in the present invention.

36 shows the beginning of a system according to the invention.

FIG. 37 illustrates loss and recovery at an early stage of interleaving T1 and T2 data. FIG.

FIG. 38 shows another presented embodiment of the IDCT system shown in FIGS. 16-37.

FIG. 39 illustrates that the MPEG information flow is demultiplexed into an initial flow including data and time stamp information in accordance with the present invention.

40 illustrates a first embodiment of a time stamp error determination and time synchronization system of an initial flow in accordance with the present invention.

41 is a second embodiment of a time stamp error determination and time synchronization system of an initial flow in accordance with the present invention.

42 is a third embodiment of a time stamp error determination and time synchronization system of an initial flow in accordance with the present invention.

Figure 43 illustrates a first embodiment of a video time stamp error determination and time synchronization system in accordance with the present invention.

44 is a second embodiment of a video time stamp error determination and time synchronization system in accordance with the present invention.

45 is a second embodiment of the video time stamp error determination and time synchronization system shown in FIG. 44 operating at 30 Hz.

46 is a flow chart of time stamp information through the system of the present invention.

Fig. 47 is a block diagram illustrating synchronization time information processed according to a machine in a microprogram state.

48 is a block diagram showing a first embodiment of the present invention.

49 is another block diagram illustrating a first presented embodiment of the present invention.

50 is a second embodiment of the present invention.

Fig. 51 illustrates a detailed method of addressing used according to the second embodiment according to the present invention.

Figure 52 is a block diagram illustrating an apparatus for decoding Huffman VLCs in accordance with the present invention.

53 is a diagrammatic diagram showing the overall structure of a parallel Huffman decoder of the present invention.

54 is a diagrammatic diagram illustrating a ROM applied to decode parallel Huffman codes.

55 is a first embodiment of a ROM applied to decrypt a parallel Huffman code.

56 is a second embodiment of a ROM applied to decrypt a parallel Huffman code.

FIG. 57 illustrates a third embodiment of a ROM applied to decode parallel Huffman codes.

58 is a block diagram illustrating the major system elements of one embodiment of the present invention.

Fig. 59 is a block diagram illustrating the start sign detector of the present invention.

60 is a block diagram showing an analysis scheme of the present invention.

61 is a block diagram illustrating the major elements of the spatial processing circuit of the present invention.

62 is a block diagram illustrating a display circuit in accordance with the present invention.

63 is an embodiment of time stamp management in accordance with the present invention.

64 is yet another embodiment of time stamp management in the present invention.

65 is a block diagram illustrating hardware elements of the system of the present invention.

Figure 66 is a block diagram providing an overview of system elements of the microcontroller of the present invention.

67 is a simplified diagram illustrating the computational core of the present invention.

68 is an exemplary ALU of the present invention.

69 is a register file diagram according to the present invention.

70 is a diagram illustrating writing to an independent bus register in the present invention.

FIG. 71 is a diagram explaining prediction based on a frame having a vector [1] = 0 and a vector [0] = 0. FIG.

FIG. 72 is a diagram explaining prediction based on a frame having a vector [1] = 0 and a vector [0] = 1. FIG.

FIG. 73 is a diagram explaining prediction based on a frame having a vector [1] = 1 and a vector [0] = 0. FIG.

FIG. 74 is a diagram explaining prediction based on a frame having a vector [1] = 1 and a vector [0] = 1;

FIG. 75 illustrates a prediction based on a field having Motion_Vertical_Field_Select = 0 and Vector [0] = 0.

FIG. 76 illustrates a prediction based on fields with motion_vertical_field_select = 0 and vector [0] = 1.

FIG. 77 similarly illustrates prediction based on fields where Motion_Vertical_Field_Select = 1 and Vector [0] = 0.

FIG. 78 is a diagram explaining prediction based on a field having Motion_Vertical_Field_Select = 1 and Vector [0] = 1. FIG.

79 is a diagram showing field based prediction in a frame screen in which motion_vertical_field_select = 0 and vector [0] = 0.

FIG. 80 illustrates the prediction of FIG. 79 with Motion_Vertical_Field_Select = 0 and Vector [0] = 1.

FIG. 81 shows the prediction mode of FIG. 79 with Motion_Vertical_Field_Select = 1 and Vector [0] = 0.

FIG. 82 is a diagram showing the prediction mode of FIG. 79 with motion_vertical_field_select = 1 and vector [0] = 1.

FIG. 83 illustrates an additional mode of predictive filtering. FIG.

84 shows another prediction mode, too.

FIG. 85 illustrates yet another prediction mode according to the present invention.

86 illustrates another prediction mode of the present invention.

87 is a block diagram illustrating the organization of various system elements of the exhibition system of the present invention.

88 is a diagram illustrating a 4: 3 filtering operation.

89 is a diagram illustrating a 3: 2 filtering operation.

90 is a diagram illustrating the 2: 1 filtering operation of the present invention.

FIG. 91 shows three tap filters used in the present invention. FIG.

92 is a diagram explaining repetition of wrong screen elements.

FIG. 93 is a diagram explaining a field_id signal of the present invention. FIG.

94 is a diagram showing horizontal timing points (cycle cycles) in accordance with the present invention.

FIG. 95 illustrates PAL vertical timing at 625 lines per field in accordance with the present invention. FIG.

FIG. 96 illustrates NTSCV vertical timing at 525 lines per field in accordance with the present invention. FIG.

97 illustrates a horizontal counting machine in accordance with the present invention.

FIG. 98 is a diagram illustrating boundary line generation in the present invention. FIG.

99 is a diagram illustrating screen clipping in accordance with the present invention.

100 is a block diagram illustrating the present invention as a chip.

101 is a diagram illustrating a system clock requirement of the present invention.

102 illustrates a two-wire protocol in the encoded data interface according to the present invention.

Figure 103 illustrates a data token of the present invention.

104 illustrates the FLUSH token of the present invention.

105 illustrates the timing of an encoded data interface.

106 illustrates the use of a non-even mark-space ratio CDCLOCK in accordance with the present invention.

FIG. 107 is a diagram showing output timing in the 16-bit mode in the present invention.

108 is a view for explaining output timing in 8-bit mode in the present invention.

109 illustrates output timing of a video output interface in the present invention.

110 illustrates a video output mode signal according to the present invention.

111 is a diagram showing horizontal timing in the present invention.

112 illustrates vertical timing for a 525 line system.

113 illustrates vertical timing for a 625 line system.

114 illustrates a synchronization and blank signal for a 525 line system in accordance with the present invention.

115 illustrates a synchronization and blank signal for a 625 line system in accordance with the present invention.

116 is a diagram for explaining a zero SDRAM connection environment in the present invention.

FIG. 117 is a diagram illustrating one (1) SDRAM connection environment in the present invention. FIG.

Figure 118 illustrates two (2) SDRAM connection environments in accordance with the present invention.

FIG. 119 is a diagram illustrating a three (3) SDRAM connection environment. FIG.

FIG. 120 is a path diagram illustrating a flag_picture_end operation in accordance with the present invention. FIG.

FIG. 121 is a path diagram showing a start_code_search operation in accordance with the present invention; FIG.

Figure 122 shows a time stamp variant in accordance with the present invention.

FIG. 123 illustrates read timing for a microprocessor. FIG.

124 is a diagram showing recording timing for a microprocessor interface;

* Explanation of symbols for main parts of the drawings

201: start sign detector 202: video analyzer

203 Huffman Decoder 204 Microprogrammed State Machine

206: Synchronous DRAM Controller 212: Video Timing Generator

This application is filed on July 29, 1994, filed in British application 9415413. Claim priority in accordance with No. 5.

The present invention relates generally to a newly improved system for decoding a plurality of audio and video signals, in particular to a new enhancement system for decoding a plurality of MPEG audio and video signals.

The continuous pipeline processing system of the present invention comprises a plurality of modified decompression circuits arranged with a reconfigurable pipeline processor, the only specially designed interaction interfacing tokens in the form of control tokens and data tokens and It consists of a single two-wire bus used to carry similar circuits.

US Patent No. 5, 111, 292 discloses an apparatus for encoding / decoding an HDTV signal. For example, transmissions on Earth include a priority selection processor to analyze compressed video code words between channels of high and low priorities for transmission. A compression circuit corresponding to a high quality video source signal provides a stepped layer of code word CW representing compressed video data and an associated code word T defining the data types represented by code word CW. The priority selection processor corresponding to the code words CW and T counts the number of bits in a given data block and determines the number of bits in each block to be allocated to each channel. Subsequently, the processor analyzes the code word CW with a high and low priority code word sequence so that the high and low priority code word sequences correspond to the compressed video data, which are relatively more important and less important respectively for picture reproduction.

One prior art system is described in US Pat. Nos. 5, 216, 724. The apparatus consists of a plurality of calculation modules for all four calculation modules paired in parallel in the proposed implementation. Each calculation module has a processor, a bidirectional memory, a grabbing paper memory, and an intermediary structure. The first bus connects the compute modules with the host processor. The device consists of a shared processor connected to a compute module with a host processor and a second bus.

U. S. Patent Nos. 4, 785 and 349 show a full color digital video signal compressed, formatted for transmission, recorded on compact disc media, and decoded at the usual video frame rate. During compression, frame regions are analyzed separately to select the optimal full coding scheme specific to each region. The zone decoding time decision is made to optimize the compression threshold. Zone expression codes that convey the size and location of the zones are gathered together in the first segment of the data flow. The zone full codes that carry pixel amplitude indications for the zones are grouped together according to the full code format and placed in different segments of the data flow. The data flow segments are variable length, individually encoded according to each statistical distribution and formatted to form a data frame. Bytes per frame is reduced by the addition of auxiliary data obtained by inverse frame sequence analysis to provide a selected mean value to minimize the pause of the compact disc during recording playback, thereby avoiding the unexpected seek load latency of the compact disc. The decoder includes a variable length decoder that corresponds to statistical information in the code flow for separate variable lengths that decode individual segments of the data flow. Zone location data can be obtained from zone representation data and applied to a plurality of zone specific decoders selected by detection of the full code form (e.g., relative, absolute, pair, DPCM) together with the zone full code and decoded. The area pixels are stored in the bit diagram for later display.

US Patent No. 4, 922, 341 discloses a method for reducing scene model support of video data for digital television signals. As a result, the picture signal provided at time is encoded, and the preceding frame from the scene already encoded at the time (t-1) is present in the image store as a reference, and the frame-to-frame information is amplified, shifted, It consists of a quaternary tree division structure obtained suitably. When the system is initialized, the screen banjo represented by a uniform and defined gray scale value or defined brightness value is stored in the image store of the encoder at the transmitting device or in the image store of the decoder at the receiving device in the same way as for all screen components (pixels). Are written in. In addition to the video store of the decoder, the video store of the encoder can also read the contents of the encoder and the video store of the decoder into blocks of variable length, can be amplified with elements of brightness greater than or equal to 1 and less, and with the shifted address Each is done by returning to itself in such a way that it can be written back into the store. Thereby, blocks of variable length are constructed according to a method known as a quaternary tree data structure.

US Patent No. 5, 122, 875 discloses an apparatus for encoding / decoding HDTV signals. The apparatus includes a compression circuit corresponding to a stepped layered code word CW representing compressed video data and a high quality video source signal providing an associated code word T defining the data types represented by the code word CW. do. Priority selection circuits corresponding to codewords CW and T provide codewords CW with high and low priority and codeword sequences so that high and low priority code word sequences correspond to compressed video data, which are relatively more important and less important for image playback, respectively. Analyze The transfer processors corresponding to the high and low priority code word sequences form high and low priority transport blocks, respectively, of high and low priority code words. Each transport block includes a header, code word CW and error detection check bits. Each of the transport blocks is adapted to a potential error check circuit for adapting the added error check data. After that, high and low priority data is applied to the modem where the quaternary amplitude modulates each carrier for transmission.

In U.S. Patent No. 5,146,325, video decompression for decompressing compressed image data in which odd and even fields of the video signal are independently compressed in a sequence of inner and interframes and then interleaved for transmission. Start the system. Odd and even fields are independently decompressed. Even / odd field data replaces unusable odd / even field data while valid decompressed odd / even field data is unavailable. Independently decompressing even and odd fields of data and replacing them with opposite fields of data for unusable data can advantageously be used to reduce image display latency during system startup and channel changes.

US Patent Nos. 5, 168 and 356 disclose a video signal encoding system including an apparatus for dividing encoded video data into transport blocks for signal transmission. The transport block format increases the reconstruction of the signal at the receiver by supplying header data that allows the receiver to determine the reentry point into the data flow in the event of loss or anomaly of transmitted data. The reentry point is maximized by supplying secondary transport headers contained in the encoded video data of each transport block.

U. S. Patent No. 5, 168, 375 discloses a method of processing a field of image data samples that feeds one or more of decimation, interpolation, and sharpening functions. This is done by the array conversion processor as used in the JPEG compression system. The blocks of data samples are both transformed by a discrete right function cosine transform (DECT) in decimation and interpolation processing. This changes the number of frequency terms. In the case of decimation, the number of frequency terms is reduced, followed by an inverse transformation that produces a reduced size matrix of sample points representing the main block of data. In the case of interpolation, zero-valued added frequency components are inserted into an array of frequency components, after which the inverse transform can produce an increased data sampling set without increasing the spectral bandwidth. In the case of sharpening, it is performed by convolution or filtering techniques, including the product of the data and filter center transforms in the frequency domain, where an inverse transform is supplied which results in a set of blocks of processed data samples. Convexities overlap, followed by storage of the indicated samples and discarding excess samples from the overlapping area. The spatial representation of the key components is changed by the reduction of the number of components for the linear phase filter and interpolates 0 to equal the number of samples in the data block. This is followed by the formation of a discrete functional cosine transform (DOCT) of the fitted key matrix.

U. S. Patent No. 5, 175, 617 discloses a system and method for transmitting video images on logs over a bandwidth limited analog channel of a telephone line. In logarithmic images, pixel organization is designed to fit the sensor geometry of the naked eye closer to the center of the pixel. The transmitter divides the frequency width into channels and allocates one or two pixels to each channel. For example, a 3 KHz voice component telephone line is divided into 768 channels of about 3.9 Hz. Each channel consists of two carrier waves in quadratic, so each channel can carry two pixels. Some channels are reserved for special measurement signals that allow the receiver to sense both the phase and amplitude of the received signal. If the sensor and pixel are directly connected to the oscillator area and the receiver can receive each channel in succession, the receiver does not require synchronization in the transmission. The FFT algorithm runs a fast discrete approximation in a continuous state where the receiver is synchronized to the first frame and then obtains frames following each frame period. The frame period is relatively small compared to the sampling period so that once the first frame is detected, the receiver does not lose frame synchronization. The experimental video telephony, which transmits 4 frames per second, applies quadratic encoding to images on a 1440 pixel log, resulting in an effective data rate of over 40,000 bits per second.

US 5, 185, 819 discloses a video compression system having odd and even fields of a compressed video signal independently of a sequence of compression modes of inner and inter frames. Odd and even fields of independently compressed data are interleaved for transmission such that the even fields of the inner frame that have compressed the data occur between successive fields of the odd fields of the inner frame that have compressed the data. The interleaved sequence provides a receiver with twice the number of entry points in the signal for decoding without increasing the amount of data transmitted.

US Patent No. 5, 212, 742 discloses an apparatus and method for processing video data for compression / decompression in real time. This device consists of a plurality of calculation modules for all four calculation modules connected in parallel in the presented scheme. Each calculation module has a processor, bidirectional port storage, scratch-pad storage, and a controller. The first bus connects the compute module with the host handler. Finally, the device consists of a host processor and shared storage connected to a compute module with a second bus. This method deals with the allocation of the images that each processor performs.

A system and method for implementing an encoder suitable for use with the ISO / IEC MPEG standard proposed in US Pat. No. 5,231,484. Perform various and appropriate priorities for the incoming digital dynamic video sequence, assign bits to the screen of the sequence, and assign the bits in the screen to different areas of the screen within the video sequence to provide the optimal time component. Three interacting components or subsystems are included to properly quantize the transform coefficients.

U.S. Patent Nos. 5, 267 and 334 show a method for removing redundant frames in a computer system for a sequence of dynamic images. This method detects the first scene change in the sequence of moving images and generates the first key frame containing complete scene information of the first image. The first key frame is known as a potential facing key frame or an inner frame in the presented scheme, which is standard in CCITT compressed video data. The process includes generating at least one intermediate level compressed frame containing difference information for at least one image following the first image at a time in the sequence of moving images from the first image. This at least one frame is known as a mutual frame. Finally, detecting the second scene change in the sequence of the video and generating a second key frame containing complete scene information about the image shown in time prior to the second scene change is known as the rear-facing key frame. The first key frame and the frame compressed in at least one intermediate stage were concatenated for the transposition execution, and the second key frame and the frame compressed in the intermediate stage were concatenated inverse for the reverse execution. The inner frame is also used for the generation of complete scene information when the image is run in the dislocation direction. When this sequence is executed in reverse, a back-to-face key frame is used for generation of exchanged scene information.

U.S. Patent Nos. 5, 276, and 513 provide effective cost-effective structural motion analysis (HMA) in real time with minimal system processing delay and / or minimal system processing delay and / or minimal hardware architecture. Disclosed is a first circuit arrangement that constitutes the same given number of prior art image pyramid stages, with a second circuit arrangement that constitutes a given number of new motion vector stages to perform. In particular, the first and second circuits correspond to relatively high resolution image data from a continuous continuous input of continuously given pixel density image data occurring at a relatively high frame rate (e.g., 30 frames per second). The apparatus derives a continuous continuous output of a given pixel density vector data frame occurring at the same given rate after some processing system delay. Each vector data frame represents an image movement occurring between each pair of consecutive image frames.

In US Pat. No. 5, 283, 646, while encoding a picture once only modifies the magnitude of the quantization step used to quantize a coefficient that describes, for example, a picture sent across a communication channel, A method and apparatus are disclosed that enable a real-time video encoding system to deliver exactly the required number of bits per frame. Data is divided into sectors, each sector including a plurality of blocks. The blocks are coded to generate a sequence of coefficients for each block, for example using DCT coding. The coefficients are quantized, and depending on the quantization step, the number of bits required to describe the data varies considerably. The accumulated actual number of bits increased at the end of each sector of data transfer is compared to the accumulated required number of bits increased for the selected number of sectors associated with the particular data group. The system then resizes the quantization step to target the last required number of data bits for a plurality of sectors, for example describing an image. Various methods are described to revise the quantization step and determine the required bit allocation.

US Patent No. 5, 287, 420 discloses a method and apparatus for image compression suitable for a personal computer device that compresses and stores data in two stages. The images are acquired in real time and compressed and stored on the hard disk using effective methods. After a period of time, the data is further compressed in non real-time using a computationally more powerful algorithm that results in a higher compression rate. The two-stage approach allows the storage reduction gains of a very sophisticated compression algorithm that is achieved without requiring computational resources to perform this algorithm in real time. A compression algorithm suitable for performing the first compression step of the host processor on a personal computer is also described. The first compression step receives 4: 2: 2 YCrCb data from the video digitizer. The two color elements are averaged and the pseudo random number is added to all the elements. The resulting values are quantized and gathered into one 32-bit word representing a 2x2 array of pixels. The pseudo random number's source value is stored so that pseudo random noise can be removed before performing the second compression step.

US 5, 289, 577 discloses a method and apparatus for a sequence processing pipeline having a first processing stage connected to a CODEC via a plurality of buffers including an image data input buffer, an image data output buffer and an address buffer. . The address buffer stores the addresses, each of which identifies the initial address of the address block in the image store. Each block of addresses in the image storage device stores a block of decompressed image data. The local controller responds to the writing of the address into an address buffer that initiates the execution of the CODEC executing the discrete cosine transform process and the discrete cosine transform quantization process.

Item, Chong, Yong M., Data Flow Design for Digital Image Processing, Wescon Technical Papers: No. 2 Oct./Nov. In 1984, a real-time signal processing system specially designed for image processing is disclosed. More specifically, a token is presented based on a data flow design where the token is a fixed word width with a fixed width address field. The system includes a plurality of identical flow processors connected in a ring shape. Tokens include data fields, control fields, and tags. Furthermore, the tag field of the token is classified into a processor address field and a recognizer field. The processor address field is used to derive the token into the correct data flow handler, and the identifier field is used to tag the data so that the data flow processor knows what to do with the data. In this way, the identifier field acts like an indication for the data flow handler. The system uses a module number to direct each token to a specific data flow handler. If the module number matches the number of modules in a particular row, then the appropriate action is taken on the data. If not recognized, the token is directed to the output data bus.

See, Kimori, S. et al. Suitable Pipeline Mechanism by Automatically Timed Circuits, IEEE J. of Solid-State Circuits, Vol. 23, No. One,. Feb. In 1988, a suitable pipeline with automatically timed circuits is disclosed. An asynchronous pipeline consists of a plurality of pipeline stages. Each pipeline stage consists of a group of input data latches prior to the combined logic circuitry that performs specific logic operations at the pipeline stage. The data latch is supplied simultaneously with the trigger signal generated by the data transfer control circuit associated with that stage. The data transfer control circuits are connected to form a link between the successive pipeline stages to send and acknowledge the control of the signal lines in the handshake mode of data transfer. Furthermore, a decoder is usually supplied at each stage to select the execution done by the operator in the current stage. It is also possible to place the decoder at the preceding stage to decode the complex decoding process earlier and to mitigate the critical path problem in the logic circuit. All interprocessing between submodules is determined by fully localized decisions, and in addition, each submodule performs its own data buffering and automatic timed data transfer control at the same time, so that the proper characteristics of the pipeline Remove control as well. Finally, to increase the suitability of the pipeline, empty stages are sandwiched between occupied stages to ensure reliable data transfer between stages.

Accordingly, those skilled in the art recognize the long-standing need for a new and improved video decompression system that eliminates the shortcomings of critical technology systems. The present invention clearly meets this need.

Briefly and generally, the present invention provides a novel and improved approach in devices applied to two-line pipeline systems with various control and data tokens. The key components of the system include a start code monitor, a Huffman decoder and a parser with an MSM, an inverse discrete cosine converter, a DRAM synchronizer with an address generator, circuitry showing appropriate circuit predictors and upsampling and picture time generators. have.

More importantly, several implementations of the present invention include multi-level mechanisms connected by MPEG picture compression and a two-wire interface arranged by a pipeline generation machine. Control tokens and data tokens go beyond a single two-wire interface format that carries both control and data tokens at the same time. The token decoder circuitry is located either for recognizing tokens that are valid for that stage, or for sending unverified tokens through the pipeline. The relocation generation circuit is placed in a fixed position and responds to the confirmed control of relocating the steps of recognizing the data token. Various types of auxiliary system circuits and generation techniques represent memory addressing, transformations using common generation blocks, starters, asynchronous swing buffers, parallel Huffman decoders, and so on.

In the above example, the present invention is not merely to draw a limit, but the present invention provides a communication system having a starter, a stamp for determining the current time, a clock reference for the system initialization time contained in the first circuit, and a clock reference for the system time of the first circuit. The first time counter, initialized by the clock reference of the second circuit synchronized by the first time counter, has a copy of the local system time and the current time between the copy of the local system time and the system time by comparing the time stamp with the second time counter. It includes a variety of things, such as a second time counter that determines the time error. Furthermore, the first time in a communication with a mechanism for synchronizing the system decoder using the time stamp to determine the display time, a clock reference for initializing the system time in the system decoder, and a clock reference for keeping the system time in the system decoder. By the clock reference of the picture decoder synchronized with the first time counter for determining the display time error resulting from the difference between the system time and the local copying system time by counting the counter and the local system time and comparing the second time counter with the time stamp. Contains a second period counter that is initialized.

Another embodiment of the present invention is an apparatus for synchronizing first and second circuits using a clock reference for initializing system time in a first circuit, a first circuit with a time counter in communication including a clock reference for keeping system time, and an elementary stream time. It includes the first elementary stream time counter in the first circuit that provides. The first circuit is applied where the time stamp is taken, and the first circuit generates a synchronization time by subtracting the system time from the sum of the elementary stream time and the time stamp. The second circuit is adapted to accept the synchronized time in the first circuit and synchronizes with the base stream counter to determine the time error through the comparison of the time synchronized with the local copy of the base stream's time and the synchronized time with the local copy of the base stream's time. Has a second elementary stream counter. In this way, the clock reference signal does not have to be passed directly to the second circuit to determine the time error.

Another embodiment of the present invention is a device for synchronizing a first and a second circuit having a clock reference for initializing the first circuit system time. The first circuit has a time counter in the communication having a clock reference to keep the system time and a first picture time counter for providing time to decode the picture. The first circuit is applied to receive burn time and subtract system time. The second circuit is adapted to receive the synchronized time coming from the first circuit, providing a copy of the picture decoding time, and comparing the synchronized time with the local copy of the picture decoding time to determine the time error between the picture time stamp and the system time. Has a second picture time counter synchronized with the first picture time counter. Therefore, it is not necessary to send the clock reference signal directly to the second circuit to determine the error of time.

The invention also includes a way of providing time information in a picture data stream having a time stamp in the packet header, where the time stamp means the first picture in the data packet. In the next step, the register is supplied with a flag for storing the period stamp information extracted from the packet header. Next, the time stamp is posted from the image to the register. This method then encounters where the picture begins, and subsequently checks the state of the flag to see if it contains time stamp information that has settled in the register. If the flag indicates that the register contains the correct time stamp, a response to it creates a time stream, which in turn enters the data strip.

Another embodiment of the present invention includes the equipment described above applied to an elementary stream time counter limited to 16 bits. Similarly, there is similar equipment as described above, where the second elementary stream time counter located within the elementary stream decoder is limited to 16 bits. Furthermore, there is a similar device as described above, where the time synchronization for controlling the elementary stream decoder is limited to 16 bits. The present invention has a process for decoding a picture and determining a display time error with respect to a threshold. Then, the image data is decomposed into tokens for further processing and to determine whether a time stamp is specified, to compare the time stamp token with the image time, and to generate a comparison value for determining an error of the specified time. . Next, when the value specified by the time error is compared with an externally recognized value, it is determined whether the comparison value is-if compared with a threshold value-an acceptable range.

Another application scope includes a system decoder and an apparatus using an image decoder. The system decoder is designed to accept an MPEG system stream and demux the picture data and picture time stamps from the stream. The system decoder has a first time counter that indicates the system time. The picture decoder accepts picture data and picture time stamps and has a second time counter synchronized with the first time counter. The picture decoder continuously receives picture data at the same rate, outputs picture data at various rates, and has a decoder buffer for decomposing picture time stamps. While the picture decoder decodes the picture from the picture data, it also compares the picture time stamp for the decoded picture with a second time counter that determines the appropriate display time. In the first circuit, the formula X = ET + TS-SY gives the synchronized time (X) to the second circuit and generates a synchronized elementary stream time (ET2), by the ET2-X formula and the synchronized time. Synchronization time (X), time stamp (TS) and system time obtained from using system time (SY), time stamp (TS), elementary stream time (ET) as the time error is obtained using (X) Another method is to determine the time error of the first and second circuits by providing (SY). Thus, time equalization of the first and second circuits can be achieved without sending system time to the second circuit.

The method for determining the time error of the first and second circuits is as follows:

Put the time stamp (TS) and the start time (IT) in the first circuit, and find the synchronized time (X) using TS and IT according to the formula X = TS-1. In the second circuit, the synchronized time (X) is input to generate a synchronized elementary stream time (ET), and the time error is obtained using the synchronized time (X) according to the formula ET-X.

Another way to find the time difference between the first and second circuits is as follows: Put the synth time (ST), the picture time stamp (VTS), and the picture decoding time (VT) in the first circuit, and Find the synchronized time (X) according to = VT + VTS-SY. A time error is obtained according to the formula VT2-X by inserting the time X synchronized to the second circuit and generating the picture decoding time VT2 of the second circuit synchronized with the picture decoding time VT of the first circuit. Thus, it is possible to synchronize the time of the first and second circuits without sending the system time to the second circuit.

According to the present invention, the parallel Huffman decoder stage is capable of decoding MPEG Huffman code variable lengths (VLCs) and fixed length codes (FLCs), and the distribution of tokens under the control of a parser microprogrammable machine. And good output can be maintained.

In the embodiment of the present invention, the code lookup technique is used to handle Huffman decoding to obtain the required result, and to handle MPEG-2 conversion constant tables which are not constant or not accepted in nature. The implementation of the present invention is also used to decode more complex elements from a stream for one period without the aid of an external controller.

To decode the VLC, the input is first put into two input registers that handle the top and bottom. The selector is used to align the start of the next VLC with the ROM input. Thus, for the first VLC, the selector only outputs 28 bits of the 59-bit input, of which the first 16 bits are sent to the Huffman code RAM. For the next VLC, the selector shifts the input by the number of bits detoted so far. By adding the size of each VLC while it is being decoded, the addition of bits is done to find the total. The length of the various words is the result of the maximum code length that can be decoded, that is, the 28-bit MPEG-1 escape code constant, and the maximum VLC size is 16 bits. (DCT constant table)

The "Chart Selection" input is used to select from the various Huffman code tables required by MPEG.

RON has an address controlled by a selector / shifter. The ROM performs a VLC table index calculation, and then performs an index-data process to obtain decoded data.

Index calculation is a content addressable memory (CAM) that performs the same thing as "Dung-Care" configured to handle the Huffman code that composes the current data. Since the creation of the index is created by a look-up rather than by an algorithm, there is no limit to dealing with a recognized table.

The ROM address of the present invention has two fields. The wider field is the bit-pattern to be decoded, and the smaller field is to select the Huffman code table to be verified. In addition to the completed MPEG code table, the ROM has the content of recognizing the disallowed VLC patterns that exist for other code tables.

In another embodiment of the present invention, there is a procedure used to provide a word of limited length, have a fixed number of bits for addressing data of varying length, and define the length of the field and address field. There is also a procedure for addressing a fixed length word memory, addressing data and having a fixed number of bits with swapped fields and address fields. There is also an apparatus for addressing a memory containing a state machine and an arithmetic core.

Addressing in memory is characterized by the following procedure:

Providing a fixed length word having a predetermined fixed number of bits used for addressing various length words; Defining a fixed length word having a definition of the length of the field and address field; Providing a length defining a field having at least one bit as a termination mark; Definition of an address field with various bits defining the address of the data; Adjusting the number of bits in an address field that is inversely related to variable length data; Adjusting the number of bits in a field that is directly related to the size of variable length data; And maintaining a fixed length word for variable length data while adjusting the length of the field and address field.

The process for addressing the memory involves:

Definition of an address field with various number of bits defining the address of the data; Defining various lengths of auxiliary fields having at least one auxiliary bit; An auxiliary field preparing at least one press bit as an end point between an address field and an auxiliary field; Use of an auxiliary field indicating an auxiliary bit from a separate addresser; And maintain a fixed length word for variable length data while adjusting the length of the address field and the length of the auxiliary field in reverse.

According to the present invention, addressing of variable-length data into a memory supplies a memory having a pre-expected word length consisting of partial words, rotating partial words to accommodate least significant bit correction, and rest of the remaining portions. Words can also be spread and recognizable as partial words, re-stored in the rest of the word, and characterized by rotation so that the partial word is returned to its original position.

The present invention provides methods and equipment for defining fields and lengths of address fields with fixed length bits for addressing fixed length words, addressing of various lengths of data. In addition, a fixed length word may be used that has a fixed number of bits and is used for addressing data having an auxiliary field and an address field.

The present invention also includes a method of accessing the Mth word smaller than the predetermined length N of the RAM from the RAM. RAM has an enable and disable line that controls what goes in and out of RAM, and how to access RAM includes the following steps:

Arrange N words for reading or writing from RAM;

Determines when M words were written to or read from RAM, M is less than N;

Disables RAM by determining when M words are written to or read from RAM.

The present invention also includes an access method for extracting and storing a two-dimensional image of a DRAM. DRAMs have two different banks, each bank can read and write data as pages, two-dimensional images are arranged in a two-dimensional grid of cells, and each cell has an MxN pixel matrix, The word occupying each cell accesses the DRAM in the following way.

a) Designate each cell as a particular bank of two banks so that a particular cell can be read or written from a page of that particular bank, and each cell is associated with a different bank. That is, you assign cells to banks so that the cells at the border are in the same column or in the same row.

b) Read a data word associated with a cell consisting of a matrix of pixels. It does not match the two-dimensional grid pattern, but matches the pixels in the cells in the two-dimensional grid pattern.

c) Find cells in a two-dimensional grid pattern that contain data words associated with unaligned cells.

d) Read the data words associated with the cells in the grid pattern determined to have data words associated with the unaligned cells from the first bank of DRAM.

e) Read data words associated with other cells in the grid pattern determined to have data words associated with the unaligned cells from the second bank of DRAM.

f) Repeat steps (d) through (e) until all data words associated with all unaligned cells have been read.

The present invention also provides a RAM interface for a bus that is connected to the RAM in a generator where the RAM interface generates the addresses needed for addressing the RAM. The address generator communicates with the RAM interface via a two-wire interface.

The present invention provides a control scheme of a buffer for receiving encoded picture information, such as a frame or a field. This method employs methods such as determining the number of pictures of each decoded frame to be input, determining the predictable number at any time, and preparing a buffer if the number of pictures matches or exceeds the number available. .

Therefore, those who have struggled for the design or development and the image decoding system will have a further improvement in the completion of the present invention. Other objects and uses of the invention will be introduced through the following detailed description and diagrams.

In the following description of the practice of the invention, the following items are frequently used and are generally defined by the following terms.

[Glossary]

Block: an 8-row, 8-column matrix of screen elements, or 64 DCT coefficients (quantized or unquantized sources)

Color element (element): A matrix, block, or single picture element that represents one of two different color signals associated with a primary color in a manner defined within a bit flow.

Coded Representation: The data element represented in the coded form.

Coded Video Bit Flow: A coded representation of a series of one or more screens as defined in this specification.

Coded Order: The order in which the picture is transmitted and decoded. This order need not be the same as the display order.

Element: A matrix, block, or single screen element from one of the three matrices (brightness, two colors) that make up the screen.

Compression: Reduction in the number of bits used to represent a data item.

Decoder: An embodiment of a decoding process.

Decoding (Processing): The process of reading the encoded bit flow of an input, as defined in this specification, and generating a decoded picture or audio sample.

Display Order: The order in which the decoded screens are displayed. Typically, this is the same order in which the screens appear at the input of the encoder.

Encoding (processing): The process of reading a stream of input pictures or audio samples, not specified in this specification, and generating a valid encoded bit flow defined in this specification.

Internal encoding: Encoding of a macroblock or picture using only information from the macroblock or picture.

Brightness (component): A matrix, block, or single picture component that represents a monochrome representation of a signal associated with a primary color in a manner defined within a bit flow.

Macro Blocks: 4 8 × 8 blocks of brightness data and 2 4: 2: 0 color formats, 4 4: 2: corresponding to 8 × 8 blocks of color data from 16 × 16 divisions of brightness elements on the screen Two color formats or eight 4: 4: 4 color formats. Macro blocks are sometimes used to refer to picture element data, and sometimes used to refer to picture element values defined in the macro block header of syntax defined in this part of this specification, and to encoded representations of other data elements. As one of the common functions in this technique, usage is excluded from the context.

Motion Compensation: Use of motion vectors to improve the efficiency of prediction of screen element values. Prediction uses motion vectors to provide an offset to past and / or future reference pictures that contain pre-decoded picture element values used to form the prediction error signal.

Motion vector: A two-dimensional vector used for motion compensation that provides an offset from a coordinate location on the current screen to coordinates on a reference screen.

Non-internal encoding: encoding of a macroblock or a picture using information itself and information from the macroblock, and pictures occurring at different times

PEL: Screen element.

Screen: Source, coded or reconstructed image data. The source or reconstructed picture consists of three rectangular matrices of 8-bit numbers representing brightness and two chroma signals. In interlaced video, the picture is the same as the frame in the enhanced video, whereas the picture is related to the top or bottom field of one frame or frame according to the context.

Prediction: The use of a predictor that provides an estimate of the current decoded picture element value or data element.

Reconstruction Processing Step (RPS): A step that corresponds to a recognized token that reconstructs itself to perform various tasks.

Slice A series of macro blocks.

Token: A widely applied unit in the form of an interactive interfacing messenger package for control and / or data functions.

Start code [system and video]: A 32-bit code embodied in a unique coded bit stream. These are used for several purposes, including identifying any part of the structure in the encoding syntax.

Variable length coding: VLC: A process that can be used as an inverse for coding to assign a short code word to a frequently used item and a long code word to a less frequently used item.

Video sequence: A series of one or more screens.

"Detailed Description of the Invention" includes the following parts.

1) Detailed description of the invention on storage addressing

Variable-length fields in fixed-width words

Use fixed-width words with variable length fields to perform address substitution

Addressing variable width data with fixed width words

Machine structure in microencoded state

Computational core

2) Detailed description of the invention for data transformation using common processing blocks

Theoretical background of the invention

3) Detailed description of the invention for time synchronization

4) Detailed description of the invention for an asynchronous swing buffer

5) Detailed description of the invention for storing video information

6) Detailed description of the invention for parallel Huffman decoder

Huffman code ROM

Maximized Throughput

FLC and Tokens

Execution mechanism

7) more detailed description

By introducing exemplary embodiments of the most common features of the invention, particularly mentioned in FIG. 1, data flow through the presented concept 200 of the invention is shown. Embodiments of the present invention are primarily implemented using a two-wire pipeline system with various control and data tokens. The main elements of the system are the video analyzer 202, which combines the start sign detector 201, the Huffman decoder 203, and the micro-programmed state machine (MSM) 204, the synchronous DRAM controller 206 with the inverse discrete cosine transform 205, the associated address generation unit 207, the upsampling 210 And 211 and a suitable prediction circuit including the video timing generator 212 208 and the display circuit 209.

This application is related to a topic similar to that shown in British Patent Application No. 9405914.4 entitled “Video Decompression” filed on March 24, 1994 by Discovision Associates. And later applications are specifically incorporated by reference in this application.

In accordance with the above, certain aspects, features, and subsystems of the invention will be mentioned in more specific details below. As with references in the figures, the numbers define the same or corresponding parts throughout the various figures and figures.

Detailed description of the invention for storage addressing

A method and apparatus for addressing a storage device in accordance with the present invention are described herein. In particular, the present invention provides a fixed width word for accepting a variable width bit field. Moreover, the present invention provides a method of addressing variable width data with fixed width words. In various forms of embodiments the various bit fields are used to specify the bits to be replaced within words, or to specify the unused portion of a word that addresses variable width data with words of fixed width. In addition, the system of the present invention includes a machine in a micro coded state with a computational core.

Machines in the microencoded state will be used to solve planning problems that require the need for versatile and / or complex computations. Examples of such schemes include address generation, flow analysis and decoding, and filter tap coefficient calculations. In this regard, addressing must deal with two different characteristics: (1) variable-length addresses and (2) address substitution to access variable-width portions of words. In the present invention, a RAM having a 64 × 32 bit environment is addressed in a partial word having a 64 × 32 bit, 128 × 16 bit, 256 × 8 bit, 512 × 4 bit, 1024 × 2 bit, or 2048 × 1 bit format. Should be able to be specified.

[Variable length field in fixed width word]

In many applications, it is useful to define variable portions of words for actions such as replacement, variable width data addressing, or compression of other portions of words. A convenient way to define the variable part of a word is to have an added word (or words) that specifies the width of the field in the data. According to the invention, a method of encoding such information in the word itself is described. Current methods have advantages in storing bits in the overall definition of the word, simplifying the decoding of the coded word, and providing a more intuitive view of the coded. Moreover, if the variable width field is the most significant or least significant bit recognized in the word, this encoding method can be applied.

Thus, Table 1 shows two examples of a variable width field (denoted "F") that is the least significant bit defined within an 8 bit word.

TABLE 1

Table 2 shows a typical way of encoding the field shown in Table 1 using enough additional bits to specify the maximum width of the binary field. (The bits marked with an "x" are "dun care", that is, their values are not important.) This method is certainly insufficient in the use of the bits, and moreover has a less intuitive form than described in the present invention. to provide.

TABLE 2

The new method according to the invention defines a field in a word. This method uses a continuous indicator and an end indicator to define the field. As a series of consecutive indicators preceding the end indicator, the field is specified from one end of the field. However, for a zero length field, only an end indicator is provided at the end of the word. Both the continuous indicator and the end indicator are single bits and must be complementary to each other. In addition, the field must be accepted at the other end of the word. Thus, the method of the present invention for encoding a field requires only one bit of extra width in the original word width.

As shown in Table 3, the coding of the fields shown in Table 1 according to the new method is described. In this example, the continuous indicator is "1" and the end indicator is "0". In this example, the field is considered the least significant bit.

TABLE 3

Therefore, the advantages of the encoding method according to the present invention are as follows. ;

1. Reduction of the number of bits required for encoding

2. Since the need for “x for 1” in the decoding of the “field definition” shown in Table 1-2, which is routinely required, is already in place in the encoding in the form of 1 for 2 ^x , it is simplified in the decoding process. Is required.

3. Encoding is a more intuitive form of allowing fields that are defined to be more easily recognized.

Thus, the use of the encoding method of the present invention can also be used such that the end indicator and the continuous indicator are reversed to provide that the encoding of Table 3 is similar to the encoding of Table 4. Thus, the use of "1" or "0" is used interchangeably through this application.

TABLE 4

As previously identified, the coded field must be accepted at the other end of the word. Table 5 illustrates the fields that are considered the most important. In other words, they are encoded in a similar manner as in the field of bits that are considered least important except that the fields reach up from the most significant bit (MSB) to the least significant bit (LSB) and contain the first end indicator. The encoding of the fields shown in Table 5 is shown in Table 6.

TABLE 5

TABLE 6

Moreover, the fields may be encoded simultaneously from the least significant end and most significant end of the word. For example, the two fields shown in Table 7 may be encoded as in Table 8 by adding only one bit for each field as described previously.

TABLE 7

TABLE 8

[Use of fixed width word with variable length field to perform address substitution]

It may be useful to replace part of the storage address by another value. In this way it is possible to construct an address of a data dependency. The encoding method of the present invention can be applied to addresses of a storage device specifying which part of the address can be replaced. If the least significant bit in the variable length field is used for the address, a replacement field may be defined. For example, the encoded 12-bit address Obaaaaaaaaaaaa with the five least significant bits replaced by the 12-bit value of Obcccccccccccc would be Obaaaaaaa011111, giving the address Obaaaaaaaccccc. Table 9 shows the encoding replaced into a 12-bit address.

TABLE 9

[Addressing variable width data with fixed width word]

One embodiment of the present invention is for addressing storage devices that can be accessed at full width, or at 2 ⁿ widths up to full width. (These small words are called partial words.) Thus, this shows how the variable field coding of the present invention can be used to address this memory and how it can index such addresses into the memory. Will indicate.

Accessing a 64x32-bit register file at widths of 32, 16, 8, 4, 2, and 1 bits requires different lengths of addresses. In other words, the execution tool of this embodiment is a 64 × 32 bit storage device accessible as 64 × 32 bit, 128 × 16 bit, 256 × 8 bit, 512 × 4 bit, 1024 × 2 bit, or 2048 × 1 bit. to be. This indicates that 12 bits are required to address one of the 2048 × 1 bit positions, while 5 bits are required to address one of the 64 × 32 bit positions. Thus, the address can be of variable length, and in fact the width of the address specifies the address format of the storage device. Thus, the address can be addressed within a fixed word width using the variable width field, which is considered the most important, to compress the address and determine its width. This is illustrated in Table 10.

TABLE 10

To allow indexing of an address, a portion of it can be replaced using the same method as previously described for address substitution. The replacement part (or field) of the address can be determined by the least significant bit recognized in the variable length field (continuous indicator “1”, end indicator “0”) added to the top of those shown in Table 10. As an example, using the address of an 8-bit word, Table 11 shows how to determine the number of least significant bits that are replaced. The least significant bit added is the alternate indicator scale (marked “w”). The general case of a fixed width word for replacement is shown in FIG.

TABLE 11

In fact, the replacement code is appended to the top of the already encoded address. From this encoding it can be seen that there are illegal addresses, very clearly 0x0000 and 0x3fff. In this case, “0” must be at the bottom 9 bits to prevent more than 8 bits being replaced, and “6” above 6 bits specifies the allowable access width. If one of these errors is detected, access will not be determined and the register file contents will not be affected.

In accordance with the present invention, a system for addressing and a word for a portion of a register file is discussed below.

Routine memory circuitry dictates that memory must always be accessed at full width. To achieve variable width access, a full (32 bit) wide word is read. This whole word is cycled until the word of the accessed part is acknowledged in the least significant bit. The upper part of the word extends to the full width and then to the output. Extensibility to zero or one (1), symbol expansion can include insertions using the symbol bits of the symbol-size number, as in the new most significant bit or any similar conventional method. Expansion depends on the mode of operation. When a word of a portion is input to the memory device and is written back into the memory device, it is multiplexed back into the whole word that was cycled, which is then cycled back and written into the array. 3 shows this step for accessing a four bit partial word to a fourth four bit word of a 32 bit word.

To access a partial word or to read a partial word, as in the highlighted four-bit word shown at line 213 of line 1 of FIG. 3, the full-width word, as shown in line 214 of 214, selects the word of the portion at the least significant bit. To be deployed. As shown in row “3” 215, the 4-bit word is expanded to create the entire 32-bit word. This word can now be accessed.

As shown in FIG. 3, the full width word selected for rewriting is truncated shortly to the width of the original partial word multiplexed with the word shown in line “2” 214. At the least significant bit position, this appears in row “4” 216. The resulting word is cycled back to the original importance in the read word, which appears in line “217”. This entire Weed can now be written back into the register file.

Thus, the following list is a summary of the numbered steps in FIG.

1. A whole word read from storage.

2. The 12 bits circulating to the right bring the partial word into the least significant bits.

3. Stretches to the whole word and passes it to the output.

4. The input partial word is multiplexed into the whole word circulated from (2).

5. The 12 bits circulating left bring the entire word to its original state as recorded.

The above approach presents the data flow structure of the storage device shown in FIG. The numbers in the structure are mentioned in the text above and in Figure 3.

The storage address must be decrypted to control the above structure. It should be recognized that the most significant bits of any width of the address are of the same importance along with the bits that reference memory. The six bits above the decoded address are 32-bit word addresses, and the rest are one-bit addresses. Thus, the decryption step (parallel to replacement) decodes the width of the address defining the variable field by detecting the position of the most important end indicator. This allows an address to be recognized as the most significant bit (by shifting to zero in the least significant bit). The six bits above can be used directly as the 32-bit word row address of the storage device. For example, since the original 32-bit address always has a shift of 0b00000 (which was shifted when the address was recognized as the most significant bit), the bottom five bits were used to directly control the barrel shifter (as shown in Figure 4). Can be used. Similarly, a 16 bit address can have a shift of 0bx0000, that is, a 0 or 16 bit shift. The 1-bit address may have an Obxxxxx shift, that is, a 0 to 31 bit shift. The expander and input multiplexer are each controlled by access width decryption, which hides the output words and multiplexes the input words with appropriate importance. The block diagram of the decryption is shown in FIG. This may indicate that decoding of the two variable width fields for width and replacement can be done in parallel and independently.

Figure 2 illustrates an example of a fixed width word 13 bit long to address variable width data and replacements as shown in the two rows below. In this example, an 8 bit word is addressed at location 0b110: ssss, where “ssss” is replaced from another address source.

[Micro-encodeable state machine structure]

The substitution in the storage address and the variable width access of the storage device are brought together in accordance with the invention in the implementation of the micro-encoded state machine of the structure shown in FIG. The structure is one of the state machines 218 that provide control of the computational core 219 by a broad word of control signal called a micro sign instruction. The operation unit core 219 passes the state flag and data in turn to the state machine 218.

In accordance with the present invention, state machine 218 includes a storage device that contains a list of microcode instructions. Like a conventional microcoding state machine, this can be undertaken through a list of microsignal instructions at hand or a jump can occur from one instruction to another. The jump address is in the form shown in FIG. The substituted value comes from the computational core 219 as shown in FIGS. 6 and 8. This allows the construction of a jump table in the micro code program. Thus, for example, if a jump is made with 32 bits replaced, there are eight possible adjacent positions that can be jumped. Each depends on the value from the computational core. In other words, this is a jump that can be programmed.

[Operation Core]

As shown in FIG. 8, arithmetic core 219 includes a storage device called a register file 221, an arithmetic and logic unit (ALU) 222, an input port 223, and an output port 224. These elements are connected via buses and multiplexers. As mentioned above, the multiplexer that defines these elements and their connections is fully controlled by the micro sign instruction indicated by state machine 218. Operational and logical unit (ALU) 222 and ports 223 and 224 are conventional, but register file 221 is a storage device that allows indexed access of variable width. The address in register file 221 is encoded directly into a micro code instruction.

There are many advantages to using this method of addressing a register file. Firstly, many locations of the application do not have to be the full width of the storage device (in this case 32 bits). While this has no effect on the operation of the device using full width locations, this is a significant waste of storage location. Minimizing the number of storage locations will minimize the amount of space used by the storage device. Thus, it will be to minimize the load of capacity in the register file. This maximizes the speed of the register file. Secondly, indexing coupled to the variable width of the accessed storage device allows skipping through the variable width locations. In the case of one bit, this allows a good transition of long division and multiplication.

Thus, in summary, a process for addressing a storage device having the following steps is described. (1) Provide a fixed width word having a predetermined fixed number of bits used for addressing variable width data. (2) Define an address field that provides a fixed width word having a width defining a field and a width defining a field having at least one bit used as an end indicator. (3) Define an address field with a plurality of bits that address the data. (4) While varying the width defining the field and address field, define a field that is directly related to the size of the variable width data, and vary the number of bits within the width to maintain a fixed width word for addressing the variable width data. Change the bit size in the address field that is inversely related to the size of the variable-width data. In addition, a process for addressing a storage device having the following steps is described. (1) Provide a fixed width word having a predetermined fixed number of bits used for addressing data. (2) Define fixed-width words and replacement fields with address fields. (3) Define an address field with a plurality of bits that address the data. (4) Define a variable width replacement field having at least one replacement bit. (5) The replacement field has at least one bit used as an end indicator between the address field and the replacement field. (6) While changing the width of the address field and the width of the replacement field in reverse, use a replacement field that represents bits replaced from separate addressed sources, and maintain a fixed width word for addressing in variable width data. In addition, the processing for addressing variable width data in the storage device is described as the following steps. (1) A storage device having words of a predetermined width composed of words of a portion is provided. (2) Cycle the word of the part that is accessed with the bit recognized as the least significant bit. (3) The remaining part of the word is expanded so that the accessed word is recognized as the word of the part. (4) The remaining part of the word is returned until the word of the part returns to the original point, and the word is circulated.

[Detailed Description of Invention on Data Conversion Using Joint Processing Block]

This embodiment according to the present invention relates to a signal conversion method from a frequency band to a time band and a digital circuit configuration for performing the conversion.

Increasing the amount of information and transmission speed at the same time is a common goal in the field of electronic communications. However, each communication medium exceeds the transmission speed limit, as is the hardware of the transmitter which must process the transmitted signal. For example, telegraph lines are typically a much faster medium for transmitting information than mail, although typing and reading mail is faster than tapping the telegraph key.

For example, a message that has the same content will take longer to deliver to a processed message than to a simply processed message. The fastest transmission and reception speeds are achieved by compressing the data to be transmitted to process the data as quickly as possible at both the transmitter and the receiver, and then using a high-speed transmission medium, which often means reducing and eliminating system bottlenecks.

Digital TV is an essential application for transmitting large amounts of data at high speed. While universal TV systems use analog radios and electrical signals, digital TV transmission systems convert analog signals to binary 'numbers' to control the luminosity and hue of each matrix pixel ('pixel') displayed on a television screen. This generates a digital representation of the image of the luminance and hue of the pixel. Modern digital encoding schemes and hardware architectures are typical of information transmissions for much higher reasons than conventional analog transmission systems. Digital TVs, for example, are capable of achieving much higher resolutions and vivid images than are realized in universal analog. Digital TV systems, including so-called HDTV systems, are expected to replace common analog TV technologies. In many parts of the industrialized world, the conversion from analog to digital imaging for transmission and storage within 10 years will be the same as the recent replacement of analog audio records to compact discs (CDs).

In order to increase the general utility of digital image technology, standardized digital image encoding schemes have been adopted. In the past, the standardization method was known as JPEG, which is used for still images. There are currently two standards for processing moving images, MPEG and H.261, both of which perform in a manner similar to JPEG for each series of frames in a moving image.

It works by using the well-known fact that there is little change between frames based on the difference between successive frames to have an advantage over simply using JPEG repeatedly. Transmitting and storing information based on this “difference” requires less time and space than transmitting and storing still images, assuming that the closest frames in time are not alike.

For convenience, all of the standard methods used today are computed by dividing an image into tiles or blocks, each block consisting of a single image with a width and height of eight pixels. Each pixel is represented by three (or more) digital numbers known as its "components." There are many ways to convert colored pixels into components, for example YUB, YCr, Cb, and RGB. All of the common JPEG-like schemes operate on individual components.

Information relating to the highest frequencies can usually be omitted, with little to no human detriment to the image. 8-by having spatial information (e.g., transient real values) in order to have the ability to reduce the information in the picture by removing high frequency information without any loss of information to the human eye. The -8 pixel block must be transformed to obtain frequency information using an appropriate method. The JPEG, MPEG, H, 261 standard methods all use 8-by-8 spatial matrices to calculate 8-by-8 frequency matrices using the known discrete cosine transform (DCT).

As described above, the input data represents a square image. The transformation applied when converting the input data into the frequency band must be two-dimensional, and it is difficult to calculate such two-dimensional transformation effectively. However, the well-known two-dimensional DCT and its Inverse Discrete Cosine Transform (IMT) have a "separable" characteristic. Rather than necessarily solving 64 pixels in an 8-by-8 pixel block at the same time, it is possible to first convert the block to column-by-column to get the median and then to convert it to row-by-row to get the frequency value. .

The one-dimensional N-th order DCT is mathematically equivalent to the multiplication of two N-by-N matrices. To perform the matrix multiplication required for 8-by-8 pixel blocks, 512 multiplications and 448 additions are required. Thus, 1024 multiplications and 896 additions are required to fully perform the two-dimensional DCT of the 8-by-8 pixel block. This logical operation is particularly complex and slow in multiplication and thus places a limit on the achievable transmission rate. In addition, significant space is required within the silicon chip implementing the DCT.

The DCTs can be reordered to reduce the amount of computation required. Currently, two methods are used to reduce the computations required for DCT, both of which use binary decimation. The term binary decimation means that an N-by-N transform can be calculated using two N2-by-N2 transforms and some calculations needed to clean them up. The 8-by-8 transform requires 512 multiplications and 448 additions, while the 4-by-4 transform requires 64 multiplications and 48 additions. In other words, binary decimation saves 284 multiplications and 352 additions, and the computation involved in performing decimation is almost negligible compared to the reduction in computation.

Currently, the two main methods of binary decimation are 'A New Algorithm to Compute the DCT' IEEE Transaction on Acoustics, Speech and Signal Processing, Vol.Assp 32, No 6, p 1243 December 1984) and Wen-Sung Chen ( A Fast Computational Algorithm for the DCT, Wen-Hsiung Chen, C, Harrison Smith, SC Pralick, IEEE Transaction on Communications, Col. Com 25, No. 9 1004, September 1977). Lee's method takes advantage of the symmetrical nature of the ICDT's definition, which uses a simple characteristic of cosine to define a method for circular binary decimation. Lee's method is only suitable for IDCT.

Chen's method takes advantage of the properties of a recursive matrix where the matrix is reduced to only a diagonal matrix. This method provides a simple binary decimation of the DCT using the known properties of the diagonal matrix.

The serious disadvantage of the Li and Chen method is that it is not balanced in terms of when multiplication and addition should be performed. Both of these methods inevitably require a lot of addition followed by a lot of multiplication or vice versa. Therefore, when implementing Lee and Chen's method in hardware, parallel operation of an adder and a multiplier becomes impossible. This reduces speed and efficiency in that the ideal use of hardware is achieved when all adders and subtractors are always available.

Another drawback of conventional methods and apparatus for performing DCT and IDCT operations is that they are often difficult to handle so-called normalization, and add an additional symbiosis time when all multipliers are used with known architectures. There is a need.

Among software designers who do not need to be concerned with the layout of the circuitry that performs the calculations, it is known that some methods are very simple and efficient to apply forward or reverse DCT to video data. However, such methods are too slow and complicated to perform satisfactorily at the transmission rates required for digital video in semiconductor circuitry and hardware branch connections.

Another disadvantage of the actual method and hardware architecture, which performs DCT and IDCT operations on video data, is that floating point internal notation is required to represent numbers. To illustrate this disadvantage, suppose you have a calculator that can handle only three digits, including the one to the right of the decimal point (if any). Also, suppose you use this calculator to add 12.3 and 4.56 (note that the decimal point is not fixed relative to these two cocks. In other words, the decimal point can move). Since the calculator cannot store the four digits necessary to give a 12.86 answer, the answer is rounded down by removing the rightmost '6' to reduce the answer to three digits. You must have the hardware necessary to round up to get 16.9.

As this simple example shows, if floating point operations are needed, either a loss of accuracy or a very complex and space consuming circuit must be in place to minimize the alignment error. Even in efficient justification circuits, the accumulation and progression of errors due to rounding or rounding results in unacceptable distortion in the video signal. This problem is exacerbated when the video signal processing method requires several multiplications (as rounding or rounding errors are generally greater in multiplication than addition).

The highly efficient DCT / IDCT method and hardware architecture will ensure that the numbers used in this method can be represented in the full dynamic range of each number while using fixed-point notation. In such a system, the rounding or rounding error will be eliminated or at least significantly reduced.

In the example above, if the hardware can handle four digits, then numbers above 99.99 will not be needed and all numbers will have a decimal point between the second and third digits, which will not affect the calculation at all. Thus, the operation can be handled as if all numbers are integers. In other words, 1230 + 0456 = 1686 is equivalent to 12.30 + 4.56 = 16.86 because it knows that “1686” must have a decimal point between 6 and 8 in the middle. Or, if a number (either constant or not) is selectively scaled or adjusted to fall within the same area, each number in that area can also be represented accurately and clearly in the form of an integer.

One way to reduce the number of multipliers needed is to simply have a multiplier that can accept input data from other sources. In some structures, one multiplier is used to perform the multiplication required in other processes of DCT and IDCT calculations. Although such crossbar switching reduces the number of multipliers required, it instead has a large and complex multiplexer structure that selects the input of the multiplier, isolates other circuits from the multiplier, and connects the multiplier with the correct signal from the selected source. It must be included. Additional large multiplexers are also required to connect a large number of outputs from the shared snowbox to the appropriate subcircuits. Thus, crossbar switching or multiplexing is complex and generally slow (since additional storage is required), which is expensive to implement the final semiconductor circuit.

Another decision of the actual structure, including crossbar switching, is that it requires a general purpose multiplier. In other words, a real system needs a multiplier where both inputs are variables. As is well known, implementations of digital multipliers typically include adders and shifters so that if the current bit of the multiplier word is' 1 ', the multiplicand value is added to the partial sum, but the current bit is' 0 'does not. Since a general purpose multiplier must be able to cope with all bits being '1', every bit of a multiplier word must have an adder string.

For example, suppose a data word is 8 bits wide and you want to multiply single inputs by 5. The 9-bit notation of 5 is 00000101. In other words, a digital process of multiplying by 5 simply shifts the input to the left two digits (corresponding to the product of 4) and then adds itself to the shifted value.

The remaining six digit coefficients have a bit value of '0', so no movement or additional steps are required. The fixed-coefficient multiplier, in this case, performs a multiplier that can only multiply '5', multiplying (ignoring the circuitry needed to handle carry bits), and only requires one shifter and one adder. A general purpose multiplier, on the other hand, requires a shifter and an adder in each of the eight positions, but not two of them. As can be seen from the example, fixed coefficients can simplify the multiplier because the designer can remove the adder zero of the portion of the coefficient equal to zero, thus saving the area of the silicon circuit.

In the IDCT method according to the present invention, 1-D IDCT for each of N columns and N rows of an N-by-N pixel block is decimated, and 1-D is applied to each of N-2 even pixel input words and N-2 or pixel input words. D Perform IDCT.

In the example raised, N = 8 according to the JPEG standard. Two-dimensional IDCT results are obtained by performing two one-dimensional IDCTs in turn (intermediate reordering-transposition of data).

In the coprocessing step, when N = 8, the first pair of input values are passed to the output adder and subtractor without the need for multiplication. Each second pair of input values is multiplied by two constant coefficients each according to the scaled cosine value. There is no further multiplication in the co-processing phase, only one subtraction and one addition are required. The second pair is then added to or paired with the first pair of inputs to produce an even or odd result.

In pre-co-processing, least-order odd input words are premultiplied by the square root before being processed in the joint processing block, odd-numbered input words are premultiplied by the square root before being processed in the joint processing block, and odd input words are added in pairs. . In the post-joint processing stage, the intermediate value according to the processed odd input value is multiplied by a predetermined constant coefficient to form an odd result value.

After calculating the even and odd results, the N / 2 higher order outputs are made by simply subtracting the odd result from the even result, and the N / 2 lower order outputs are made by simply adding the odd result from the even result. .

For DCT (at the transmission end of a video processing system) and IDCT (at the output end in various aspects of the present invention), the values are scaled down by factor 2 by deliberately simple binary right shift as needed.

This deliberate and balanced upscaling eliminates several multiplication steps if required according to a universal method.

Another aspect of the method according to the invention is that the data words calculated in the selected bit or intermediate of the constant coefficients are rounded or manipulated in such a way as to preset the selected bit to '1' or '0'. Two-dimensional transformation of the pixel data is performed by performing a second same operation on the output of the first 1-D IDCT processing step.

As another aspect of the present invention, an IDCT system includes a pre-co-processing circuit and a co-processing circuit for performing pre-co-processing, co-processing and post-co-processing calculations on input data. A supervisory controller generates control signals for controlling the loading of various system latches, instructing the addition of even and odd result values for the formation and latching of lower order output signals as needed, or the formation of higher order output signals. And time-multiple of the N / 2 even or N / 2 odd inputs in the input latch of the co-processing block, such as instructing the latch to subtract the odd result from the even result, or sequentially controlling the internal multiplexer. You will apply the flex.

In the present invention, even and odd input words are processed such that they each pass through a joint processing block whenever possible. The input words are latched in order to enable (but not necessarily) exactly, but not in ascending or descending order, an efficient "butterfly" structure in the data path.

In addition, at least the co-processing circuit is a pre-logic circuit, which can be formed without the need for a clock or control signal for its proper operation, which may be possible in other processing blocks depending on the particular application.

A general purpose multiplier (two variable inputs) is not necessary. Rather, a constant coefficient multiplier is included throughout the claimed embodiments. In addition, the embodiment of the present invention includes a fixed-point logic device, and is designed to provide a method and a system for performing IDCT transformation on video data.

1. Constant use of all costly operations.

2. To reduce the area of silicon circuitry required to implement IDCT, have a small number of storage elements (such as latches) and preferably smaller than general-purpose multipliers that require no other storage elements than the number needed for an efficient pipeline of structures. Combined with a constant multiplier of numbers.

3. Each operation is tuned to eliminate the need for complicated designs. For example, even if a 'ripple adder' is used, these operations will allow enough time to transform and solve the answer: that is, other devices may be able to precede the recalibration operation with high computation and efficiency to avoid delays. If the calculation is adjusted to

4. You can produce results in a natural order.

5. Inexpensive and uncomplicated crossbar switching is required.

6. The structure can support much faster operations.

7. The circuitry used to control the flow of data through the conversion hardware takes up a small area.

[Theoretical basis of invention]

In order to understand the purpose and function of the various components used in the IDCT system and the advantages of the signal processing method, it is helpful to understand the theoretical basis of the system.

[Separation of 2D IDCT]

The mathematical definition of the two-dimensional forward DCT for N × N blocks of pixels is as follows. U (j, k) is a pixel frequency value according to the pixel absolute value X (m, n).

Equation 1:

Where j, k = 0,1 ..., N-1,

c (j), c (k) = 1 / If j, k = 0: 1 otherwise

2N determines the DC level of the transform, and the constants c (j) and c (k) are well-known normal factors.

IDCT according to this is as follows.

Equation 2:

Where j, k = 0,1 ..., N-1,

c (j), c (k) = 1 / If j, k = 0: 1 otherwise

Forward DCT is used to convert spatial values (directly expressing luminosity-like characteristics or representing differences, as in the MPEG standard) into frequency band representations.

As its name implies, reverse DCT (IDCT) is a transformation of another 'direction', that is, a frequency value back into a spatial value.

Note that in Equation 2, the cosine function is a function each related to only one of the summation indices.

Therefore, Equation 2 can be summarized as follows.

Equation 3:

This equation is the first one-dimensional IDCT performed on the product of all terms related to k and n, followed by a straightforward standard data transposition by a second one-dimensional IDCT using the result of the first-order IDCT operation. same.

[Definition of 1-D IDCT]

One-dimensional N-point IDCT (when n is even) is defined by the following equation.

Equation 4:

Where k = 0,1 ..., N-1,

c (n) = 1 / n = 0 otherwise 1

Where y (n) is N inputs to the inverse transform function, and x (k) is N results accordingly. As in the case of 2-D, the equation for DCT had the same structure under the sum sign. However, the normalization constant is outside the sum sign and the x and y vectors are inverted.

[Resolution of 1-D IDCT]

As shown above, 2-D IDCT can be calculated sequentially using 1-IDCT processing separated by transpose. According to one method, each of these 1-D processes is broken down again into sub-procedures, which were developed to reduce the complexity and size required in semiconductor circuit implementation.

[Normalization of coefficients]

As discussed earlier, IDCT hardware is an important goal in design to reduce the number of multipliers that must fit into the circuit. Therefore, almost all methods of calculating DCT and IDCT attempt to reduce the number of multiplications needed. However, according to this embodiment, all input values are deliberately upscaled by a square root factor. In other words, according to the present invention, the right term of the IDCT equation is deliberately multiplied by the square root.

In accordance with an embodiment of the invention, the final 2-D IDCT processing is processed in order (via intermediate transposition). Each of these 1-D treatments equally includes a square root factor. Since there is no scaling in the intermediate transposition, the result of two sequential multiplications by the square roots results in the final 2-D scaling up to a factor of two. To get an unscaled value, simply divide by two in the circuit. Since all values are represented digitally, this process can be easily performed by simply moving the data to the right. A more detailed description and explanatory detail later, the upscaling by the square root and the downscaling by 2 in each 1-D IDCT stage, ensures that the system does not need to make scaled inputs to another device to which it is connected. This is done by adders, multipliers, and shifters in hardware. For this reason, the system is compatible with other universal devices that operate according to the JPEG or MPEG standards. Thus, the normalization according to an embodiment of the present invention eliminates the need for a hardware multiplier in the IDCT semiconductor structure to perform the operation of multiplying at least two square roots. As detailed later, an additional multiplication step (upscaling to the square root) of one 1-D motion input data obviates the need for another multiplication required when using the universal method.

[Separation of Higher and Lower Order of 1-D IDCT]

Equation 4 now shows N / 2 lower order outputs (k = 0,1 ..., N / 2-1) and N / 2 higher order outputs (k = N / 2, k = N / 2 + 1, .. It can be obtained separately by .N). If N = 8, first convert the input to compute y (0), y (1), y (2), y (3), then y (0), y (1), y (2), We just need to convert the input to compute y (3).

Variable k '= (for higher order output (k = N / 2 + 1, ... N), changing from (N / 2-1) to N as k changes from (N / 2 + 1) to N N-1-k) is introduced. If N = 8, then k '= (3,2,1,0) for k = (4,5,6,7). Then, Equation 4 may be divided into two sub-expressions of Equation 5 (the same as Equation 4 except for the summation interval).

Low order output:

Equation 5:

Where k = {0,1 ..., (N / 2-1)},

c (n) = 1 / n = 0 otherwise 1

Higher order output:

Where k = {N ..., (N / 2 + 1) → k ′ = 0,1 ..., (N / 2-1)},

(C (n) is not included in this expression because c (n) = 1 in all higher terms)

In both Equations 5 and 6, when the odd input (odd n) for the upper N / 2 output value within the sum code, the (-1) n term changes the sign of the products in the sum code, and the y term is c (0) = 1 / Notice that it has the same structure except multiply by.

[Isolation of 1-D IDCT into Even and Odd Terms]

Note that the single sum of 1-D IDCT in Equation 4 can be separated into two sums. One for even-numbered inputs (y (0), y (2), y (4), y (6) when N = 8) and one for odd-numbered inputs (y (1), y ( 3), y (5), y (7)). Suppose g (k) represents a partial sum of even-numbered inputs and h (k) represents an odd-numbered inputs.

then :

Equation 7.

Where k = {0,1 ..., (N / 2-1)}

Equation 8.

Where k = {0,1 ..., (N / 2-1)}.

When N = 8, make sure that the synthesis of equations 7 and 8 were both performed for n = {0,1,2,3}.

Recall the known cosine properties:

2, cosA, cosB = cos (A + B) + cos (A-B)

Where A = π (2k + 1) / 2N, B = π (2k + 1) (2N + 1) / 2N

Both sides of Equation 8 can be multiplied by

2 · cosA = 1 / {2 · cos [π (2k + 1) / 2N]} = Ck

Note that Ck is not related to the sum index n, so it can be indented within the sum code. Note that by definition y (-1) = 0, the cosine function for input y (7) is zero. Then, the expression for h (k) can be rewritten in the form

Equation 9.

Where k = {0,1 ..., (N / 2-1)}.

Input [y (2n + 1) + y (2n-1)] is the odd input term when calculating h (k). N / 2 pairs of input p (n) = [y (2n + 1) + y (2n- Note that they are grouped together to form 1)].

If N = 8, the p (n) value is as follows.

Therefore, Equation 9 expressing h (k) can be expressed as follows.

Equation 10.

Where k = {0,1 ..., (N / 2-1)}.

Note that the cosine term in the sum code is the same for both g (k) and h (k) and has the structure of 1-D IDCT (compared to Equation 5). As a result, h (k), the result of IDCT for odd k terms, is a factor

It is multiplied by Ck = 1 / {2 · cos [π (2k + 1) / 2N]}.

In other words, g (k) is an n / 2 point IDCT that handles even input y (2n) and h (k) is [y (2n + 1) + y (2n-1)] (y (-1) IDCT of n / 2 points).

Now introduce the following properties:

yn = y (n);

c1 = cos (π / 8);

c2 = cos (2π / 8) = cos (π / 4) = 1 / ;

c3 = cos (3π / 8);

d1 = 1 [2.cos (π / 16)];

d3 = 1 [2. cos (3 [pi] / 16)];

d5 = 1 [2.cos (5π / 16)];

d7 = 1 [2.cos (7π / 16)];

Let's introduce more scaled coefficients as follows:

c1s = cos (π / 8);

c3s = cos (3π / 8);

Using cosine function, right function property (cos (-φ) = cos (φ) and periodicity (cog (π-φ) =-cos (φ)), It can be described as follows. (c (0) is 1 / Recall that

Recall that now all values are scaled up to factor 2 in both DCT and IDCT operations in accordance with an embodiment of the present invention. In other words, according to the embodiment both h (k) and g (k) are multiplied by this scaling factor. Thus, the expressions for g (k) and h (k) are as follows.

Equation 11.

Equation 12.

c2 = cos (π / 4) = 1 / Because Note that by multiplying the value of scaled c2 is 1. By the scaling expression according to the present embodiment (according to the upscaling of the absolute value of the video and the frequency value), the constant coefficients c1s and c3s do not need to be multiplied, nor do they need a general purpose multiplier. This in turn eliminates the need to create a hardware multiplier accordingly when implementing semiconductor circuits for IDCT processing.

The similarity of g (k) and h (k) structures can be seen by representing a set of equations in matrix form. Define C as a 4x4 cosine coefficient matrix:

Equation 13.

Equation 14.

Equation 15.

Here, D = diag [d1, d3, d5, d7] is a 4 × 4 matrix with d1, d3, d5, d7 along the diagonal, and the other elements are zero. As shown in equations (14) and (15), the order of processing even-numbered inputs to obtain g (k) and the order of odd-numbered inputs to obtain h (k) commonly include multiplying the cosine coefficient matrix C. . However, to get h (k), the inputs must first be added in pairs (defined as y (-1) = 0) and y (1) must first be multiplied by two.

As the previous expression indicates, N-point 1-D IDCTs (see Equation 4) can be divided into two N-points, with each 1-D IDCT having N / 2 odd inputs (grouped) and N / 2 even numbers. It goes through a common core operation (under the minus sign) of the input.

The above expression provides the following simple structure for the IDCT implemented by this embodiment.

Lower order output (N = 8, output k = {0,1,2,3});

Equation 16.

y (k) = g (k) + h (k)

Higher order output (N = 8, output k = {4,5,6,7});

y (k) = 1 (N-1-k ′) = g (k ′)-h (k ′)

g (k) processes the even inputs directly in order to provide the output directly, while h (k ') goes through the grouping of inputs as well as the multiplication by d1, d3, d5 and d7 values.

As always, IDCT circuit designers face a balance between the size and speed of the circuit, the number of instruments to be implemented and the complexity of the extension connection. For example, the computational speed is often improved by using additional and more complex devices in silicon chips, but the circuits are larger and more complex. In addition, the question of what is available or what is needed on an IDCT chip limits and excludes the use of difficult and complex designs such as "look-ahead" adders.

[Standard of Accuracy]

Given the infinite precision and accuracy of all calculations, i.e. unlimited storage and calculation time, images reproduced with IDCT's DCT-converted image data can reproduce the original images perfectly. Of course, such accuracy is not attainable with current technology.

For some standardization, the IDCT system is currently measured according to the standardization method proposed by (Comite Consultatif International Telegraphique et Telephonique ('CCIT') in 'Annex 1 of CCITT Recommendations H.261-Inverse Transform Accuracy Specification'). . This test specifies that a set of 10,000 8-by-8 blocks with irregular integers will be generated. The blocks then perform DCT and IDCT transformations (pre- and post-defined rounding, clipping and logic operations) with a predefined precision that produces 10,000 8-by-8 'reference' IDCT output data.

When testing an IDCT implementation, the CCITT test block is used as input. The actual IDCT transformed output is then statistically compared with the 'reference' IDCT output data. Maximum values for IDCT are specified for peaks, means, squares of means, and block error means for the whole or individual elements. In addition, if all input blocks are 0, IDCT should output all 0s, and if all input data codes are changed, IDCT should come out with the same standard.

When these tests were performed, it can be said that the implementation of IDCT had acceptable accuracy only when their maximum errors did not exceed the specified maximum.

Other known standards are those specified by the IEEE ('IEEE Draft Specification for the Implementation of 8 by 8 Discrete Cosine Transform', P1180 / D2, July 18, 1990; and Annex A of '8 by 8 Inverse Discrete Cosine Transform' ,. ISO commitee Draft CD 11172-2). These standards are essentially the same as the CCITT mentioned earlier.

[Hardware implementation]

9 shows the data flow of the IDCT method according to one embodiment of the present invention (although the hardware structure is more compact and efficient as shown and described later). In Figure 9 it is shown that the inputs of systems such as Y [0] and Y [4] and the outputs of systems such as X [3] and [6] are delivered on a single line. The lines drawn in one line in FIG. 9 represent conductors in the form of data buses carrying as many bits of words as possible in parallel to determine the input and output.

In FIG. 9, large circles 225 and 226 are two-input adders, and small circles 227 at the intersection of input and adder indicate that the complement of the input word is used. An adder that uses the complement of the input, in other words, subtracts the complemented input from the non-compensated input. For example, the output of the top left adder is T0 = Y0 + Y4, but the adder that gets the output of T1 gets the output of T1 = Y0-Y4. Thus, an adder that takes a complement of input can be said to be a component that finds the difference.

Also in Figure 9, triangle 230 in the data path is a constant multiplier. For example, input Y1 goes through a square root multiplier before entering the adder to make B0. As a result, the median values T3 = Y2 · c1s + Y6 · c3s and B2 = p1 · c3s-p3 · c1s = (Y! + Y3) · c3s- (Y5 + Y7) · c1s. You will see a structure that implements Equations 11 and 12 for g (0) to g (3) and h (0) to h (3) by performing the indicated addition, subtraction, and multiplication.

9 shows the important advantages of the embodiment according to the invention. As shown in FIG. 9, the structure is divided into four main parts: a pre-joint block that forms a paired input p (k) and multiplies the input y (1) by the square root; A first order post-joint block POSTC1 233 comprising a constant d1, d3, d5, d7 multiplier (see equation 12);

A second post-co-block POSTC2 235 to find the difference between the sum of the low order output g0 and g3 and the h0 to h3 terms and the higher order output of g0 and g3 and h0 to h3 terms; And a common block CBLK 232. both of which are included in the even and odd data paths. In the processing circuit according to the embodiment of the present invention, the co-operation performed on the odd or even inputs is performed by a single structure rather than a duplicate structure shown in FIG. Is performed by.

It is a great help to understand what the carry bits are in understanding the advantages of the computational methods and the given digital structures used in this embodiment. As a simple example, let's look at the addition of two binary numbers to create a carry "1" that is added to the next higher order term to produce the correct result "10" (binary representation of decimal 2) with 1 + 1 = 0. In other words, the carry word is summed to 01 + 01 = 00 (without carry) to get the correct answer 00 + 10 = 10.

For example, suppose we need to add "436" and "825." A common way of adding two numbers by hand generally proceeds as follows.

1. Place of work: '6' plus '5' becomes '1' with '1' in the ten's place.

Total: 1, carry-in: 0, carry-out: 0

2. Decimal place: '3' plus '2' plus carry '1' raised from the previous step to become '6' without carry

Sum: 5, Carry-in: 0, Carry-out: 0

3. The seat of the hundred: '4' plus '8' is the thousand seats, carry '1' to '2', and carry does not rise in the previous stage.

Sum: 2, Carry-in: 0, Carry-out: 1

4. Thousand seats: '0' plus '0' plus '1' from the hundred's seat to become '1'.

Total: 0, carry-in: 1, carry-out: 0

In other words, the answer '1261' is made by adding the carry-in of the adjacent lower position and the sum of the positions. (Which means that the carry-in at the lowest position is always '0'). The problem, of course, is that you have to wait to add the hundreds '4' and '8' until you find out if there is a carry-in made from the tens. This is essentially a description of the ripple adder that performs this type of operation. Thus, the ripple adder can get the final answer without the need for a separate storage element but is slower than other designs.

Another design approach is the "carry-save" approach, which adds two numbers to each digit formed by storing a subtotal, that is, a result word (0251 in this example) and a carry value of another word. The complete answer is obtained by transforming this sum and carry word into the following addition step, 0251 + 1010 = 1261. As long as the subtotals are stored, the addition of all the digits can be performed simultaneously in each digit without having to wait for the determination of whether the carry word can be added to the subtotal.

This transformation operation generally takes most of the time required for each calculation step, so making this operation faster affects the overall operation speed, while the increase in transform size is relatively small. Thus, a carry-save multiplier is usually faster than using a ripple adder for each column. However, this temporal gain causes increased complexity because the carry word for each addition of the multiplier must be stored or passed through to the next addition. Furthermore, to get the final result of the multiplication, the final subtotal and the final carry word must be modified, usually by the addition of the ripple adder. Note, however, that only one ripple adder is needed to realize a reduction in computation time that is proportional to the size of the multiplication being performed. Moreover, note that the carry word can be treated like any other number to add, and that the actual addition can be delayed as long as it is added at some point before the final multiplication answer is needed.

In an embodiment of the present invention, the possibility of delay of deformation is used to simplify the design and increase the throughput of the IDCT circuit. In addition, any bits of the preselected carry word are deliberately predetermined values as needed to provide the high accuracy expected for the IDCT results based on the statistical analysis of the test run of the present invention on a standard test data set prior to the transformation step. Will have

10 is a block diagram showing the structure raised above in accordance with the present invention. In the embodiment posed by the present invention, even and odd inputs are time-multiplexed and processed separately in coblock CBLK 232. Input can be processed in each order.

In FIG. 10, Y [1,0], Y [5,4], Y [3,2], and Y [7,6] are represented by the odd-numbered inputs Y1, Y3, Y5, and Y7. This is used to indicate that the odd-numbered inputs Y0, Y2, Y4, and Y6 are passed through behind. However, although this order is not inevitable in this embodiment, according to the description below, some downstream logic is performed only on odd-numbered inputs. By putting odd input values first, the logic operations common to all these inputs can be processed simultaneously with the upstream inputs to even inputs. This approach reduces the time that some logic units sleep if not implemented.

Similarly, X [0,7], X [1,6], X [3,4], and X [2,5] are the low order outputs X0, X1, X2, and X3 first, followed by the higher order outputs X4, X5, Used to indicate that X6 and X7 follow. As shown in Figures 9 and 10, although the odd-numbered inputs are Y1, Y5, Y3, Y7, this is not necessary, but the inputs are not initially tied in ascending order. Arranging the input signals in this order enables the simple “butterfly” data paths shown in FIGS. 9 and 10 and greatly increases the efficiency of the extension connections of embodiments of the present invention in silicon semiconductor devices.

As shown in Fig. 10, the adder and the subtractor have a '+' (adder, 235) and one input in the circle, '-' (subtractor, 236) and '±' (addition and subtraction, switchable variants). Adder 237). The leftmost adder and subtractor of the common block 232 of two m-bit input words is the m-bit partial result in parallel with the m-bit or (m-1) bits, including the carry bits of the add / subtract. In other words, the first addition and subtraction of the joint processing block CBLK 232 is not modified as much as possible, which means that the carry bit addition is delayed until the subsequent processing stage. The advantage of this step is that the carry-save add / subtractor does not need to perform the final addition of the carry bit word. Modified adders can also be used to reduce the bus width at the adder output.

10 shows the use of one and two latches in an embodiment addressed by the present invention. In FIG. 10, the latches are indicated by rectangle 288 and are used for both pre-co-block PREC 231 and post-co-block POSTC 233. Latches g [0,7], g [1,6], g [3,4], g [2,5] and h [0,7], h [1,6], h [3,4], latches inputs resulting from g (k) and h (k) from the output expected from h [2,5] into resolving adders / subtractors, multipliers D1, D3, D5 It is also used as an input to D7. The transform adder / subtracter performs addition / subtraction as expressed in Equations 16 and 17 above.

As mentioned earlier, even-numbered inputs Y0, Y2, Y4, Y6 do not need to be paired before being processed in the co-processing block CBLK 232. However, it is not only necessary to pair odd-numbered inputs, but input Y12 must also be multiplied by two square roots to ensure that the proper input values appear in co-processing block CBLK 232. Thus, the pre-joint block PREC 231 includes two-input multiplexing latches C10, C54, C32, C76 for each input value. The other input is received from the modified adder and the modified quadratic root multiplier for input Y1, while one input of the two-input multiplexing latch is immediately attached to the unprocessed input value. Thus, the correct paired or unpaired inputs can easily be represented in the common block CBLK 232 by simply switching the multiplexing latch between those two inputs.

In FIG. 10, the square root multipliers D1, D3, D5, D7 transform their output as much as possible. That is, a carry bit is added to find a perfect sum. This ensures that the output of the multiplier has the same width bus as the unmultiplied input of each parallel data path.

Embodiments posed to joint block 232 in accordance with the present invention also include one dummy subtractor 240 each in the forward data path of Y [1,0] and Y [5,4]. These devices work by mixing two inputs that pass in the same way as a parallel output (in the case of a dummy subtractor, after a two's complement to one input). In each case one input is manipulated as it is one input as if it has a carry bit, which is added in subsequent processing steps. Although delayed, addition and subtraction are performed accordingly.

This technique reduces the resources required for the above two data paths because these devices do not require a full scale adder / subtractor. Thus, the mixer operates like an adder or subtractor, and for these devices, it can be implemented as a simple conductor (on addition) or inverter train, which requires little additional review on the next device.

The use of this mixer is also compatible with the output of the carry-save adder / subtracter under the two data paths, with the outputs of the initial adder and the subtractor in the common block CBLK 232 all the same width. This means forming the input of the modified adder / subtractor of the joint block CBLK.

As described above, in the embodiment posed by the present invention, the even-numbered input is processed separately from the odd-numbered input. Furthermore, suppose that odd-numbered inputs are processed first. The overall control circuit (shown in FIG. 10) applies an odd-numbered input word to the pre-joint block PREC, and stores multiplexing latches C10, C54, which store the values p0 to p3 (shown in FIG. 10) as current pairs. Select the lower input of, C32, C76. Latches 1h0, 1h1, 1h3, 1h2 are then activated to latch H0, H1, H3, H2, respectively.

The overall control circuit latch then selects the higher order inputs of the two-input multiplexing latches C10, C54, C32, C76 of the pre-joint block PREC 231, and applies even-numbered input words to these latches. Since even-numbered inputs are used to form the values of g0 to g3, the overall control circuit also opens Lg3 at latch Lg0 of post-joint block POSTC 233 to store the g (k) value.

Once the g (k) and h (k) values are latched, the post-joint block POSTC 233 converts the transform add / subtracter to the subtraction mode and outputs the higher order signals X7, X6, X5, X4. The lower order output signals X3, X2, X1, and X0 are then generated by converting the modified adder / subtractor to the add mode. Note that the output data can come in any order, including natural order.

The multiplexing implementation addressed to this invention is shown to be quite simplified in the configuration of FIG. 10 and performs the same calculations as the non-multiplexing structure of FIG. However, the number of adders, subtractors and multipliers in the common block CBLK 232 is cut in half, and the dummy adder / subtracter 240 further reduces the complexity of expensive logic circuits.

11 shows main components and data lines that actually implement IDCT circuits according to embodiments of the present invention. The main components are the pre-co-block circuit PREC 231 and the co-block circuit CBLK 232. The system has a controller CNTL 241 which directly or indirectly inputs and controls signals to the pre-co-block PREC 231 and post-co-block POSTC 233.

In the embodiment posed by the present invention, the widths of the input and output signals (Y0 to Y7, X0 to X7 respectively) are 22 bits. This is the smallest width that can be tested to achieve the accuracy acceptable by current industry standards. As will be explained later, the minimum width is obtained by forcibly applying 1 or 0 to given carry words of a deliberately selected logic device.

As described above, bit manipulation according to adjustment of a given data word is performed by statistically analyzing the result of the IDCT system after using the IDCT change of the input test data known in the present invention. It is found that by forcing a bit into a predetermined value, the effect of rounding and rounding errors can be reduced so as to deviate from the exact spatial data known to the spatial output data of the IDCT system as little as possible. It became. The present invention is applicable to data words of different lengths because all of the components used in the circuit according to the present embodiment are designed to be applicable to other bus widths using known methods.

Although all four inputs processed together are simultaneously input to the pre-co-block PREC along 88 parallel conductors (4x12), the pixel words are generally turned into one at the same time from the transmitted data. Thus, according to this embodiment, the input data words are all delivered in series over a 22-bit bus, preferably with each input word sequentially latched at the appropriate input point in the data path. As shown in FIG. 11, the 22-bit input data bus is labeled T_IN [21: 0].

In the figure and the discussion below, the width of the multiple-bit signal is shown in parentheses, the higher order bits are to the left of the colon ':', and the LSB is to the right of the colon. For example, the input signal T_IN [21: 0] 242 is a 22-bit wide signal ordered from 0 to 21. A single bit is defined by a number in parentheses, so T_IN [1] points to the number following the LSB of the T_IN signal.

The following control signals are used to control the operation of the pre-joint block PREC 231 of the embodiment posed herein.

IN_CLD, OUT_CLK: The system according to the present invention uses two phase clocks where possible that no overlap occurs. The IN_CLK and OUT_CLK signals control the rows of latches that hold the input, intermediate and output signals.

LATCH10, LATCH54, LATCH32, LATCH76: Whenever possible, one word of 22 bits is input to the system. On the other hand, four input signals are processed at one time. Therefore, each input signal must be latched to the proper position in the structure before three different input words can be processed. This latch signal is used to enable each input latch. For example, the LATCH54 signal latches the first input signal Y5, and then latches the input signal Y4 which enters the same point in time as the input signal Y5 (see FIG. 10), although different in subsequent processing steps, in the pre-joint block PREC 231. Used.

LATCH: Once four even or odd input signals are latched into the pre-co-block PREC 231, they are moved simultaneously in rows of latches whenever possible. The signal LATCH is used to enable the second row of the input latch holding four input values to be processed by the logic unit of the pre-co-block PREC 231.

SEL_BYP, SEL_P: As shown in FIG. 10, even-numbered input signals latched into latches C10, C54, C32, and C76 must pass through the adder and the quadratic transform multiplier. However, odd-numbered input signals must first be paired to produce a paired input p (n), and signal Y1 must be multiplied by a square root. The control signal SEL_P must be activated to select the paired inputs. These signals are therefore used to control the gate acting as a multiplexer that allows the correct signals to be passed to the output latch of the pre-co-block PREC 231.

As discussed earlier, the need to sort the inputs in exactly ascending order enables a simplified “butterfly” bus structure with high efficiency extension connections. As described above, odd-numbered inputs are preferably applied to the pre-co-block PREC 231 as a group, and then even-numbered inputs are applied. However, any order may be used within each odd or even group. That is, any order of input may be used. However, an appropriate latch arrangement must be provided either individually to handle odd-numbered inputs, or at least on separate parts of the circuit.

The overall control circuit also generates a timing and control signal to the post-joint block POSTC 233. These control signals are as follows:

EN_BH, EN_GH: Referring back to FIG. 9, the output from the common block CBLK 232 which processed the odd-numbered input may be represented by H0, H1, H3, H2. These signals are sent to the coefficient multipliers d1, d3, d7, d5 of the first post-joint block POSTC 1 233, respectively. The signal EN_BH is used to enable the latches holding the signal h3 at h0 after they have been multiplied in the counting process, as well as to enable the latches holding the signal g3 at g0.

ADD, SUB: As shown in FIG. 10, this embodiment sets the modified add / subtractors to the addition and subtraction modes, respectively, by adding or subtracting g (k) and h (k), respectively, to form a lower order output. Used to

EN_O Used to enable an output latch that latches the result from the transform adder / subtracter.

MUX_OUT70, MUX_OUT61, MUX_OUT43, MUX_OUT52: According to the invention, the output data of the system is transmitted via a single 22-bit output bus as much as possible so that only one result value (X0 to X7) is delivered at a time. These signals are sequentially activated to select which of the four latched output values to send to the final output latch. Accordingly, these signals act like control signals of a 4-to-1 multiplexer.

T_OUT [21: 0]: This label points to the 22-bit output signal of the post-joint block POSTC 233.

The pre-joint block PREC 231 and the output signal are latched to form an input signal of the joint processing block CBLK 232. As shown in FIG. 11, the output signal of the pre-co-block PREC 231 is composed of four 22-bit data words CI10 [21: 0], CI54 [21: 0], CI32 [21: 0], CI76 [21: 0]. These are the input signals IN [0], IN [1], IN [3], and IN [2] of the joint processing block CBLK 232, respectively.

As shown in FIG. 12, four 22-bit results obtained from the joint processing block CBLK are parallel to the output signals OUT0 [21: 0], OUT1 [21: 0], OUT3 [21: 0], and OUT2 [21: 0]. They are then latched in as input signals to the post-joint block POSTC 233, such as CO70 [21: 0], CO61 [21: 0], CO43 [21: 0], CO52 [21: 0]. .

Special care should be taken that no control signal is required for the joint processing block CBLK. Because of the unique structure of the IDCT system of this example, the co-processing block operations of the system can be performed with pure logic without the need for clocks, timings, and control signals. This further reduces the complexity of the device. Also, in some applications (especially when there is sufficient time to perform the required logic operation) the pre-co-block PREC 231 and post-co-block POSTC 233 can be adjusted to operate without clock timing or control signals.

12 is a block diagram of the present invention. In this and subsequent figures, the notations S1 [a], S2 [b], ..., SM [z] indicate that S is an arbitrary signal label, and a, b, ..., z are integers within the bus width of the signal. It means that the bits (a, b, ..., z) selected from the signals S1, S2, ..., SM are transferred. At this time, MSB is selected bit a of signal S1 and LSB is selected signal z. The selected bit need not be a single bit, but rather can be transmitted with full or partial multibit words. In the figure, the symbol S will be replaced with the corresponding signal label.

As an example, in FIG. 12 a square root multiplier is shown as R2MUL. The save and unresolved sum of the non-resolving multiplier is represented by the 22-bit word M55 [20: 0]. Similarly, the output of the multiplier R2MUL is represented by the 22-bit word M5C [20: 0], which is passed over the bus to the input b of the carry-save modified adder M5A. Recall that (0 is inserted as the MSB in the least significant 21 bits of the save output, but this is done before being applied to the input a of the transform adder M5A. This is GND.M5S [20: 0] in FIG. 12). Revealed in the notation). In other words, the conductor corresponding to the MSB input of adder M5A is forced to zero by ground GND.

To understand why zero is inserted as the 22nd bit of the sum, we need to observe whether the subtotal of the multiplication has n widths or if the carry word is shifted one digit to the left of the subtotal. Thus, the carry word is extended to n + 1 digits with valid data in the LS digit, i.e., the n + 1 digit (because there is nothing in front of this digit that can produce a carry bit). If these two words are used as inputs to the modified binary adder, care must be taken to ensure that the bits of the carry word are properly aligned with the corresponding subtotal bits. This also ensures that the decimal point (though just imaginable in integer logic) remains aligned in both words. Assuming that the width of the adder's input is n + 1 bits, 0 can be inserted into the most significant bit of the n-bit positive subtotal to provide an n + 1 bit input aligned with the carry word of the other input.

As described above, four inputs processed at a given time in the pre-co-block PREC 231 are delivered via input bus T_IN [21: 0]. This input bus is connected to four input latches. Each latch is enabled only when the latch selection signals LATCH10, LATCH54, LATCH32, and LATCH76 corresponding to the input signal IN_CLK are high. Therefore, four inputs are latched into each input latch of four cycles of the IN_CLK signal by sequential activation of the latch enable signals LATCH10, LATCH54, LATCH32, and LATCH76. During this time, the LATCH signal, which enables input latches IN10L, IN54L, IN32L, and IN76L, must be low (or another phase) to schedule and latch the four input values.

One example of latch timing in accordance with the present invention is in FIG. Once the four input signals are latched in the order presented above, they are passed to the second bank of latches L10L, L54L, L32L, L76L. The secondary banks of these latches are enabled when the signals OUT_CLK and LATCH are high. This inter-signal timing is shown in FIG.

Note that the system of the present invention does not need to delay the reception of all eight input words. Once all the even and odd input words are accepted and latched into the input latches IN10L, IN54L, IN32L, IN76L, they make the In latch free, after which it is not delayed at the next rising edge of IN_CLK. It can start accepting four input signals.

The 2-digit suffix notation used for the various components shown in the figure indicates that the odd numbered signal is processed first and then the even numbered signal passes through the structure. As mentioned earlier, this order is not required by the present invention, which will be appreciated by one of the general techniques in the art in which additional adders can be used.

Once four signals are latched into the second set of latches L10L, L54L, L32L, and L76L in the proper order, the corresponding values are passed to the inputs of output latches C10L, C54L, C32L, and C76L by activation of the selected pass signal SEL_BYP. Passed as an input multiplied by the same pair of output latches by the activation of the 'p select' signal SEL_P. In other words, all signals are passed, directly or indirectly, through logic to the output latches C10L, C54L, C32L, and C76L of the pre-joint block PREC 231. However, the correct values are for the activation of the 'select bypass' signal SEL_BYP (for even inputs Y0, Y2, Y4, Y6) and the p selection' signal SEL_P (odd inputs Y1, Y3, Y5, Y7). Is loaded into these latches. As would be appreciated by one of the common techniques, the desired timing and the order of these and other control signals are easily performed with proper and / or programming operations of the controller CNTL_241.

Latch L10L output The best input value is first passed to the square root multiplier R2MUL, and as mentioned earlier, the output of the strain adder M5A looks like the square root strain multiplier of the latch L10L output. The outputs of the other three latches L54L, L32L, and L76L are also passed to the output latches C54L, C32L, and C76L accordingly.

Outputs from the other three latches (L54L, L32L, L72L, L76L) also correspond directly through the 22-bit latch buses [LCH54 {21: 0}, LCH32 {21: 0}, and LCH6 {21: 0}], respectively. The output latches are transmitted to the output latches C554L, C32L, and C76L and indirectly transmitted to the output latches through the sea adders P2A, P1A, and P3A.

In the present invention, each adder P2A, P1A, P3A has two outputs "a" and "b". In the adder P2A, one input is received from the latch L32L and the other input is received from the latch L54L. Therefore, the input values Y5 (latched at L54L) and Y3 (latched at L32L), output from adder P2A, will be equal to Y5 + Y3 as shown above and equal to P (2). Thus the odd inputs of the paired adders form a paired input value P (1), P (2) and P (3). Of course, the even input signals latched in L54L, L32L and L76L will pass through the sea adders P2A, P1A and P3A, respectively. The composite P “value” has not passed the output latches (C54L, C32L and C76L) because the “selection P” signal SEL_P will not be activated for even input.

Therefore, the values latched in the output latches C10L, C54L, C32L and C76L according to the activation of the input clock signals IN-CLK are paired input values for even inputs (Y0, Y2, Y4, Y6) or odd inputs. Will be equal to (P0, P1, P2, P3). Input Y (1) is paired with the value U (-1), which is assumed to be zero. As shown in FIG. 12, it means that this assumption is not added to the value Y1. Instead, Y1 is the product of the square root of two, as shown in FIG. 9 and FIG.

14 shows a preferred configuration of the common block CBLK232 according to the present invention. Because of the various additions and increments of other system blocks, it is necessary or desirable to reduce the input to the common block before performing various calculations. This ensures a uniform position for the decimal point (which means integer method) for the corresponding input to the various computing devices in the system.

Thus, the inputs IN0 {21: 0} and IN1 {21: 0} are correspondingly smaller with a factor of 4, which corresponds to two bits and orthogonal displacement in the digital calculation. In order to preserve some number of signals (positive values are positive and negative values are negative) in binary, the most significant bit (MSB) must be duplicated into the two most significant bits of the resulting positive word. This process is known as "signal extension". The input value IN0 is converted small by two bits by the signal extension process to form a converted input value specified by IN [21], IN0 [21], IN0 [21], IN0 [21: 2]. The input value IN1 [21: 0] is signal extended similarly in both positions. This one positional transformation corresponds to the truncated region by two factors.

As shown in FIG. 10, the inputs IN2, IN3 should be multiplied by the scaled coefficients C1S and C3S. Each input IN3, IN2 must be multiplied by a respective scaled coefficient. As shown in FIG. 14, this is performed by four constant-coefficient carry save multipliers (MULC1S, MULNC1S, MULC3S3 and MULC2S2). The basic multiplier for IN2 is an inverse multiplier (MULC1S), ie its output corresponds to the negative of the input value multiplied by the constant C1S. Therefore, the value latched in C76 is subtracted from the value latched in C32 (after being multiplied by C3?). In order to provide an inverse multiplier (MULNC1S), it is achieved by adding the corresponding value of the equivalent value to form the difference. This allows the use of the same circuit for the continuous adder, while allowing the non-inverting multiplier to use the next deductor.

In the illustrated embodiment of the present invention, four cosine coefficient multipliers (MULC1S, MULNC1S, MULC2S3 and MULC3S2) are included. The devices are designed to pass signals separately through a multiplier, but the necessary multiplication can be done using only two multipliers, one for the C1S coefficients and one for the C3S coefficients.

According to the invention, the multipliers for MULC1C, MULNC1S, MUL3S3 and MULC3S2 are preferably carry-saved, which produces two output words, one corresponding to the additional result of several rows completed in the hardware multiplier and the other One corresponds to the generated carry bits. The outputs from the multiplier are connected as inputs to one of the four input resolution adders BT2, BT3.

Only for ease of illustration, the five output buses from the multiplier are not shown connected to the corresponding input bus of the adder, but their connections will be understood by ??? of ordinary skill in the art, and the same It will be appreciated that it is shown by each input and output with a label. The save output M1S [20: 0] of the multiplier (MULC1S) is connected to the lower 21 bits of the "Save-A" of the adder BT3.

As shown in FIG. 14, five inputs to the adders BT2 and BY3 are shown to be "split". For example, the "CA" input of adder BT2 is shown having IN3 [21] for M3C [20: 0] which is the input as the least significant 21 bit. Similarly, “sa” (“Save-A” input) of the same adder is shown as GND, GND for M3S [19: 0]. This means that two zeros are added to the two most significant bits of this input word. These added bits are appropriate 22 bits to ensure that wide input words are formed with the appropriate signal.

Carry-Save adders (BY2, BT3) carry and save words from two different 22-bit inputs to form 22-bit output save words T3S [21: 0] and 21-bit output carry words T3C [21: 1]. do. Thus, the input of each adder is wide at 88 bits and the output from each adder is wide at 43 bits. As shown in FIG. 10, the output from latch C10 is combined with the output from latch C54 in the upper most data path before being added with the output from carry save adder BT3. However, "combine" is not necessary until the next adder in the upper data path is reached. Thus, as shown in FIG. 14, the converted and signal-extended input value IN0 is connected to the upper carry input.

The upper carry input of adder CS0 is connected to the converted and signal-extended input value IN0, and the converted and signal-extended input IN1 is connected together with the upper save input of the same adder. In other words, IN0 and IN1 are added later in the adder CS0.

Therefore, the designation of “dummy” adder / subtracter 240 used in FIG. 10 indicates that the action should be performed even though it does not need to be achieved at the point specified in FIG. Similarly, the lower dummy subtractor 240 shown in FIG. 10 requires subtracting from the output from the output latch C10 from the latch C54. This is equivalent to adding the output from C10 to the free number of outputs of C54.

Referring back to FIG. 14, the evenness of the input IN1 (corresponding to the output of the latch [C54] in FIG. 10) is the 22-bit input inverter IN1 [21: 0] (the logic inverse of each bit of the bit-to-bit input). Is generated). The value of IN1 --- NIN1 [21: 0] is an extra number corresponding to IN0-IN1 as the upper "Save" input of adder (CS1) with the corresponding upper "Carry" input which is converted and signal-extended IN0. To perform the subtraction.

In the lower two data paths shown in FIG. 10, the sea subtractor is commercially used instead of the adder shown in the upper two data paths at the output of the common block BLK232. Each sea adder or subtractor is equivalent to a carry-save adder or subtractor following the sea adder. This is shown in FIG. Dividers CS2 and CS3 have their inputs of processed values of IN0 to IN3 according to the connection structure shown in FIG.

The 22-bit carry and save outputs from each adder / subtractor C20-CS3 are distributed in the decomposition adder RES0-RES3. As will be appreciated by one of ordinary skill in the art, the distribution of carry and save outputs will be omitted from the digital design technique. As shown in Figure 14, the save output of the carry-save adder / subtracter CS0-CS3 passes directly to the "A" input of the corresponding decomposition adder RES0-RES3 as a 22-bit input.

As is well known in the art, two corresponding binary numbers are represented by each bit of it (both from 1 to 0 or vice versa) and 1-???? It is formed reversibly. It should be noted that “1” can be added immediately after the inverse and later. The LSB of the carry word will always be "0" performed in the illustrated embodiment of the present invention by typing the LSB of the carry words O0C and O1C into ground GND, which is input to the decomposition adders RES0 and RES1, respectively. . Adding a “1” to the carry outputs of the dividers CS2 and CS3 forms a free value of 2, but is achieved by typing LSB in these data words O2C and O3C to the supply voltage VDD, thereby “ 1 ”is added to“ replace ”the same“ 1 ”LSB.

For the same reason as above, "0" adds an LSB to the 21-bit carry word from the carry-save adders CS0 and CS1, and the LSBs of the carry words from the carry-save dividers CS2 and CS3 are supplied with a supply voltage. A data line corresponding to VDD) is typed and set equal to "1". Therefore, decomposition adder RES0-RES3 distributes the output from adder / divider CS0-CS3 to form 22-bit output signals OUT0 [21: 0] -OUT3 [21: 0].

In FIG. 14, two advantages of the IDCT circuit according to the embodiment of the present invention are shown. First, no control or timing signal is needed for the common block CBLK 23L. Rather, the input signal of the common block is already processed in such a way that it can be immediately supplied to the pure-logic arithmetic unit in the common block 232. Second, the decision on the proper size of the data word integer calculation can be used from start to finish. (Or the decimal point will be fixed for at least all values.) This avoids the complexity and slowing down of the floating point device without unacceptably sacrificed precision.

Another advantage of the present invention is to arrange the outputs as shown and to use the balanced method according to the present invention, and a structure of similar design can be used at various points in the silicone apparatus. For example, as shown in FIG. 14, the constant coefficient multipliers (MULC1S, MULC3S3, MULC3S2) receive data at the same point in the data path so that all four multipliers operate simultaneously and all have a similar structure. This eliminates obstacles, whereby the semiconductor is complex and can take full advantage of parallelism. The carry-save adders BT2 and BT3 allow to operate simultaneously with the following carry-save adders and dividers. This symmetrical structure and simultaneous use of several devices are common throughout the structure according to embodiments of the present invention.

Fig. 15 shows a preferred device of the post-common block (POSTC 233) according to the present invention. As shown in FIG. 10, the primary function of the post-common block POSTC 233 is to multiply the output of the common block by the coefficients d1, d3, d5, d7 to form a value of h0-h2; Add g (k) and h (k) values to form a lower order output; The h (k) value is divided by the corresponding g (k) value to form a high order output. 10 and 15, the post-common block POSTC 233 latches the corresponding output from the common block CBLK 232 to the latches BH0L, BH1L, BH3L, and BH2L when the Bh latch is disabled. The circuit latches in the corresponding latches G0L, G1L, G3L and G2L when the EN_BH signal is high and the output clock signal OUTC_CLK is high.

The processed odd inputs, i.e., the values of h0-h3, are latched by latches H0L, H1L, H3L, and H2L via constant coefficient multipliers D1MUL, M3MUL, M5MUL, and D7MUL when the EN_GH and IN_CLK signals are high. These multipliers are multiplied by d1, d3, d5, d7, respectively. In a preferred embodiment, these constant-coefficient multipliers are good carry-save multipliers to simplify the design and increase the computation speed. As shown in FIG. 15, the output “carry” C ″ C ″ from the constant coefficient multiplier is connected to the inputs of distribution adders H0A, H1A, H3A, H2A with the modification described below. Similarly, the "save" ("S") output from the coefficient multiplier is connected to the other input of the corresponding distribution adder as a change described below.

As shown in FIG. 15, the LSB of the H0 signal sets a corresponding "save" output that sets H0 to 0 (connects to GND) and sets the second bit (corresponding to HOS [1]) to "1". It is good to make it become "1" by typing. The data words from the carry and save outputs of the constant-coefficient multiplier D3MUL manipulate the input to the decomposition adder H1A. This is the advantage of their input to the adjustment and distribution adder H1A.

According to the invention, all 22 bits of the carry output from the coefficient multipliers D7MUL, D5MUL are connected directly to the "A" inputs of the corresponding decomposition adders H3A, H2A. However, the MSB of the "save" output of each multiplier is pressed to "0" by typing a data line corresponding to ground (GND).

IDCT systems were tested according to the CCITT specification described above. Because of the size of the digital adder and multiplier and other known characteristics, some precision is typically lost in 10,000 samples, but the reduced and expected error of digital transfer is “0” or “1” to vary the various bits described above. It works even under pressure. As a result of the bit manipulation of data words, an embodiment of the present invention achieves acceptable precision below the CCITT criterion using only 22-bit wide data words, while 24 bits are normally required to yield equivalent precision.

Due to limited precision and rough errors, there is some inaccuracy typical for all data within the IDCT system. However, the selected push bit of the data word is found by an error, whereby a specific data word at a specific location in the statistically calculated hardware that is better than the particular overall result is introduced systematically. For example, a "whisked" multiplication may be applied by selectively pressing one or more carry bits to a predetermined value.

In the present invention, the bit pressing method is not static, and pressing is always performed at a specific value as a certain bit, but a dynamic method can also be used. For example, selected bits of a data word are pushed to "1" or "0" depending on whether the word (or any other data) is odd or even, positive or negative, above or below the set limit.

Normally, only a few systematic changes need to improve the overall statistical performance. Thus, in accordance with an embodiment of the present invention, the LSB of the selected data word (although one bit and one data word at a time is good, although this is not necessary) is pressed to be either "1" or "0". The CCITT test runs and compiles the CCITT statistics for execution. The LSB (or LSBs) of the other data word is pressed to "1" or "0" and similarly compiled by statistics. Examining statistics for various combinations of pressed bits in various pressed words may determine the best statistical performance.

If this statistical improvement is not necessary, the output from the constant-coefficient multipliers D1MUL, D3MUL, D5MUL, D7MUL may be decomposed in the usual way in the decomposable adder HOA-H3A. The LSBs of these inputs and the lower 21 bits of the inputs of the corresponding latches H0L-H3L are connected to ground.

The outputs from H-latch (H0L-H3L) and G-latch (G0L-G3L) are paired to form a and b inputs to decomposition adder-dividers S70A, S61A, S43A and S52A, respectively. As noted above, these devices may add their input when the ADD signal is high and subtract the “b” input from the “a” input when the SUB signal is high. The second bits of the upper two latch pairs H0L, G0L, H1L, G1L are adjusted by the multiplication apparatus in the manner described below.

The outputs from the decomposition adder-dividers S70A, S61A, S43A, S52A are latched into the composite latches R70L, R61L, R43L, R52L.

As shown in Figure 15 (b), the input words for the adders / dividers S70A, dS61A in accordance with the present invention have a second bit of each adjusted input word. For example, the second bit of the input word for the “a” input of the adder-divider S70A is set to have a value G01M. The second bit of the other input to the adder / divider S70A is similarly adjusted. This bit adjustment is performed by four 2: 1 bit multipliers (H01MUX, G01MUX, H11MUX, G11MUX) (shown on the right in FIG. 15 (b)). In the present invention, these multipliers are set to one if the second bits H01M, G01M, H11M, and G11M are each adder and dividers S70A, S61A and ADD is set high and the second bit is a SUB signal. If is set too high, it is controlled to be set to the actual latch output value. In this way, individual sets of bits are easily performed at high speeds. Therefore, the preferred embodiment includes a bit subscription device, and as explained above, the statistical interpretation of the majority of test pixel dare shows a more accurate result, whereby this is obtained. However, no adjustment is necessary, and the second bit in this method gives the advantage of a small word width.

The results of the four high or low orders are latched in the output latches R70L, R61L, R43L, and R52L. The result is successively latched to the final output latch OUTF under the control of the multiplication signals MUX_OUT70, MUX_OUT61, MUX_OUT43, MUX_OUT52. The order of the composite signals can be controlled simply by changing the order of latching in the latches.

The relationship between the block force and the control signal in the rear common block POSTC 233 is shown in FIGS. 13 (b) and 13 (c).

As described above, two one-dimensional IDCT operations may also be achieved with intermediate conversion of data to perform two-dimensional IDCT. Therefore, the output signal from the rear common block (POSTC, 233) is first shorted in a conventional column format (and also in matrix form) to a conventional storage unit such as a RAM memory circuit according to the present invention, and the storage unit is successively reserved. In order to be passed to the common block input and processed as described above in this block and the common blocks CBLK 232 and the subsequent common blocks POSTC 233, they are read in matrix form (column form).

The matrix (column) is stored and reading into the column (matrix) performs the required operation of the conversion before the second 1-D 1DCT. Output from the second POSTC 233 is required, and the 2-D 1DCT can be dimensioned in a conventional manner by converting to bias the dimensional transformations achieved in the various processing blocks. In particular, a positive transformation by one position will be achieved by two divisions by the need to bias the two square roots of the two multiplications achieved in the 1-D 1DOT operation.

Depending on the application, the second 1DCT structure (preferably the same as that shown in FIG. 11) is preferably a separate semiconductor. This avoids the speed drop and slows down if the same circuit is used for both conversions, and split ID conversion is not necessary if the pixel-block ratio is sufficient to allow a single circuit to handle two passes in real time.

As shown in Figures 16-38, the second embodiment of the present invention uses a single one-dimensional transform. The embodiment does not need to lower the pixel block ratio as described above.

In the first embodiment, the presence of the "decomposition-adder" was changed to "rapid decomposition adder". As shown in FIG. 38, they are termed "fast decomposition adders." This change has the effect of allowing more time for each data path arithmetic block to act as its data input. In the first preferred embodiment the presence of "latch" is changed to a two-phase "flip-flop" or "register". Latch memory elements located at the beginning and end of the existing 1D 1DCT data path pipeline are combined into a single block as shown in FIG. In addition, in the second preferred embodiment, the number of memory elements present in the input and output is also increased to allow a large amount of T2 data to be buffered.

As shown in FIG. 116 and FIG. 17, two data streams " T " (data passed through 1D 1DCT, converted in TRAM) are introduced into the data path pipeline in time with the process.

In the present invention, each stream is introduced into a group of data items into the data path pipeline. The data stream is "interleaved" to pass continuously into the data path pipeline and "de-interleaved" to the data path output as shown in FIGS. 17, 18 and 33. The group is changed to many, but in this embodiment they are 8 bits.

According to the invention, T1 should not be installed. If T2 reaches the point where it intersects T1, the input buffer must not introduce data into the pipeline, which will cause it to collide with the T1 strip, and then strip T2 to provide extra buffering to prevent T2 from installing the data stream. Buffer the data from the input stream until it is safely interleaved with stream T1. This is illustrated in Figures 19 and 33, where data from stream T1 is loaded with a first transform in a latch using signals (latch 1 (0) through latch 7.) In addition, T2 The data from is loaded into "Latch 2 (0)" through "Latch 2 (15)" as shown in FIG. 19 using the signal shown in FIG.

Interleaving is controlled by the "T1 OK2 Insert" and "T2 OK2 Insert" signals. Interleaving under normal operation occurs when the signal is high. However, if the proper amount of data in the latch for T2 has not reached when the “T2 OK insert” becomes high, the latch will lose its chance and must continue to buffer the data until the next opportunity for insert data occurs.

In summary, if the buffering described above according to the invention takes place, a comparable “slip sebum” must occur at the output of T2. T2 should sleep when it loses its data insertion point and must continue buffering with the latch shown in FIG. If T2 sleeps or fails to introduce data into the pipeline, there will be a corresponding gap from the datapath output to the T2 strip output. This gap may be eliminated or "swallowed" by the use of extra buffering at the T2 output. This process may have a “fixed” T1-ID IDCT that is changed to a modifiable T2-1D IDCT, where the data strips are interleaved in time multiplication so that they can use the same arithmetic data pass pipeline.

In the present invention, "recovery" occurs when data does not enter T1. This buffers the opportunity for T2 to catch T1 and the data strip. Non-data is data in the form of bypassing IDCT and is shown with the data spikes in “Latch 2 [ø]” in FIG. This eventually results in a T2 input, which is accomplished by outputting T2 buffering. Recovery is shown in Figures 33 and 25, wherein the "T2 out" and "out" signals are gapped by multiple cycles. The gap is used as a reference to fix the data strips. It should be noted that the gap in the cycle between these two signals is buffered when the latch for T2 waits to insert its data.

After being excused in part B POSTC 233, the interleaved string is interleaved to “T2 out” as shown in FIG. 18 and FIG. The “T2 out” data strip has a slip gap in the data as described above. The T2 out [143: ø] shown in FIG. 17 is introduced into a 16-to-1 multiplier block shown by the block “IDDPMUX” in FIG. The multiplier block is one in which data is selected from one of the 16M positions in the output buffer block as shown in FIG. This position is selected by the control logic shown in FIG. 29, which uses a gap by T2 "buffer-up" as its input. This gap is used as a reference. The output strip (T2DOUT) from the multiplier block is a "fixed" data strip.

In the series of tests conducted in one embodiment of the present invention with the ID (T device described above), the median and final values meet the CCITT criteria and are well within known limits at each point. The selected value can be "adjusted" to a small amount (e.g. by pressing any bit of the selected data word to the required value) without fear of any overflow or underflow in arithmetic.

The method and system according to the invention can be modified in many ways. For example, the structure used for decomposition addition or multiplication may be changed using conventional techniques. Therefore, the preferred embodiment makes it possible to use a decomposition adder of a divider when using a split decomposition adder and a carry-save device. In addition, the preferred embodiment of the present invention uses downscaling at several points to ensure that all values are within their acceptable range. However, if other precautions arise to avoid overflow or underflow, downscaling is not necessary.

In one embodiment of the invention, certain bits of the various data words are adjusted to reduce the word width required in the system. However, of course, several intermediate values may be passed without bit adjustment. Furthermore, although the data words have been bit adjusted in the illustrated embodiment, it is also possible to adjust the bits of the constant coefficient and evaluate the results under CCITT criteria. Although the comparison of the results is shown to be good for pressurization because it is specific to a given value, in some cases the number of "zeros" will increase in the binary method of these coefficients to further reduce the silicon area required to perform the corresponding multiplication. It may be. Once again no bit adjustment is necessary.

In a summary of this aspect of the invention, an apparatus for deformation data having a first latch defining a first data strip source and a second latch defining a second data strip source is described. The first and second latches communicate with a single arithmetic unit. The arithmetic unit communicates data to the preamble ram, which transposes the data and communicates with the second latch. The second latch is adjustable and the rate of change of data received and transmitted is variable in size to accommodate. The second and first latches are in continuous communication with the arithmetic unit and the first and second data strips, but the continuous communication of the second latches does not interrupt the communication from the first latches. In this way, a common arithmetic unit is used for the first and second data strips. Moreover, a procedure for processing transmission data using a common arithmetic unit having subsequent steps will be described. First, data is loaded into the first latch when a predetermined number of cycles of transmitting data to the arithmetic unit is reached, and the first marker bit is loaded into the control conversion register. The next loads data into the second latch, the second latch being changeable and adjustable in size to accommodate the changing rate of data received and transmitted at different rates. The next step is that the first control conversion register reaches the adjustment state and the data in the second latch is sent to the arithmetic unit. Next, preventing transmission of data from the second latch is recovered when the second latch is not filled with a predetermined amount of data or the second latch is not receiving the data.

Detailed Description of the Invention for Time Synchronization

In MPEG-2, video and audio data are synchronized using information carried in the MPEG-2 system strip. In this regard, there are essentially two pieces of information used to synchronize; This is the clock reference and time stamp. The clock reference is used to know what number the decoder used to represent the "now" time. This is used to count the decoder incrementing at normal intervals to see what the current time is.

Time stamps carry strips of data that are used to create programs (typically video and audio). In the case of video, the time stamp is associated with the picture and tells the decoder to display the picture at some "time" (limited by a counter initialized by the clock reference).

In MPEG, a series of clock references is multiplied into a system strip. These clock thresholds define “system time”. There are two types of clock reference values: program clock reference values (PCRs) and system clock reference values (SCRs). In the present invention, the distinction between PCRs and SCRs is not allowed because each clock reference value is not used in the same way by the decoder. PCRs and SCRs have time information for fields that extend the resolution of 90 kHz and the resolution of 27 MHz (or 1/27 × 10e 6 seconds). The clock reference is often included in the data strip so that the "system time" is reinitialized after random access or channel change.

Therefore, it is important to understand the time stamp resulting from the hypothesis of the decoder that can decode the picture immediately. As one understands one of the common techniques of art, no real decoder can do that and take steps to fix the theoretical time at which the drawing should be displayed. Moreover, time stamps and clock references are used to determine display time and errors in display time. This modification depends on the details of the architecture of the unusual decoder. Obviously, any delay is derived that the video decoder must match the same delay as in the audio decoder.

When decoding MPEG, discontinuities in terms of "system time" can occur. For example, each edit point may have a discontinuous time in bitstream editing. A similar situation can occur when switching channels. It is important to understand that using time stamps requires caution when using them as they can encode and lead to incorrect results in one situation with the "system time" defined in Clock References from Other Situations. Can be.

Figure 39 shows the demultiplexing of the MPEG system stream into elementary streams 250. Each elementary stream usually carries both video or audio data. In general, any type of data is transmitted. Each elementary stream is divided into a series of access units. On the video side, the access unit is called a photograph. On the audio side, this is the specified number of audio data samples.

Again, multiplexing to the system stream is a series of clock references. These clock references define "system time."

Associated with the present invention, each elementary stream is a series of time stamps 251. The time stamps are described as "system time" in which the next access unit for each elementary stream is represented. These time stamps are called current time stamps, “PTS”.

In the case of video data, the second type of time stamp is also called the decode time stamp, “DTS”. Since a DTS is only current, when one PTS is also present and there is a simple relationship between the two, the detailed differences between these two types of time stamps are ignored because the differences in PTS / DTS are not a problem in this presentation. Can be.

The decode time stamps DTS define the time at which the access unit (picture in video) is decoded. The presentation time stamp (PTS) defines the time at which the access unit is represented (displayed). However, the timing model used is a hypothetical model as an infinitely fast decoder. In this case, the DTS and PTS are the same as the others.

However, in MPEG video decoding, some of the pictures are rearranged. Therefore, after decoding, the pictures have capacity for a certain time, for example, some frame times before being displayed. During this period of time, questions are displayed and other pictures are decoded into pictures, followed by other pictures. As a result, these rearranged pictures are the difference between DTS and PTS.

In accordance with the present invention, it is understood that coordination is required in terms of the use of time stamps for the appropriate synchronization time. In one preferred embodiment, a time-sheetizing circtree is placed at a point in the decoding pipeline when the pictures occur in their decode order. Thus, such embodiments use DTS.

Nevertheless, the suctree can be equivalent to moving the pictures to a point in the decoding pipeline that occurs after rearrangement. Therefore, the photos arrive at the synchronizing document tree in their display order. Therefore, as one of the common techniques of art is understood, the PTS is used in this embodied state.

In preferred embodiments of the present invention, the information infers that the time stamp is transmitted through various cycles using a token. Tokens contain a series of words of one or more pieces of information. The first word of the token contains code that identifies the type of token, so the type of information is carried by the token. Tokens associated with each word are extension bits that set a bit indicating that there are more words in the current token. Therefore, the last word of one token is indicated since the extension bit is zero. In the present invention, the code in the first word is the type of the token so that while some codes use a larger number of bits, the number of one small bit (the rest of the bits in the first word represents different information). Allow) to indicate the significant number of bits.

Tokens can be thought of as controls or DATA tokens. For example, at the interface between the system decoder and the video decoder, there are two types of information: (1) coded video data and (2) sync time inferred from the time stamp information. Coded video data is shown as data and carried in a DATA token, while the sync time is shown as a control of information and carried in a control token (SYNC_TIME) (that token is called DATA). Additional control tokens can sometimes be used in the present invention. For example, a FLUSH token behaves similarly in a reset signal and manner, which requires an error to initialize the video decoding queue before starting decoding again.

Consistent with the present invention, it is a more preferred object of the emojiant to time synchronize two time synchronized circuits without direct communication system time between the first and second circuits. In accordance with the invention, the time synchronization of the two circuits is performed without direct system time passing to the second circuit by supplying synchronized time counters in each furnace.

The present invention also allows for synchronizing two circuits in time, with no communication system time between the first and second circuits being fed a base stream time counter in each circuit.

Thus, another object of the present invention is to synchronize the two circuits in time and determine the presentation time error, although the others have a synchronous time past the first circuit with time stamp information, system time, and elementary stream time. It compares the base stream time to the second circuit that occurs and the copy of the base stream time synchronized to the base system of the first circuit in the second circuit. The system of the present invention does not have a direct communication system between the system decoder and the video decoder, and without a system that is directly passed to a video decoder that is provided with a synchronized time counter for each circuit, without a direct communication system between the system decoder and the audio decoder. A system decoder and a video decoder without communication system time can be synchronized in time between the system decoder and the video decoder supplied by each video counter.

The invention also enables the system to synchronize the system decoder and the video decoder in time and determine the display time error, passing the video decoder from the video time stamp information, system time, and the system decoder, if anything else. Video decoding time until synchronization time occurs.

40 shows the elementary stream time stamp management transitioned to the first preferred embodiment, consistent with the present invention. Clock reference 253 represents the system time, which is decoded and initialized by the system demultiplexer 254, and, if necessary, increases from system decoder 256 to time counter 255 and to 90 KHz. The second copy of clock reference 253 is simultaneously loaded into counter 255, which is internal to elementary stream decoder 257, also incremented to 90 kHz, and synchronized to time counter 255 of system decoder 256.

Time stamp 251, consistent with the present invention, the flow of elementary stream buffer 260 from system demultiplexer 254 is delayed by the same amount of incoming data. Time stamp 251 may also have a solution by supplementing the non-zero decode of elementary stream decoder 257. The corrected time stamp 251 is compared with a copy of the time that stored the time counter 258, which is the interior of the elementary stream decoder 257, to determine whether the decoded information was presented too early or too late.

The above embodiment is better than just the direct passing system of the elementary stream decoder 257 from the time counter 255 in the system decoder 256 since the counter in the system decoder changes 90,000 times per second. Therefore, system time is essentially necessary to continue to pass to elementary stream decoder 257 as needed. The passing system time is continuously determined by using a time counter 255 located at the base stream decoder 252 and a time counter 255 located at the system decoder 256, such as a dedicated pin or the like. The time can be passed in the form of several clock references 253 per second.

Another embodiment is shown in FIG. That embodiment of FIG. 41 shows that avoiding the need for clock reference 253 for the pass to elementary stream decoder 257. This is done by using an "es_time" 262 containing information of the elementary stream time maintained by the system decoder 256 and elementary stream decoder 257, which are the second counters. Both es_time counters 262 and 263 are reset when powered on, such as a channel switch, and free run from on. Because it depends on staying on the embodied two es_time counters, 262 and 263, we understand that we need to take measurements to make sure that the es_time counter does not step. One way to ensure that the es_time counters 262, 263 stay in agreement is to use the es_time counter as it resets the es_time counter in the elementary stream decoder 257 shown in FIG.

Looking more closely at FIG. 41, clock reference 253 is decoded by the system demultiplexer 254, where the system time is decoded, placed by the time counter 255 in the system decoder 256 and increased to 90 kHz. The es_time counter 262 of the inventive system decoder 256 and the es_time counter 263 of the inventive system basic strip decoder 257 are synchronized with each other and incremented to 90 kHz. Elementary stream time stamps are also decoded by the system demultiplexer 254. Therefore, the synchronization value X is calculated using the elementary stream time stamp, the system time is included in the time counter and the elementary stream time is included in the es_time counter 262 and the system decoder 256 according to the equation 3-1.

The following set of equations 3-1 (a-d) is a description of a method consistent with the present invention for time synchronization avoiding passing from clock reference 253 to elementary stream decoder 257. Equation 3-1 (a) is an equation requiring time synchronization. Since system time is not desirable to pass directly to the elementary stream decoder circuit 257, as shown in FIG. 41, by passing the system decoder 256 and this value to the elementary stream decoder, equation 3-1 ( Using bd), the registration time representation X occurs. Sync X is compared to include an es_time counter 263 whose elementary stream time is located within elementary stream decoder 257. Therefore, the comparison result is used to determine whether the decoded information will appear early or late, and to further time synchronize the system.

Equation 3-1:

a) time sync = (default stream timestamp-system time)

b) time sync = (X-elementary stream time)

c) (X-elementary stream time) = (elementary stream time stamp-system time)

d) X = (Default Stream Time Stamp-System Time + Default System Time)

In the present invention, the synchronization time, X, can be corrected by supplementing the non-zero decode time of the elementary stream decoder 257. The corrected sync time is compared with the base stream time constituting the es_time counter 263 located inside the base strip decoder 257 to determine whether the decoded information is coming out early or late, and to further use the time to synchronize the system. do. Note, the time correction may be omitted from the elementary stream time, including es_time located inside elementary stream decoder 257, instead of sync X added as a result. The embodiment above is an example of a solution to the occurrence of sync time X and determines whether the information is early or late. It will be clear that there is such a technique in art that there are many other equivalent solutions for the above achievement.

For example, Figure 42 shows an alternative method of determining synchronization X, consistent with the present invention. In this arrangement, the system decoder 256 does not maintain the elementary stream time. Instead of recording it, in the register initial_time 265, the system time value at the time of the elementary stream time counter is reset to zero, es_time 263 located in the elementary stream decoder 257. The value of es_time 263 may be calculated by system decoder 256 because the value of es_time 263 will differ from the value recorded at the current system time and initial_time.

Equation 3-2 (a-c) below describes an alternative method for time synchronization. Equation 3-2 (a) represents the value of the elementary stream time in es_time 263 located in the elementary stream decoder 257. This is inferred by equation 3-2 (c) because equation 3-2 (b) is replaced by equation 3-1 (d), as a function of the system and by storing the value of the initial_time register 265, the synchronous time X is supplied. It is simple.

Equation 3-2

a) elementary stream time = system time-initial_time

b) X = (default stream timestamp-system time + [system time-initial_time])

c) X = (default stream timestamp-initial_time)

Two solutions for leading to synchronous time, X, have been described in accordance with the present invention. However, it is clear that many other equivalent solutions are skilled in art.

Figure 43 shows another embodiment representing the invention of performing video time stamp management. Clock reference 253, which represents the system time, is initialized with system demultiplexer 254 to place a time counter 255 at system decoder 256 and increment to 90 kHz when necessary. The second copy of clock reference 253 is simultaneously loaded into time counter 258 inside video decoder 270 and incremented to 90 kHz and synchronized to time counter at system decoder 255.

Video time stamps circulate from the system demultiplex 254 through the video decoding buffer 271 which is deferred by the same amount as the incoming video data. The video time stamps can be corrected by supplementing with the non-zero decode time of the video decoder 270. The corrected video time stamps are compared to a copy of the time at time counter 258 inside video decoder 270 to determine whether the decoded picture will be displayed too soon or too slowly.

The embodiment is enhanced in FIG. 43, since the counter of the system decoder varies 90,000 times per second from the system decoder's time counter to the video decoder only at the time of the direct system time. Therefore, system time will continue to be passed to the video decoder for all needs. Passing system time continuously requires a dedicated pin or something like that. It uses a time counter located at the system decoder, a system decoder, and a video decoder located at the system time, so it can pass in the form of a clock reference every few times.

Referring now to FIG. 44, the clock reference representing the system time is decoded by the system demultiplexer 254 and placed in the system decoder 256 as the time counter 255 and incremented at 90 kHz. The vid_time counter 272 is synchronized differently and incremented at 90 kHz. Video time stamps are also decoded by the system demultiplexer 254. Thus, the synchronization value X is calculated because it uses the video time stamp, according to equation 3-3, the system time includes a time counter 273 and the video decoding time includes a vid_time counter 272 including a system decoder 256. It includes.

The combination of the following equations 3-3 (a-d) is one way in which time synchronization consistent with the present invention avoids from the clock reference 253 to the video decoder 270. Equation 3-3 (a) is an equation requiring time synchronization. As shown in FIG. 44, since it is not preferable to pass the system time to the video decoder circuit 270, a synchronous time representation X occurs, and using the equation 3-3 (bd), the system decoder ( 256 is passed to video decoder 270. The sync time, X, is compared to the video decoding time, which includes the vid_time counter 273 in the video decoder 270. The result of the comparison is used to determine whether the decoded picture is displayed too early or too late, and furthermore, the time synchronization of the system.

Equation 3-3

a) Time Sync = (Video Time Stamp-System Time)

b) time sync = (X-video decoding time)

c) (X-video decoding system) = (Video time stamp-system time)

d) X = (Video Time Stamp-System Time + Video Decode Time)

In the present invention, the sync time X can be corrected as a supplement for the non-zero decoder of the video decoder. The corrected synchronisation time is related to the video decoding time, which includes a vid_time counter 273 located inside the video decoder 270 to determine whether the decoded picture will be displayed too early or too slowly and for time synchronization to the system. Are compared. Note, the time correction may omit the video decoding time including the vid_time counter 273 located inside the video decoder 270 instead of the addition of sync time X for the same result. The embossment of the present invention above is another example of a solution for determining the picture to be displayed early or late and for generating synchronizing time X. However, it is evident that many other equivalent solutions to the above work are skilled in the arts.

In connection with the present inventions, another good feature is that there is no need to deal with a full 33 bit time stamp number or a 42 bit clock reference number. The present invention limits the counter to 16 bits and allows video bit 270 to handle 16 bits. At first glance, 16 bits do not seem to be sufficient to represent the numerical range of a resolution of 90 kHz. However, such high accuracy is not necessary because the video decoder 270 only needs to be accurate in field time (the video timing generator VTG is free to operate or any closed is not related to the decoded MPEG stream). And, therefore, it is not related to the time stamp or presentation time anyway.

As shown in FIGS. 44 and 45, with synchronous time X and video decoder 270, vid_time counter 273 uses only 16 bits. This is made possible by two factors. First, the difference between the system time and the time stamp (inferred to synchronous time; see Equation 3-3) must always be small, thus allowing more important bits to be discarded. Therefore, less significant bits are discarded unnecessarily because they are shifted 4 bits to the right.

Thus, 16 bits of time information used in the present invention can handle timing error for about 11.5 seconds with an accuracy of about 180 ms (about 1% of field time). PAL or SECAM's European 625-line system scored 112.5 points at 5625 Hz clock; NTSC's 525-line TV system has a 93.84 point. Therefore, 16 bits allow timing calculation with an accuracy of about 1% of field time.

Figure 46 shows the preferred process. The movement of the time stamp through the present invention and hardware is consistent. It will be appreciated that the communication information method in the preferred hardware is tokens, but an optional method is also used. The hardware is divided into two modules. The first module is added after the start code detector 201. As discussed above for this module generating tokens, SYNC_TIME contains sync time X and occurs before it is associated with the PICTURE_STERT token. In the MPEG system stream, time stamps are sent through the packet header and send the first picture in a packet of data. The packet has the end of the picture just before the start of the picture sent by the time stamp, since no video data is sent.

Synchronous time information is supplied to this invention by using a microprocessor interface or token. In both cases, as detailed in Table 12, the synchronous time data (16 bits) is stored in the synchronous time register (the permission to access each byte in two parts).

TABLE 12

In the present invention, a flag, ts_waiting, is set to indicate that valid synchronization time information is in the time stamp register. If the data was supplied using a SYNC_TIME token, the token is removed from the token sequence.

When a PICTURE_START token is encountered, a plug indicating the state of the sync time register is checked. If the flag is not set, there is no action and the PICTURE_START token and all subsequent data are not affected. However, if the flag is set, it indicates that valid sync time information is available in the register and placed in the data string on the PICTURE_START token line when a SYNC_TIME token is generated. The flag is cleared and the sync time register is valid for the next time_stamp generated.

The second module, as shown in FIG. 46, consists of a prescaler clocked at 27 MHz and a vid_time counter clocked by the prescaler 278 associated with the microprogram state machine (MSM) 128.

As shown in Figures 44 and 46, there is a prescaler 278 that divides the clock into 4800. In other words, the 4800 is 300 (27 MHz / 90 KHz) times 16. The 4804.8 options shown in FIGS. 45 and 46 are discussed later.

In the NTSC color television, the frame rate is not 30 Hz, but in fact other than almost 29.94 Hz (exactly 30000/1001 Hz) [color television 30 Hz was used.]. There is exactly a 1716.27 MHz clock period for NTSC line time (the line time is 1/525 of the frame time).

The US television standard body has expressed interest in reverting to 30Hz [probably 60Hz for HDTV] in the future. After all, MPEG supports exactly 30Hz frame rate. However, since it is impossible to generate a stable 30 Hz television signal from a 27 MHz clock (1714.29 cycles per line), it is difficult to generate a 30 Hz raster in the MPEG framework. One possible solution is to "bend" the clock speed at the decoder. Thus, instead of generating a 27 MHz clock, a 27.027 MHz clock is generated. This clock is generated using an MPEG clock with a 300.3 (in addition to 300.) divider and generates a 90 KHz clock. This 27.027MHz clock provides exactly 30Hz speed when clocking a matching video timing circuit that provides a 29.94Hz frame rate from 27MHz.

In the framework of the present invention, another factor of 16 is prescaled to 90 kHz. Therefore, divide 27.027MHz into 300.3 × 16 = 4804.8.

The Vid_time counter 273 (described above) is incremented each time the prescaler reaches its end count, including the video decoding time. The vid_time counter 273 is reset by a reset-time pin.

The prescaler and vid_time counter of the present invention can be performed with a fully clocked feedback flip-flop that is much more resistant to α-particle blight than resistive feedback or weak feedback latches used elsewhere. Using a clocked feedback flip-flop for the time counter causes the time counter of the video decoder to remain in step with the time counter of the system decoder.

Figure 47 shows the MSM 21A, processing performed when accepting a SYNC_TIME token. The MSM 218 reads the current time indicated by the video time counter and then compares it with the value supplied by the video SYNC_TIME token. It is therefore possible to determine whether it is early or late, relative to the time at which the picture should be decoded.

In the present invention, the 16 bit signal time stamp correction is added to the sync time X (described above) shifted by the video SYNC_TIME token. This calibration is reset to zero by the MSM 218 at chip reset, and if there is no action, the sync time remains unchanged. The control microprocessor always records the value with ts_calibration to correct the sync time and thus compensates for the charge delay through the video and audio decoder.

The current video decoding time included in the vid_time counter 273 is subtracted from the calibrated sync time. The signal value gives the direction of error (if any, determines the error code generated by MSM 218) and the absolute value of the difference is taken so that the result is compared with a threshold and determines whether the timing error is within tolerance. This threshold is set at one frame time as the video time can now be controlled from nominal time to plus or minus precision by frame period (as VTG333 is often).

If the error exceeds frame_time, some must be corrected. The MSM 218 of the present invention can correct the situation by itself when the decoding is too early. This is because the MSM can simply delay decoding by a reasonable time. However, if the decoding is later than the intended time, time correction is difficult. This is because it is impossible to reliably discard the picture at the output of the coded data buffer. The decoding of the sequence must be broken so that the best reliable way to correct the situation is to restart the decoding process in a manner similar to random access or channel change. For this process, the control register of MSM 218 is programmed to discard data until it encounters the appropriate start code or FLUSH token. In addition, the error "ERR_TOO_EARLY" is not generated during startup regardless of the disbale_too_early setting. This is because the first image is expected to be early in the startup.

Table 13 illustrates how the MSM 218 register works and how some of the action and error message information placed within the register occurs.

TABLE 13

As a result of the synchronization time adjustment of the present invention, one of two mistakes may occur.

ERR_TOO_EARLY is generated when decoding has occurred earlier than the time indicated by the time stamp. ERR_TOO_EARLY can be suppressed, but ERR_TOO_LATE will always be raised unless all errors are prevented.

In summary, the present invention includes the following. A second time initiated by a mechanism to match the time it has, a time stamp to determine the serving time, a clock reference for starting the system time in the first circuit, and a clock reference in the second circuit that is set to match the time with the first time counter. To determine the error in the provision time between the local copy of the system time and the system time by maintaining the time counter and the system time in the first circuit, maintaining a local copy of the system time, and comparing the time stamp and the second time counter. First time counter associated with the clock reference. It also includes mechanisms to match the time of the system decoder and video decoder using time stamps to determine the display time, a clock reference to initiate system time at the system decoder, and a video that is timed to match the first time counter. Between the local copy of the system time and the system time by maintaining the system time at the system decoder at the decoder and the system decoder at the decoder and by the clock reference, maintaining a local copy of the system time, and comparing the time stamp with the second time counter. First time counter associated with a clock reference to determine display time error. In another embodiment, a first circuit having a time counter connected to a clock reference to maintain the system time, a mechanism for matching the time of the first and second circuits, and a clock reference to initiate the system time in the first circuit. The first elementary stream time counter is included in the first circuit to provide an elementary stream time. The first circuit is adapted to receive a time stamp, and the first circuit matches the time by adding the elementary stream time to the time stamp and subtracting the system time. The second circuit is adapted to receive the matched time from the first circuit, providing a local copy of the elementary stream time and a first elementary stream time counter for determining timing errors between the sync time and the local copy of the elementary stream time. It has a second elementary stream counter with a matched time of. In this way, the clock reference signal does not need to go directly to the second circuit to determine the timing error. In another embodiment there is no need to enter the first and second circuits directly. In yet another embodiment, the mechanism for matching the time of the first and second circuits has a clock reference to initiate the system time in the first circuit. The first circuit has a time counter connected to a clock reference to maintain system time and a first video time counter to provide video decoding time. The first circuit is adapted to receive a video time stamp and creates a synchronous time by adding the video decoding time to the video time stamp and subtracting the system time. The second circuit is adapted to receive the synchronization time from the first circuit and provides a local copy of the video decoding time and compares the local copy of the sync time and the video decoding time to determine the timing error between the system time and the video stamp. It has a two-time video time counter that is set to have a time that matches the first video time counter. Therefore, the clock reference signal does not need to go directly to the second circuit to determine the timing error. Also included in the present invention is a method of providing timing information by providing a video data stream having a time stamp whose time stamp is executed in a packet header representing the first picture in the data packet. In the next step, a register is provided with the flag used to display valid time stamp information taken from the packet header and transferred to the register. Next, the time stamp is removed from the video data stream and then moved to a register. This method then executes a picture start and, as a result, examines the state of the register to determine if valid time stamp information is included in the register. If the flag indicates that valid time stamp information has been included in the register and then the time stamp has been reinserted into the data stream, a time stamp is generated in response to the picture start. Another embodiment includes the mechanism described above where the elementary stream time counter is limited to 16 bits. Similarly, there is a mechanism as described above, in which the second elementary stream time counter located within the elementary stream decoder is limited to 16 bits. There is also the same mechanism as described above, where the synchronization time is limited to 16 bits to adjust the elementary stream decode. The present invention also includes a process for determining display time errors for video decoding and thresholds. This then further processes the video data to determine whether a time stamp indication has appeared and breaks the time stamp indication into indications for comparison with the video time, creating a value that is compared to determine the timing error indication. This in turn determines whether the timing value is within the allowable variables when the timing error is indicated when comparing the compared value to the threshold, and indicates when the value being compared is outside the allowable variable. Another embodiment includes a mechanism for using a system decoder and a video decoder. The system decoder is adapted for multiplexing video data and video time stamps from MPEG system streams and streams. This system decoder has a first time counter representing the system time. The video decoder accepts video data and video time stamps and has a second time decoder that is timed to match the first time counter. The video decoder also has a video decoder buffer that is capable of accepting data at essentially constant rate, releasing video data at varying rates and sending a video time stamp. The video decoder compares the second time counter with the video time stamp for the decoded picture while also decoding the picture from the video data to determine the appropriate display time. There is also a way to determine the time error between the first and second circuits. That is, after giving the system time (SY), time stamp (TS), and elementary stream time (ET) to the first circuit, the elementary stream time (ET), time stamp (TS), and system time (SY) are given by the equation X = ET + TS Substitute in -SY to obtain the synchronization time (X). After giving the synchronization time (X) to the second circuit, a time-matched elementary stream time (ET2) is produced, and then the synchronized error (X) is substituted into the equation ET2-X to obtain a time error. Thus, the first circuit can achieve time agreement with the second circuit without sending system time to the second circuit. Another method of determining the time error between the first and second circuits is to follow the procedure below. After a time stamp (TS) and an initial time (IT) are assigned to the first circuit, the time-stamped elementary stream time (ET) after the time stamp (TS) and initial time (IT) is given to the second circuit with the equation X = TS-I. ) And then obtain the time error by substituting the synchronized time (X) into the equation ET-X. In this way, the first circuit can be matched with the second circuit without sending system time to the second circuit. Another method for determining the time error between the first and second circuits follows the following procedure. The first circuit is given system time (SY), video time stamp (VTS), video decoding time (VT), and then the video decoding time (VT), video time stamp (VTS) and system time (YS) are equations X = VT + Substitute in YS to obtain the synchronization time (X). After the synchronization time (X) is given to the second circuit, the video decoding time (VT2) in the second circuit that coincides with the video decoding time (VT) in the first circuit is generated, and the synchronized time (X) is expressed by the equation VT2. Get a time error by substituting for -X. Thus, the first circuit can be time aligned without sending system time to the second circuit.

Detailed Description of the Invention for Asynchronous Swing Buffering

In accordance with the present invention, for asynchronous swing buffering, two buffers operate asynchronously, one being written and the other being read. This makes it possible for a data stream with the first processing rate to be reconsistent at another rate while still maintaining the desired rate. In the present invention, the write control device and the read control device both have status indicators for communicating about which buffer they are using and whether the control device is waiting for access or in fact accessing the buffer. Each side communicates one bit each. This is the only signal that must be matched in time between both sides of the asynchronous circuit structure. When one regulating circuit (read or write) finishes accessing the buffer, the invention allows the regulating device to move to the other circuit. If both regulating circuits try to use the same buffer after the regulating device swings, the latter regulating circuit will begin to wait. The regulating circuit will wait until each side uses its respective buffer, i.e. the other side swings. If after the swing it is found that it is now writing its own buffer to the other side, it will immediately start accessing without waiting. The coordination scheme between these buffers is started by two buffers using the same buffer, in this case buffer 0. While the write side is approaching, the read side will start waiting because there is no valid read from each buffer.

In one embodiment, in accordance with the present invention, swing buffers are two separate RAMSs that allow data to be transferred from either the strobe, address, or one of the read or write sides, depending on which buffer is being accessed by each side. It has all the signals that make it happen. This structure is known to use a large area to transport many signals between two buffers.

Combining two RAMs into a single structure saves a significant part of the transfer area while maintaining the same functionality. This structure has twice as many columns. However, the second embodiment must have two pairs of bit lines because reads and writes to separate buffers occur simultaneously and asynchronously. Each row will have its original thickness (ie have the same number of cells) because the approaching ones will have the same thickness as the separate RANs. Each pair of columns is accessed at the same address, but from different buffers, so they are connected to different pairs of bit lines. Using the same address, these pairs of columns can be easily accessed by one column decoder coupled to the read address and one column decoder coupled to the write address. The read and write controls never access the same buffer again and again at the same time, so there is no conflict as to which pair should be accessed by which column decoder.

By the same method that allows each column decoder to access the columns of each buffer, the read and write circuits in the structure of the present invention are all connected to each pair of bit lines, one pair in each buffer. These reads and writes are multiplexed into each buffer and are free of conflicts for the same reasons described above.

As shown in FIG. 48, in accordance with the present invention, the swing unit 1 includes a swing buffer 10 having RAMs 12 and 14. Swing unit 1 also includes write control circuitry and read control circuitry, which control data in or out of RAM 12 and 14. The read and write control circuitry accomplishes this by using strobe, data and address control lines 8. Lines 7 and 9 are control lines for indicating the RAM used by the write control circuit and the RAM used by the read control circuit. Line 7 operates to regulate the write control circuitry, which uses RAM 12 when low and RAM 14 when high when using read control circuitry. Similarly, line 9 tells the read control circuit that it is using RAM 12 if the write control circuit is low and RAM 14 if it is high.

In the present invention, the swing buffer 10 has two RAM arrays of 12 and 14. Swing buffer 10 allows asynchronous, alternative reads and writes to the RAM area that allows this mechanism to have the bands needed for fast memory access. RAM 12 and 14 require the following signals. See also FIG. 49 for write address 16, read address 18, data in 2, data out 22 and read and write enabled signals (not shown).

Write address and read address signals are multiplexed by the multiplexer 24. RAM arrays 12 and 14 work with traditional write circuits, column decoders, and read circuits. In the first embodiment of the present invention, during the start of the swing buffer 10, the writing will continue in the RAM 12 until the control circuit converts the writeable signal to the RAM 14.

Once the RAM array 12 is written, it is under the control of the read control circuit 4 to be read. During this time the RAM array 14 is also written. It is important to note that when the RAM array is placed under the control of the read array control 2 or the write control circuit 4, the adjustment is established until the adjustment is changed after the read or write is completed. In a situation where the read control circuit 4 is accessing the RAM array 12 and the write control circuit 2 has to access the same RAM array 12, the write control circuit starts to wait.

Thus, two conditioning events are made in accordance with the present invention. When a write control circuit or a read control circuit swings to another RAM, it immediately starts accessing or waiting for RAM because the RAM is free and not under the control of another circuit. During startup, the read side yields to the write side because there is nothing valid to read from each buffer.

A second embodiment of the present invention is shown in FIG. The integrated swing buffer 30 includes a RAM array 32 having a logical size of RAM array 12 combined with a RAM array 14. In other words, there is the same amount of RAM in the first and second embodiments, but it is combined in the second embodiment. Thus, the integrated swing buffer has the same swing buffer function and significantly reduces the transmission area.

In the second embodiment of the present invention, the write circuits and read circuits 34 and 36 are similar to those used in the swing buffer 10. However, these circuits now have a selector selected from the next pair of bit lines specified. Similarly, read access column decoder 38 and write access column decoder 40 are similar to those included in swing buffer 10, but they are capable of accessing a pair of columns as described in FIG. 51 below.

As shown in FIG. 51, the specific structure of the integrated swing buffer 30 has been described in accordance with the present invention. Each of cells 42 is included in column 44. Read column decoder 38 and write column decoder 40 access column 44 in pairs. The pair of columns have the same address provided by address lines 16 and 18. Read buffer line 52 and write buffer line 54 provide adjustment information to select one of the paired columns 42. Buffer 0 bitline 48 and buffer 1 bitline 50 are connected to columns of alternative cells and to read and write circuits 34 and 36. To clarify the drawing of the addressing, the brighter shading shows the read column decoder 387 accessing the column in buffer 0. Similarly, the darker shading represents write column decoder 40 accessing the column of buffer 1.

In summary, at least two RAM arrays of the present invention include a write control circuit connected to a RAM array for controlling data input to the RAM array, and a read control circuit connected to a RAM array for controlling data output from the RAM array. Swing buffer mechanism is included. Furthermore, the read and write control circuits are in contact with each other, allowing time-matching adjustment of the RAM array. In addition, each cell can be addressed by a RAM array, a write control circuit in contact with the RAM array via a pair of bit lines, a read control circuit in contact with the RAM array via another pair of bit lines, and a pair of columns to address the RAM There is a swing buffer mechanism having a read column decoder and a write column decoder to allow reading.

[Detailed Invention for Storing Video Information]

The video decompression system includes three basic parts used to decode and display picture information. The three main parts of a video decompression system are the spatial decoder, the temporary decoder and the video formatter. The present invention includes a temporary decoder and video formatter and a method in which the temporary decoder and video formatter process their respective picture buffers and then frame store buffers. In the MPEG system, the temporary decoder has two frame store buffers, and the video formatter also has two frame store buffers.

MPEG uses three different picture types: Intra (I), Predicted (P) and Bid inrectionall Interpolated (B) pictures into two different pictures. Based on predictions from: one picture comes from the future and the other from the past. The I picture no longer needs to be decoded by the temporary decoder, but must be stored in one of two frame store buffers for later use in decoding the P and B pictures. When decoding a P picture, forming prediction is required from the decoded P or I picture. The decoded P picture is stored in the frame scorebuffer for use in decoding other P and B pictures. The B picture can be predicted from both frame store buffers. However, B pictures are not stored in the frame store buffer.

When I and P pictures are decoded, it can be seen that the pictures are not output from the temporary decoder. Instead, the I and P pictures are input into one of the frame store buffers and only output when the next or P picture arrives for decoding. In other words, the temporary decoder relies on the subsequent P or its picture to flow the preceding pictures from the two picture buffers. Therefore, when it is necessary to flush the two frame store buffers of the temporary decoder, the spatial decoder of the present invention can provide a dummy or P picture. The dummy picture flows out at the beginning of the subsequent video sequence.

As shown in Table 14, image frames are displayed in numerical order.

TABLE 14

However, in order to reduce the number of frames to be stored in the temporary decoder, the frames are transmitted in different orders. It is useful to start the analysis from an intra frame (I frame). I frames are transmitted in the order in which they are displayed. Subsequently, bi-directional interpolated frames (B frames) that are displayed between I frames and P4 frames are transmitted. Therefore, the transmitted B frames may refer to the front frame (forward prediction) or the rear frame (forward prediction).

After all B frames displayed between the I and P4 frames are transmitted, a P7 frame is transmitted. Next, all B frames displayed between P4 and P7 frames, that is, B5 and B6, are transferred. Subsequently, the next I frame, i10, is transmitted. As a result, all B frames that are displayed between P7 and I10 frames, that is, B8 and B9, are transmitted. This arrangement of transmitted frames only requires two frames to be stored in the temporary decoder at any one time, and there is no need to wait for the transmission of the next P frame or I frame to indicate the interacting B frame. As described above and shown in Table 14, the temporary decoder of the present invention may be configured to provide MPEG picture rearrangement. With this picture rearrangement, the output of the P and I pictures is delayed until the next P or I picture in the data stream begins to be decoded by the temporary decoder.

As the P and I pictures are rearranged, some tokens, Picture_Start Picture_Type and Temporal_Reference, are temporarily stored in the chip as the picture is written to the picture buffer. When the picture is read for display, the tokens stored there are revived. At the output of the temporary decoder, the DATA tokens of the newly decoded P or I picture are replaced with the DATA tokens for the old P or that picture and then sent to the video formatter. The output from the temporary decoder is in the tokenizal macroblock format and there is no block-raster conversion.

In short, the video formatter of the present invention stores two frame stores or pictures. In some video formatters, three pictures or framestores are used to accommodate repeating or skippin pictures. Off-chip DRAM in video format has three framestores. In this case, using three framestores, frames may be repeated or skipped when the decoded video and the display have different frame rates.

All I, B and P pictures are stored in the framestore of the video formatter. At any time, there may be one frame store where data is displayed and one frame store from which the data is read, and in the video formatter with three frame stores, another frame is stored in the third frame store.

This embodiment performs the prediction, rearrangement, and block-last tasks that MPEG typically handles using a temporary decoder and video format, each having two framestores. This is achieved in the present invention by using a framestore that shares a scheme using only three framestores. However, this embodiment does not handle repetition and skip frames of the video formatter with only three framestores.

The present invention stores the picture in the store in the first frame and the P picture in the second frame store. Since it is necessary to perform block-raster conversion, the B frames are stored in the third framestore in the following detailed manner. In order to minimize the amount of external DRAM required, a structure in which consecutive B frames share a third framestore is used.

If a B frame is decoded, it may refer to two already decoded I or P frames occupying the first and second framestores. The decoded B frame is recorded in the third frame store. In this embodiment, the raster can operate before the framestore is completely filled. Since this raster operates before the framestore is filled, the next B-frame can be read into the same framestore to occupy the area left by the raster on top of the previous frame.

The framestore is occupied with picture data and individual framestores are divided into sectors to keep records available as new data. In the present invention, each frame store is divided into two field stores, each field store consisting of N sectors, where M is the number of block rows in a field.

Frames coded as field pictures are straight. Each successive macroblock row occupies two sectors in one field store. Once the write back has advanced far below the frame, the raster starts reading individual sectors from above. Once the writeback of the first frame is complete, the next frame is read into the area left by the raster. By checking the status of the individual sectors, it is possible to check whether the sectors being scanned are completely filled, or whether the two sectors required are empty for writeback.

Frames coded as frame pictures are more difficult. Unlike field pictures, macroblock rows of data are not read into DRAM in the order in which they are scanned. Field stores are read side by side while fields are scanned alternately.

Consider an image with eight sectors on a field store. That is, the fieldstore 0 is composed of eight sectors from 0 to 7, and each sector occupies one row of the block. (Ie 8 pixels per width of the image) The field store 1 consists of 8 sectors from 8 to 15, with each sector occupying one row of blocks. (I.e. 8 pixels per width of the image).

The first macroblock row is read back to sector 0 in field store 0 and sector 8 in field store 1. At some point, the raster in the field store (0) does not catch up to writeback because the raster begins to mark sectors from the fieldstore (0) and that point is selected. However, the second frame cannot be recorded again in the same way as the first frame. Since the sectors are written and read in a different order, waiting for the same two sectors to be free at the beginning of the frame means that writing and reading cannot occur consecutively. This must be achieved in order to maintain the display and keep the decoding at the required rate.

Therefore, the second frame must be recorded in the sector of the framestore freed by the raster. This is done by splitting the framestore into two parts. Therefore, the meaning of the half field store is changed for the second frame. Sectors 4 to 7 become the upper part of the second field store and sectors 8 to 11 become the lower part of the first field store. The first macro block row is written to sector (0) and sector (4) and once free, subsequent rows are sector (1) and sector (5) and sector (2) and sector (6) followed by sector (3) and It is recorded in the sector 7. The next row is recorded in sectors 8 and 12 and in sectors 11 and 15. This rearrangement of memory is sufficient to ensure that the writeback and raster persist at a reasonable rate.

When the third consecutive B frames arrive, the writeback order returns to the writeback order of the first frame.

In the shared B frame store, as a FRAME picture:

The FIRST image is recorded in sector 0 and sector 8 again. [First macroblock row = 2 block rows]

Then it is written in 1 and 9, 2 and 10, 3 and 11, ..., 7 and 15. The FIRST picture is rasterized from sector 0 and then rasterized from 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15.

SECOND frames are recorded in sectors 0 and 4, and then in 1'5, 2'6, 3'7, 8'12, 9'13, 10'14, 11'15.

SECOND frames are rasterized from sector 0 and then written to 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15.

According to the present invention, the second frame and the first macroblock row are not recorded in sector 0 and sector 1, so that the first two sectors are not rasterized. Instead, it waits for the sector 4 to light up. This is done for two reasons: First, waiting for sector 4 to light up is easy to implement and does not affect the system's ability to maintain continuous decoding and display even in the case of worst coded data. Secondly, the process of entering and reading from a memory sector with a picture size that is divided into multiple sectors rather than two powers is often not repeated (e.g. NTSC format has 30 sectors per field and sequence is every 58 frames). Is repeated). This makes testability and recovery difficult.

In an embodiment of the present invention, a halffield store is effectively performed as a fifo with a pointer to the next position to be read, rather than keeping a record of the state of the individual sectors. Thus, once the individual envelopes are filled or emptied, lightback and raster are impossible. This takes advantage of the fact that individual half-field stores are written and read in just one direction, like Pippo.

In short, the present invention provides a method of storing video information by providing video information in the form of I Frame, P Frame, B, Frame and B2 Frame and storing the I Frame in the first frame store in the second frame; Provide a third frame with the first and second field stores, split the first and second field stores into at least two memory regions, respectively, store B and Frame in the third register, and then select from the selected portion of the memory region in the first or second field stores. B, read Frame; B, write the B2 Frame part in the selected part of the memory area where the Frame is read; Thus, video information can be stored with a reduced memory capacity.

The following two programs have Code used in the preferred embodiment of the present invention.

[Detailed Description of the Invention for Parallel Huffman Decoder]

According to the present invention, the parallel Huffman decoder decodes Huffman coded Variabre Length Codes (VL Cs) and Fixed Length Codes (FL Cs), and passes the tokens under the control of a Parser microprogrammable state machine (MSM). .

Embodiments of the present invention deal with MPEG-2 and MPEG-1 Huffman codes. One important aspect of the embodiments of the present invention is that it can support high throughput (throng-put) because it is a parallel decoder instead of serial large code.

An embodiment of the present invention uses a code lookup technique to decode Huffman codes. This is done to fulfill the performance requirements and also to handle the second irregular MPEG-2 transform coefficient table which is inherently irregular, i.e. not standardized.

In addition, embodiments of the present invention have the following characteristics, i.e., examples of more complex elements from a single cycle stream without the aid of an external controller include Escape-coded coefficients, Intra-DC values and Motion Vector deltas. All of which are present in the stream as complex VLC / FLC elements.

Referring now to FIG. 52, this diagram shows how the parallel Huffman decoder 300 processes codes of various lengths (VLCs). FLCs require a bypass mechanism that uses selector 301 outputs and input fields, respectively, to generate data and specify the length of the FLC. Therefore, ROM 302 is not needed during FLC decoding.

As the name suggests, the "earlier" or most important data is stored in MSReg. The start of the next VLC is used with a selector to match the ROM input. Thus, to decode the first VLC, the selector outputs the top 28 bits of the 59 bit input, of which the top 16 bits are sent to Huffman Code ROM 302. For subsequent VLCs, the selector effectively changes the input according to the total count of bits decoded so far. This count is made by adding to VLC. As a result of the maximum coding size that can be decoded, there are various word widths, which are 28 bits MPEG-1 Escape Coded Coefficient and 16 bits the maximum VLC size (DCT coefficient table).

The “table select” input is used to select between the various Huffman code tables required by MPEG.

[Huffman Coed ROM]

The key to the practice of the present invention used to decode all VLCs is a special ROM 302 whose address is controlled by the selector / shifter 301 shown in FIGS. ROM 302 performs VLC table index calculations and then performs index-data operations to yield decoded data.

Index calculation can be thought of as a Content Addressable Memory (CAM) operation with “dont care” formatting performed to handle Huffman code forming the displayed data. Since all VLC code tables are fixed, the CAM-ROM will be sufficient and this is the task of the ROM AMD-plane shown in Figures 54-57. There are no restrictions on the handling of irregular tables because index generation is look-up (somewhat computational).

ROM Or-plane converts an “index” (enabled word-line) to the size (ie length) of the decoded data and code. The data forms a decoded output (error-checked), and the size information is fed back so that a calculation is performed that controls the selector and provides accurate data to the ROM 302 to perform decoding of the next VLC in subsequent cycles.

The ROM 302 address of the present invention is in two fields. The large field is the bit-pattern to be decoded and the small field selects the Huffman code table to be examined. The bit pattern to be checked is 16 bits corresponding to the longest VLC code, with an additional 4 bits of the table select. Thus, although there are only 450 entries in ROM 302, there is a 20-bit full address area (a million addresses). The different reason is due to the “don't care” bit.

To decode VLCs, the AND-plane must be able to decode the “don't care” bit in the VLC bit pattern. This is because all VLCs shorter than a maximum of 18 bits are followed by additional bits that do not form the decoding portion of the VLC. Because of the wide address, the AND-plane is decoded in advance (2 → 4) and ROM 302 must combine “don't care” handling with this predecode. In addition to the full MPEG code table, the ROM 302 also has an entry that identifies an ambiguous VLC pattern and exists for some code tables of this VLC pattern.

[Maximum Throughput]

Some care must be selected to control the decoder input to maintain the output of one decoded item at each cycle and special handling is required for some “complex” symbols (eg symbols other than single FLCs or VLCs). Do.

In order to maintain peak throughput of escape-coded coefficients, at least one complete code must be entered per cycle. Since the maximum length required in MPEG-1 is 28 bits, it indicates an input word width of 32 bits (a detectable size larger than 28).

This coefficient is also a “complex” symbol because the VLC is followed by a 1-bit FLC that gives the level of the path and is treated in a similar manner to other complex symbols (eg motion vectors, intra DC and Escape coated coefficients). . If the coefficients are decoded as VLC followed by FLC (in individual cycles), peak throughput cannot be achieved, and if ROM 302 can decode the signal bits, then the size of the two largest tables in ROM can be doubled. Thus, in the present invention, special handling is used for the various symbols, resulting in the final required result in a single cycle.

[FLCs and Tokens]

The basics of FLC handling are to control the selector with the required length of the FLC and to simply output the correctly selected FLC by bypassing the ROM 302. Thus, simple FLCs can be handled naturally with decoders without significant extra hardware. Also tokens are not manipulated but simply passed directly to the output of the decoder.

[Implementation]

This section describes some important features of the implementation of the decoder in accordance with the present invention. Execution involves arranging registers in the counter 303, the selector 301, and the current code ROM, as shown in FIG.

The schematic diagram of FIG. 53 shows how the core elements are interconnected to implement the main Huffman decoding core section of the present invention. Registers ms [31: 0] and ls [31: 0] are MSReg and LSReg, respectively, and the block phselect is the selector. Counter logic is contained in the phcclog (along with various other logic) and the latch is called cntl [4: 0]. Other logic shown in this figure handles handling commands, data, command dynamics, and manipulation of more complex symbols (performed by block phcop).

54 shows a very small sample ROM configuration used to implement the Huffman code ROM 302 according to the present invention. A useful feature of this ROM 302 is the AND-plane where predecode and “don't care” are used to implement the method of decoding variable length Huffman codes.

Reference is now made to Figs. 55-57 and particularly Fig. 55 is shown a first embodiment of a ROM AND-plane capable of "don't care" handling. In this embodiment, individual address lines a [3], a [2], a [1], and a [0] traverse the AND-plane in both the forward and reverse directions. Transistors are connected to the positive or reverse address lines in a conventional manner to decode "one" or "zero" at a given address line. To decode “don't care” (marked with X), do not connect the transistor to the positive or reverse line.

56 and 57 illustrate another embodiment of using predecoding to reduce the number of series transistors in the decoding logic. In these embodiments, two address bits are combined with each other in predecoding so that one of the four lines moves high for each of the four possible numbers that can be represented by the two address bits. It will be appreciated by those skilled in the art that the present invention works equally well with the high level of precoding in which more than one bit is coupled to each other. If two address bits that are coupled to each other in predecoding define a value (1 or zero, but not “don't care”), the transistor is connected to the appropriate predecoded address line in a conventional manner. However, if one of the address bits needs to have a defined value (1 or zero) while the other address bit needs “don't care”, when either of the two predecoded address servants is active It is necessary to select a wordline that crosses the or-plane during decoding. In the embodiment of Fig. 56, this is done by installing two transistors, which are placed in parallel on each of the associated predecoded address lines as in the case of code; 001. In the embodiment of Fig. 57, elemental decoding is done without using parallel connection of transistors. In this case, two separate decodes to be selected are performed. Decode is combined using a NOR gate in the wordline driver so that the wordline is activated when two selects are active.

The overall concept, system implementation and various operating aspects of the present invention are described in detail above so that a person skilled in the art may carry out the present invention with the features, objects, and advantages of the present invention in mind. I believe it would have been. However, for further details relating to a more complete understanding and commercial practice of the invention, see the following detailed description.

The following more detailed description of the system of the present invention is described for ease of organization, clarity, and description, under the headings set forth below.

summary

Start code detector

Parser

Spatial processing

Prediction

Display circuit

Parallel Start Code Detector (SCDP)

Input Fifo

Start code

Elimination of Bit Stuffing

Navigation mode

Unaligned Start Code

Overlap Start Code

Unrecognized Start Code

Extension and User Data

Insertion of PICTUIE_END Token

Stop after picture interrupt

discall_all

Access bits

Token recognized by SCDP

SCDP memory map

Implementation

Data flow around coded data buffers

Working theory

discontinuity

Start-up

Example

hardware

MSM Handling of Time Stamp Information

Start up

MSM time stamp error code

Support for 30 Hz

Introduction

Start Machine

Jump and Calls

Interrupt and Error

Jump address

State machine internal command

State Machine Testing

State machine Ucode map

State Machine Ucode Word

Arithmetric Core

Transformation block

Carry block

ALU Core

ALU Ucode Word

Use of ALU

Register file

Register file register type

Register fileless map

Register file CODE word

Token Port

Token Port Uod Word

Multiplexer

UPI memory map

Preface

detail of fuction

Demand for timing

Microprocessor Interface Access

Preface

interface

detail of fuction

Mal-formed tokens

Zig-zag scan path

Raster Scan Order

Microprocessor Interface Access

Preface

Prediction on Frame Images

Frame based prediction

Field based prediction (in frame pictures)

Double prime (in frame picture)

Prediction on Field Images

Field based prediction

16 × 8MC

Double prime in field image

Overall composition

Horizontal Up Sampler

Preface

4: 3 Up Sampling

3: 2 Up Sampling

2: 1 Upsampling

Boundary Effects

Number of output pels

Location signal

Multiplexed data

Horizontal alignment

Up Sampling Ratio

Video timing generator

Preface

Horizontal timing

Vertical timing PAL

Vertical timing NTSC

VTG Structure

Horizontal machine

Vertical machine

Hard Wired Comparator Design

Output multiplexer

Border generation

Vertical border

UPI Control

Output multiplex

[summary]

This detailed description deals with the invention as an overall chip. 58 shows a high level block diagram of the system. In the sections that follow, individual blocks are developed to provide more detailed block diagrams.

This description provides information on all the interfaces between the various functional blocks of the circuit. This should ensure that each block is constructed with full knowledge of the interface he has to provide.

As shown in FIG. 58, components of the basic system include a clock generator 350, a start code detector 201, a parser 202, a microprocessor interface 320, and a memory control assistance system 352. , Spatial processing system 351, prediction assistance system 208, and display 355. 58 also illustrates the interface that occurs between the various system components.

[Start code detector]

Figure 59 shows the start code detector 201 (SCD) interfaces with other blocks of the system circuit in accordance with the present invention.

SCD 201 can be thought of as providing three separate functions. First, the SCD 201 provides an input circuit for receiving data from a dedicated pin or MPI 320. Secondly, the SDC 201 finds a start code in the data and provides the necessary circuitry to assemble the third incoming data into a format used within the coded data buffer (CDB) 321.

[Parser]

60 shows a parser assistance system in accordance with the present invention. Data formatted for CDB 321 is unpacked and sent to the parser receiving commands from MPI 320. The data is then sent to the rest of the system via a two-wire interface.

[Spatial processing]

61 shows the components of the spatial processing circuit. These components include inverse modeler (Imodel) 325, inverse zig-zag (IZZ) 326, and inverse modeler (Iquant) 327 and inverse discrete cosine transfer (IDCT) 328. The data is passed into Imodel 325 and then to IZZ 326 followed by Iquant 327 and IDCT 328.

[Display circuit]

62 shows a display circuit of the present invention. The system includes a vertical upsampler 210, a horizontal scale auxiliary system 331, an output multiplex 332 and a video timing generator 333.

[Parallel Start Code Detector]

The start code detector 201 according to the invention is a parallel start code detector, ie it passes data in parallel. This system is similar to the systems of the previously disclosed UK patent application No. 9405914.4 (filed March 24, 1994) and EPO patent application 92306038.8 (filed June 30, 1992) (hereinafter “Brolly”). However, there are some major differences between the two start code detectors. First, byte alignment is assumed. In the present invention, there is no movement of data to find the start code. Secondly, the present invention basically occupies MPEG data.

It consists of a single bit (byte pattern) in a bit stream known as MPEG (1 and 2) start code prefixes. The pattern is 23 zeros followed by one. The eight bits following the start code prefix are known as the start code value. This indicates the type of start code. Indicates the type of start code reaching the SCD of the present invention. The start reaching the SCD of the present invention needs to be byte aligned. Therefore, the above data byte sequence can also be specified. For example:

0 × 00

0 × 00

0 × 01

0 × b8

Is the group start code.

[Fifo]

Given the peak data rate of 250 K bytes / s and the coded data buffer is not overflowed, the present invention is constructed such that the incept pin is never pulled down. Thus, to calculate the length of the input envelope, we need to know: (1) worst-case latency for the swing buffer, and (2) data expansion via the worst-case SCD.

With input data arriving at the data clock rate coded in accordance with the present invention, scdp generates two stalls per start code with 3 bytes removed from the data stream.

[Input circuit]

The input circuit of the present invention operates exactly the same way as described in Broll. However, there are some differences between the two circuits. First, the vpi does not wait for the valid end of the token to appear. Instead, wait until the signal on the token goes low. Second, when entering byte mode, the generation of the DATA header depends on the byte mode data.

[Start code]

In the present invention, the MPEG start code is recognized by the SCD and converted into tokens. These are shown in Table 15.

TABLE 15

[Remove Bit Stuffing]

Zero bits preceding the start code prefix are stuffing and can be safely removed. In the present invention, only complete bytes are removed during stuffing.

For example, in the byte sequence of 13 stuffing bits shown below, only 8 stuffing bits are actually removed.

0 × 20 // 5 stuffing bits

0 × 00 // 8 stuffing bits

0 × 00

0 × 00

0 × 01 // start code prefix

[Search mode]

The search mode according to the invention is described in Table 16 below.

TABLE 16

Nonzero search mode discards all data that arrives until the required class of start code is found. At this point, the seek mode is reset to zero and a start code seek interrupt may occur. A new control bit, or stop on seek, determines whether the SCD is actually stopped after generating an interrupt (interrupts are masked in a tone-like manner, but stopping is not necessary).

In the present invention, the search mode is also set to zero when the SCD receives the FLUSH token. However, when the FLUSH token finishes discard-all, the search mode is completely reset, that is, the search mode is reset with a combination of the FLUSH token and discard-all.

[Unaligned Start Code]

The operation of one or more zero bytes followed by 0 × 01 is a start code. Also, the operation for one greater than 23 zero NOT is the unaligned start code. This is converted to a byte alignment world: if 0x01 is not accepted after removing bit stuffing, the start code is not aligned. You can see that this state actually has no unaligned start code (contains less than one byte of stuffing).

The scdp of the present invention ignores this without explaining the data sheet in which the class of unaligned start code is detected. That is, the stapling is still removed.

[Overlap Start Code]

The "value" part of the start code may form the "prefix" part of the subsequent start code. This typically occurs for two reasons. Standards allow system-level start codes to occur anywhere in the stream. -It can happen directly in the middle of the video level start code. And 2) error. Better error recovery can be achieved by removing the faulty start code up to the last code.

In a bind alignment environment, the only way in which overlapping starts can occur in accordance with the present invention is that image start (value = 0x00) forms a different start code. In this case the picture start is removed from the data and the second start code is decoded. If this overlaps, the same procedure is performed until a non-overlapping start code is found.

[Unrecognized Start Code]

In the present invention, the holding values (0xb0, 0xb1, 0xb6), all system start codes (0xb to 0xb9), and sequence error codes (0xb4) are each set to an unrecognized start code. Are treated. After removing the unrecognized start code, the SCD discards all incoming data until the next valid start code is found. In addition, if the unrecognized start error register is set, an interrupt is generated according to the unrecognized start mask.

[Extension and User Data]

Two configuration bits are used in the present invention:

1) Discard_User (or not)

2) Discard_extn (behind MPEG2 main profile, main level)

These configuration bits are reset to ONE.

MPEG2 extended start codes are different from each other. The four butts following the extended start value are extended start identifiers and must be decoded to the SCD. They generate four new tokens to signal. Allowed extended start code identifiers and their individual tokens are shown in Table 17. However, reserved extended start code identifiers are not recognized. Unrecognized extended start codes are discarded according to (Discard-extn) or replaced with (old) extended data tokens.

TABLE 17

[Insert token of PICTURE_END]

None of the STANDARDs (MPEG 1,2, JPEG, or H.26) specify how to stop the current picture.

However, in the present invention, the SCD 201 maintains a state called in_picture. This state is set whenever the picture start token is output by the SCD 201. Subsequent start codes higher than picture start (i.e. FLUSH token) in terms of syntax cause the generation of a picture end token. A picture end token is generated and output before the tokens are combined with the new start code. in_picture is reset when the picture end token leaves SCD 201. When the SCD 201 receives a token in the input data stream, the operation is logically the same-including receiving an image end token. In short, the start codes that cause the generation of a picture end in accordance with the present invention are as follows:

Burn start code OR token

Group Start Code OR Token

Sequence start code OR token

Sequence End Code OR Token

FLUSH token

[Stop after Image Interrupt]

A feature of the sap behind the image of the present invention is the complete termination of the current sequence, i. It is necessary to perform this function as automatically as possible without external real-time software.

The sap control bit is referred to as the flag picture end.

In addition to the flag image end, mask, and error bits, there are two control bits. :

1) after_picture_step: Determines whether SCD is stopped after interrupt is generated.

2) after_picture_discard: Generates a flag picture end interrupt and determines whether scdp automatically enters discard_all mode.

In this way, the discard_all mode does not need to know what it is called, and can quickly and reliably proceed to the search mode, leaving the discard_all mode.

According to the present invention, whenever a flag picture end is set whenever a PICTURE_END token is output by the SCD, a flush occurs after PICTURE_END, and an event occurs. Interrupting depends on the flag picture end mask and stopping depends on after_picture_stop.

For example, the sequence of events for channel change is as follows. :

1) Set flag_picture_end to after_picture_stop = 0 and after_picture_discard = 1

2) Respond to flag_picture_end_event.

a) Set the search mode to sequence, for example.

b) return

3) FLUSH or S / W resets discard_all.

4) scdp searches for the start of the next sequence.

[discard_all]

Due to the R / W control bit, discard_all, the scdp of the present invention discards all input including the FLUSH token. This butt is automatically reset by the FLUSH token and can also be reset by the flag-picture-end function.

[token recognized by scdp]

The basic function of most scdp of the present invention is related to actual token generation, and there are several tokens that are decoded and operated by scdp when given to a coated data port (i.e. via an input circuit). Table 18 defines these tokens.

TABLE 18

[Scdp Memory Map]

The various registers of the present invention and their associated addresses for scdp are described in Table 19.

TABLE 19

[Data Flow Around Coded Data Buffer]

The present invention provides the following advantages.

1) How to Enhance the Swing of a Buffer

2) how to avoid having to pack bytes with odd bits

3) Reduce the width of the (essentially long) bus of the SCD to 8 bits.

4) The SCD itself is packed with 32 bit data. To avoid large buses, this bit of the SCD sits in a dramif. In the present invention, it is referred to as sccdbin. This module packs all data into 32-bit words.

5) Swing buffers do their own counting and swinging. The buffers are flushed from the Sccdbin in response to a signal, i.e. fill_and_swing, in response to a PICTURE_END or FLUSH token (i.e. signal).

6) The unpacking module, sccdbout, sitting in front of the Huffman decoder erases all data following FLUSH or PICTURE_END until it receives the buffer_start signal provided by the output swing buffer.

[Preface]

This part defines the handling of time stamp information in accordance with the present invention.

[Theory of Operation]

In MPEG-2 video and audio, data is synchronized using information in the MPEG-2 system stream. There are basically two types of information that deal with synchronization: clock reference and time stamp.

The clock reference is used to tell Decope what number represents the time "now". Since it is used to initialize counters that are incremented at regular intervals, the decoder always has the concept of what the current time is.

Time-stamps are needed for the individual data strips used to construct the program (typically video and audio). In the case of video, the time-stamp is related to the picture and tells the decoder when to display the picture, which is defined as a counter initialized with a clock perspective.

However, as with everything in MPEG, this condition is more complicated than this. There are two types of clock references. Program clock references (PCRs), system clock references (SCRs), and clocks have information about 90KHz resolution, while other clocks have additional information to extend the resolution to 27MHz. Because clock references are often included in the data stream, they can initiate a “time” after random access or channel change.

There are also two types of time stamps. Presentation time stamps (PTSs) and decoder time stamps (DTSs). They are different for I pictures and P pictures (not B pictures) that are rearranged. The DTS tells you when to decode the picture and the PTS tells you when to display it. For frame pictures without 2-3 pull-down effects, the difference between the DTS and PTS and the I picture and P picture is one more than the number of B pictures following the picture frame period.

The main complexity is that the DTS and PTS refer to a virtual model of a decoder that can decode the picture immediately. No real decoder can do this and steps must be taken to correct the theoretical time to display the image (as defined by the time-stamp and clock reference).

This modification depends on the details of the structure of the decoder. Obviously any delay introduced by the video decoder must be matched with an equivalent delay in the audio decoder.

[discontinuity]

Discontinuities in the concept of “time” can also occur. For example, individual edit points in the edited bitstream will have discontinuous time. A similar situation occurs when changing channels. Care should be taken when using time stamps encoded in one time domain for the “time” defined by the clock reference in another organization, as this will lead to inaccurate results.

[Start up]

A special problem arises at startup (or channel change) because there are two competing demands for starting decoding correctly. In the case of video, it is necessary to start decoding into an I picture following the system header (this does not apply to all situations but is generally correct), but in the case of a system, the first decoded picture must be time-stamped. However, not all pictures need to have a time stamp, and one picture may wait long if it finds a picture with a time stamp.

One may think about calculating what time stamp for an I picture from a picture preceding a picture having a time stamp. Unfortunately this is very difficult because it is necessary to partially decode the intervening picture to determine whether the pictures are fields or frame pictures (and repeat_first_field is set). This requires that data pass through the coded data buffer and be discarded by the Huffman decoder.

EXAMPLE

FIG. 63 shows a first embodiment of time stamp management. The clock reference 253 is decoded into the system demultiplex 254 of the present invention and installed in the counter 255, incremented by 90 KHz and indicating time. They also enter a second copy of the counter 258 located within the video decoder 270.

Since the time stamp flows through the video buffer 271, it is delayed by the same amount as the video data. These are then compared with a local copy of the time to determine if the picture is too fast or too late.

Another embodiment of the present invention is shown in FIG. In this embodiment, the clock reference 253 does not need to be passed to the video decoder 270. This is accomplished by using a second counter "vid_time" 272, 273, which is embedded in both video decoder 270 and system decoder 256. Since this embodiment has two counters in the step, it is necessary to take measures so that they do not leave the stem. This is done by turning on a counter in the system demux to reset what is in the video decoder.

Another advantage of this embodiment is that it does not need all 33 bits. It is desirable to limit the counter to 16 bits so that video decoder 270 handles 16 bits. This may represent an insufficient number at a resolution of 90 KHz (terminal 2/3 seconds), but this high accuracy is not necessary because the VTG works freely in the video decoder (ie it is not related to the MPEG stream being decoded). The time control is accurate to field time either way because it is gen-locked.

As a result, the lower order bits of the timestamp going to the decoder are discarded. In the present invention, four bits are discarded. This means that the video decoder uses 16 bits out of 20 bits. Therefore, the resolution is 5625Hz and can show a time difference of 11.65 seconds.

Therefore, the PAL field is 112.5 ticks of 5625 Hz clock. The NTSC field is 93.84 ticks. Thus, a time calculation can be made up to an accuracy of about 1% at a field time suitable for the present invention.

[hardware]

65 shows hardware according to the present invention. In addition to those disclosed in Brolly, there are two more modules. The first one is added immediately after the start code detector 201. This serves to generate tokens. The TIME_STAMP token appears just before the PICTURE_START token. In the MPEG system, the time stamp is in the packet header and refers to the first picture in the packet of data. Because the packet is not aligned with the video data, there is usually an end of the preceding picture before the start of the picture referenced by the time stamp.

The time stamp information can be supplied to the system of the present invention via a microprocessor interface or using a token. In either case, the time stamp data (16 bits) is stored in a register. A flag is set to indicate that valid time stamp information is in the register. When data is supplied using the TIME_STAMP token, the token is removed from the token stream.

When a PICTURE_START token is encountered, a flag indicating the state of the register is checked. If it is certain, no action will occur and all subsequent data will not be affected. However, if the flag indicates that valid time stamp information is available in the register, a TIME_START token is generated before the PICTURE_START token. The flag is cleared and used at the next time stamp.

The second hardware module relates to the micro programmable state machine 218. This is a series of simple counters that are clocked at the 27MHZ decoder clock. The first is a prescaler by dividing the clock by 480 (the 4804.8 option in the diagram is described later). The 4800 is simply 300 (27 MHz / 90 KHz) x 16.

The second counter is a time counter and is incremented each time prescaler 278 clocks. This is reset to the reset_time pin.

The counter in this section is implemented as a fully clocked feedback flip-flop (SYNC'S), which is much more resistant to particle corrosion than the weakly used feedback latches used elsewhere. Time counter can come out of step with what is in the system decoder).

The microprogrammable state machine 218 can read the current time indicated by the time counter and compare this time with the value given by the TIME_STAMP token. Thus, it can be determined whether it is fast or slow compared to the time to decode the picture.

Table 20 shows the registers used in SCD 201 related to time stamps.

TABLE 20

[MSG Handing of Time-stamp Information]

This part describes its function when the MSG 218 receives a TIME_STAMP token in accordance with the present invention.

First, a 16-bit time stamp correction is added to the time stamp for the TIME_STAMP token. This correction is reset to zero by the MSM 218 at chip-reset and the time stamp does not change unless operation occurs. However, to modify the time stamp, the control microprocessor may write some value to this register. Therefore, compensation for automatic delay through video and audio decoders is provided.

Next, the corrected time stamp is subtracted from the current time. Its signal provides the direction of the error (and also determines if there is an error code generated by the MSM 218. It takes the absolute value of the difference and the result is compared to the frame time. As mentioned earlier, the VTG works freely, so you can control the time exactly by subtracting or adding frame time from the nominal time.

In the present invention, the error must be corrected if the frame time exceeds. Because decoding can be deferred until the appropriate time, the MSM 218 can correct this condition if the decoding is too fast. However, if it is later than the intended decoding time, this becomes more difficult because the picture cannot be discarded at the output of the coded data buffer. Essentially, the decoding of the sequence is interrupted and the best way to correct the situation is to restart the decoding process in a random access or channel-specific manner. To facilitate this process, the MSG 218's control registers may be programmed to discard all data until a FLUSH token is encountered.

[Start up]

According to the present invention, when the MSG 218 receives a time stamp at the time to recognize it as a start-up state (i.e., following the SEQUENCE_END token or FLUSH token after reset and still before the first PICTURE_START), the behavior of the MSM 218 is modified. . If the time stamp indicates that decoding should occur earlier than the current time, the state is handled in the same manner as described above. However, if the time stamp indicates that decoding continues to occur after the current time when the decoding is normal at startup, the decoder waits until the correct time even when the error is less than one frame time. In this way, the nominal decoding time can be set to the correct time as accurately as possible. And subsequent pictures can be decoded up to one frame time before or after the process time without triggering any error condition.

Also, in the present invention, the error "ERR_TOO_EARLY" does not occur during startup regardless of the setting of disable_too_early (because the decoding is considered to be fast).

[MSM Time-stamp Error Code]

One of two errors occurs as a result of the time stamp handing.

If decoding occurs earlier than the time stamp indicates, ERR_TOO_EARLY occurs.

If decoding occurs later than the time stamp indicates, ERR_TOO_LATE is raised.

You can suppress ERR_TOO_EARLY, but ERR_TOO_LATE always occurs unless all errors are masked out.

Table 21 describes the various time stamps associated with microprogrammable state machines in accordance with the present invention.

TABLE 21

[Support for 30Hz]

The present invention does not adequately support 30 Hz frame rate. However, it will be appreciated by those of ordinary skill in the art that the present invention may decode 30 Hz data if the clock generation circuit is properly modified. In this case, the system is clocked at 27.027 MHz, so a typical “CCIR-601” raster will provide the picture at exactly 30 Hz. To accommodate the 27.627 MHz clock, it must be separated by 300.3 to provide a 90 KHz clock. Since the present invention scales this value to 16 factors, it is necessary to divide the clock by 4804.8.

[Preface]

Here, the micro-codeable state machine (MSM) according to the present invention will be described in detail. The goal of building an MSM is to provide a machine that can be used in many applications, such as VLC decoders and address generators, with a small calibration.

The MSM of the present invention provides many features. An important component of MSM, however, is its modularity, which can be flexibly formed. Therefore, it can be seen by those skilled in the art that the present invention can be applied to various aspects.

As shown in FIG. 66, the system is divided into two parts. The first part is the state machine 218. This state machine issues commands to the data processing pipeline under the control of a two-wire interface as in the Brolly patent application described earlier. The second part is an Arithmetic core 219 which consists of an ALU 222 and associated register file 221. Arithmetic core 219 is part of the data processing pipeline. It receives data and terrain under the control of the 2-wire interface ¹ above. It also provides data on output under the control of a two-wire interface. Using these two components allows the specification of complete uncode words.

―――――――――――――――――――――――

These two two-wire interfaces can be combined even if the one state machine coordinates the upstream block.

[State machine]

State machine 218 in accordance with the present invention provides instructions to arithmetic core 219. It also provides a command to itself during the process through the command.

The address passed to the instruction arithmetic core 219 is in the program counter. The program counter is reset to 0x00 and proceeds continuously through the address. However, a "jump" or "call" command and / or an "interrupt / error" event may cause the program counter to reload, thus changing the order of terrain execution.

If the state machine also controls the upstream block, these two-wire interfaces may be combined.

The state machine is capable of up to 4096 instructions in the present invention. However, it will be appreciated by those of ordinary skill in the art that other terrain quantities may also be used and this does not act as a limiting value.

[Jump and Call]

In this implementation, all commands are conditional jump commands. The condition is calculated for all commands to decide whether to jump or not. Two conditions, "True" and "False", are provided respectively to jump or not jump without conditions. The remaining conditions (all 16) are tested on the status bus. If the condition is not "true" or "false", the state machine 218 waits until the arithmetic core 219 processes the terrain and sends the status bus back to the state machine for testing of the condition. These conditions are shown in Table 22.

Table 22

If a jump condition is given with a set of call bits, the next address not given a jump condition is stored as the return address. Thus, this constitutes a mechanism for routing calling. A call is given to address (0x001) to return to the stored address from the routine. Calling is only given one call, ie only one return address can be stored. Nevertheless, although there is an error, the call in the call is not found in the hardware.

[Interrupt and Errors]

In the present invention, if the interrupt / error is collected high, an unconditional jump is made at the interrupt / error address (0x001). The next address that is to be selected without interrupts / errors is stored. A jump to the interrupt address (0x001) occurs to return from the interrupt / error routine.

The state machine 218 of the present invention is hardwired to handle interrupts or error routines. The difference between interrupt routines and error routines is that the former masks out other interrupts in the process, but the latter does not. The state machine 218 is wired as an interrupt rather than as an error.

[Jump Addresses]

The address in the program counter is a jump address. 12 bits of this address are contained in an uncoded field. This may be an absolute address or may have a portion replaced from the output of ALU 222. If the address is replaced, the state machine 218 waits until the arithmetic core 219 issues a command to send the ALU 222 to the state machine for replacement.

The format of the address according to the invention is shown in Table 23. “Jump Address Replacement”. Bits marked "a" indicate absolute address bits. The remaining less important addresses are replaced. The LSB, denoted by "s", is a substitute bit.

TABLE 23

The address substitution characteristic of the present invention constitutes a jump table configuration.

[State Machine Internal Command]

It is desirable to perform an iterative condition test on the state bus.

These commands are inside the state machine 218 and require stereo feedback at arithmetic corner 219. Thus, these imperatives may be marked as unfair to arithmetic core 219 and may not be executable. Thus, a "Valid" bit is given to indicate that the arithmetic core 219 is valid.

[State Machine Experiment]

In the present invention which enables the demonstration of the 218 operation of the state machine, the register number will be accessible to the microprocessor bus. Access is obtained by setting the "access" register to one and polling the register until this value is read back. The state machine then stops for secure access. The device can be restarted by writing zeros to the "access" register.

When the microprocessor has access, it can read and write to the following registers.

Program counter

-Call return address

Interrupt Return Address

The interrupt status bit (ie, whether the interrupt is in progress)

Mode bits of U code

Table 24 shows the various addresses of these registers.

State machine 218 may generate a microprocessor event and stop itself. The device stops only when the event mask bit is set. Access is then gained in the usual way when servicing this event. An event is caused by a call to a reset address (○ × ○○). The call doesn't actually happen, it just fires the event after the command has been executed. Nevertheless, it remains in the command ROM output for inspection.

The state machine 218 of the present invention has a mode that is a single step through its command. The single step begins by setting the bits in the MSSR register to zero. The device then stops before each command. The stop status is indicated by "1" = stop. Instructions for execution are the output state of the instruction ROM and can be converted via microprocessor access. Write "1" to bit 1 of the MSSR register to restart the device. All of these bit registers require microprocessor access before they can be accessed synchronously.

[State Machine U Code Map]

Table 25 shows the micro code map of the state machine of the present invention.

TABLE 25

[State machine U codeword]

Table 26 likewise shows the micro codewords of the state machine according to the invention.

TABLE 26

From here ;

a = address

s = address substitution

c = call or jump

Condition = jump condition code; And

v = arithmetic core valid instruction

Arithmetic Core

In the present invention, arithmetic core 219 performs all data manipulation in MSM 218. As shown in FIG. 67, the overall structure of arithmetic core 219 includes functional blocks that select their inputs on a valid bus and provide the bus as an output.

Arithmetic Core 219 is 32 optical bits and consists of bit-slices that allow 8, 16, 24 or 32-bit data paths to be built in other implementations.

As shown in FIG. 68, the arithmetic core 219 of the present invention comprises: a coconn unit 360 for communicating with the data flow; ALU222 to perform calculations (and possibly other functions); It has three main functional blocks in register file 221 that accommodate all registers. All output buses are also shown in FIG. Input to the block is selected on these buses. The size of these selectors and their inputs can vary and are under U code control.

[ALU]

The ALU block 222 according to the present invention is responsive to all arithmetic and numeric manipulations in the arithmetic core. This allows for very complex calculations (such as recycling, multiplication, splitting) to be performed by a combination of relatively simple operations (i.e., shifting, reversing, adding). Each of these blocks is described below. We provide examples of how they are used in Arithmetic Core 219 to perform more complex calculations overall.

[Shift Block]

In the present invention, the “shift” block is a 1 bit left, right shift, or no shift. The 1-bit bus K rotates in words like an extra bit. This is shown in Table 27.

TABLE 27

If SS = 0601, "NOP" signals to ALU222 as a whole. This is an NO operation, which prevents any state flag from starting to change in the last operation.

[Carry block]

The carry block picks up or clears the move bit in the state register. In single word addition and subtraction operations, the transfer bit is cleared, while in compound word operation, the carry (feed) generated in the preceding operation (and stored in the status flag) is used as the transfer. This is shown in Table 28.

TABLE 28

[Condition block]

The carry of block conditions, added water and ALU core functions according to the present invention is shown in Table 29.

TABLE 29

[ALU Core]

The ALU Core 222 of the present invention uses two complementary arithmetic to perform simple logic sets and arithmetic functions. These are shown in Table 30.

TABLE 30

Four status flags are generated as a result of the ALU Core 222 (see Table 31). All of these are stored in register file 221 (as shown in Table 36) and sent back to state machine 218 for comparison with condition codes.

Table 31

[ALU code word]

Table 32 shows ALV microcode words.

Table 32

From here,

ss: shift block control,

ii: condition block control,

ff: ALU core control

c: carry block control.

[Use of ALU]

Table 33 shows the bit patterns for the different functions of the ALU according to the present invention.

Table 33

[Register file]

69 shows register file 221 of the present invention. Register file 221 has 64-32-bit word registers. Register file 221 may address some words. In other words, the file can address a 64 × 32 bit, 128 × 16 bit, 256 × 8 bit, 512 × 4 bit, 1024 × 2 bit, or 2048 × 1 bit format. The address has a portion either given directly from the U code or replaced from a special register. This allows indexed access of the register.

In each function, read-modify-write is done on one single register. Read-Modify-Write is convenient for writing some words to a file. The record source is determined by its own independent U code and external multiplexing device. If no recording is desired, the output of register file 221 is selected by the multiplexing device.

Some words are treated as either positive or non-negative numbers, depending on bit 0 of the mode register. If some words are negative (ie have their MSB set) they are stretched to the maximum width of the bus. This facilitates the use of some words in arithmetic.

The three locations in the register file 221 of the present invention are also connected to the assigned bus but are available in parallel with the other register file locations. These are the A and B registers and the status registers shown in FIG. The register file also includes an index register for address substitution along with a terminal count register, a constant register, and a mode register that specifies the mode of the register file.

[Register File Addressing]

The addressing according to the present invention has to deal with two other features: variable length address accessing the width of the word change, and address substitution.

Some word addresses require long addresses. Thus all addresses are of variable length and encoded as follows; Where a is the address bit and the minimum significance of the address bit is the “s” replacement bit.

Table 34

Addressing is a big endian. In other words, the higher and more significant part of the word is addressed with the lower address.

The address portion “a ... a” can be replaced with one of the index registers. By way of example, using an address of an 8-bit word as shown in Table 34, Table 35 shows how to limit the minimum number of significant bits to be replaced. All descendants are replaced.

Table 35

For example, replacing 4 bits with a 32-bit address has the form 0b000001aaa01111, or replacing zero bits with a 1-bit address has the form 0b1aaaaaaaaaaaa0.

In the present invention, the replacement comes from one of the 28 non-index registers and is specified in the register file U codeword. Therefore, it can be seen that the maximum of 8 bits can be replaced by the address.

In the above table, it can be seen that illegal addresses such as 0b0000000000000 or 0b11111111111111 can be used. Illegal addresses result in no address being accessed and leaving the output bus of an unknown register file.

[Register File Register Type]

In the present invention, there are a plurality of register file register types. Each of them is as follows.

Independently Bused Registers

The three registers (A, B, and status registers) have their own assigned buses that are accessible in the normal way in the register file. This allows the register to be placed further on arithmetic core 219 and to be accessible parallel to the other in the register file. The independent bus is only accessible to registers at other sufficient widths, i.e. 32 bit wide.

There are no U code records possible in these registers. Writing to them is done only by an external multiplexing device which itself has a U code control word. To prevent writing, they must be recorded at their own values, as shown in FIG.

Independent bus writes are suppressed when independent bus registers are written as in the register file.

The status register is implemented as an independent bus register. The bits in the register are specified in Table 36.

TABLE 36

Index and Terminal Count Registers

A 28-bit index register is installed to replace the address. One of these becomes incrementable per instruction under the control of the U code. As the incremented register passes, its terminal count is reset to zero.

The index registers are referred to as Y and Z having terminal count registers U and V, respectively. All of these are accessible to the register file.

Index register Z has a predetermined decoder attached to its output (currently this decode is inverted). Depending on the index mode in the mode register (bit 1), this decoder is used as an address replacement, and read from Z in the register file (index mode = 1 read decode, index mode = 0 read count).

Constant registers

In the present invention, the 32-bit location of the 16 register files is a predetermined constant. These are read into regular registers. Writing to these locations has no effect. (The constant chosen in the present embodiment is 0 to 7. However, of course, other constants can be used.)

Execution of this constant in accordance with the present invention does not require constant buses in certain areas and arithmetic cores in U code. However, it limits the constants available to the program. These constants are programmed into the unit temporary base. In addition, very frequently used values can be connected to the multiplexer if necessary.

[Register File Address Map]

Table 37 shows the register file address map of the present invention.

TABLE 37

[Register File U Code Word]

Table 38 shows the register file microcode words for the present invention.

Table 38

From here

a = full register file address (always 12 bits)

s = replacement bits

r = for replacement

incremental index register specified by l = r

[Token port]

The token port of the present invention is the connection of the arithmetic core to the data stream. This is a two wire interface connection.

Data at the token port input is defined only during the token port read cycle. Therefore, this should only be used during the read cycle.

If the input port does not contain valid data during the read cycle or if the output port is not allowed during the write cycle, the arithmetic core will stop. Thus, the arithmetic core does not work, does not read new U code words, and does not write registers. The arithmetic core will only restart when these conditions are not present.

[Token Port U Code Word]

Table 39 depicts token port micro code words.

TABLE 39

From here

l = read into input port

o = read from output port

[Multiplexer]

The selection of the source for the blocks is done by using a multiplexer. Almost any combination of buses is allowed (except that input to a function block, eg, ALU, must be from a storage block (eg token port or register file)).

The multiplexer is 2, 4 or 8 inputs. Therefore, they use one, two or three bit words respectively to control their input selection.

[UPI memory map]

Table 40 shows an MSM address map in accordance with the present invention.

TABLE 40

[Preface]

In the MPEG coding standards (EGMP-1 and MPEG-2), the quantified coefficients are coded as "imaginary." Each event is encoded as RUN and LEVEL. RUN is the number of zero coefficients that precede nonzero coefficients. LEVEL is the value of the coefficient. Moreover, in one particular idea a block terminator character is used after the last non-zero coefficient to indicate that the rest of the blocks are all zeros.

For example, assume the following coefficient sequence:

1, -7, 0, 3, 0, 0, 0, -1, 0, 0, 0, 0, ... 0 (total 64 coefficients)

These are modeled by the following ideas expressed as (RUN, LEVEL).

(0,1) (0,7) (1,3) (3, -1) (EOB)

It is the task of the inversion modeler to reverse the modeling process so that each of the 64 coefficients is represented in the singular for subsequent processing.

[interface]

The following signal pins are used to pass data into the inversion model of the present invention:

Level [11: 0]

Run [5: 0]

In-extn

In-valid

In-accept

Tokens are passed on the level [11: 0] bus (low order 8 bits; at level [7: 0])

RUN [5: 0] acts as an auxiliary bus with RUN information. This means that the DATA token has no meaning except in the data word.

The following signals are used at the output of the inversion model:

Out_data [11: 0]

Out_extn

Out_valid

Out_accept

[Functional description]

The data in the DATA token is expanded so that there are always 64 coefficients in the DATA token provided to the output of the inversion model. In most cases, the final data word of the DATA token ensures that no 64th order count occurs. This is not an error, only the EOB mapping is encoded in the bit stream at this point. Therefore, in this state, the inversion modeler must continue to output zero data token words until a total of 64 coefficients are produced at the output.

In some situations (eg, when a data error occurs), the DATA token at the input to the inversion modeler may represent more than 64 coefficients. In this state, the modeler should discard all the extra data and generate a token from its output containing only 64 coefficients.

All non-DATA tokens appearing at the input are simply passed to the output of the inversion modeler to be unmodulated.

[Timing Requirements]

It is a requirement of the present invention that the data flow through the inversion model at the clock ratio.

In situations where there is no gap in the input to one model and the circuit connected to the output does not cause one model to stop (i.e. in-valid = 1, out-accept = 1), the output of one model per clock cycle A new data word appears. In this state, however, since non-zero RUN (in the DATA token) generates more than one data word for each input, one model may not accept new data at its input every single clock cycle.

[Microprocessor Interface Access]

The inversion modeler circuit of the present invention is not required to be connected to the MPI in its normal operating mode. Error conditions (excessive counts) do not cause microprocessor interrupts. This is handled internally by discarding the extra data.

However, microprocessor access is required for the snooper (test) circuit at the input of the block.

[Preface]

In the MPEG coding standard, the coefficients are “zig-zag” scanned such that low frequency coefficients are delivered before high frequency coefficients.

According to the present invention, it is the function of the reverse zig-zag to transform a one-dimensional strip of coefficients received from the inversion modeler into a two-dimensional array of coefficients that can be processed by IDCT.

In MPEG-1, only one scan path is used, meaning zig-zag (ie name). However, MPEG-2 uses two scan paths. The first is the original MPEG-1 path, and the second is optimized for use in interlaced scan coding with unusually large vertical frequency components.

In addition to the coefficients clearly transferred in the zigzag scan order, the quantification matrix is likewise transmitted downward in the zigzag scan order. This occurs in MPEG-1, H.261 and JPEG. As a result, the present invention has its quantizer before reverse zig-zag (performed as part of IDCT). Therefore, this quantifier acts on a one-dimensional strip of coefficients arriving in the same order as the downwardly transmitted quantification matrix coefficients. Thus, the simple should associate the first coefficient with the first matrix element, the second coefficient with the second matrix element, and so forth.

However, since there are two scan paths in MPEG-2, a new approach has been taken in the present invention where the reverse zig-zag precedes the inverse quantifier. The count and downlink transmission matrices are inverted scanned and the inverted quantifier operates on two-dimensional data. This is possible because in all three representations of the data (two zig-zag scans and raster scan order at the output of 1ZZ) the first coefficient is always first and the last coefficient is always last. Since the first coefficient is a DC term, it is specially processed in one quant. The final coefficient is specially handled because it needs to be changed as a function of the values of all other coefficients as a result of the mismatch control. (Hence this must be the last.) 62 Residual coefficients are all processed in the same way (except that each has its own quantification matrix element).

[interface]

The following signals are used at the reverse zig-zag input of the present invention.

In-data [11: 0]

In-extn

In-valid

In-accept

The following signals are used at the output of the reverse zig-zag.

Out-data [11: 0]

Out-extn

In-valid

Out-accept

[Functional description]

1ZZ responds to the following tokens:

PICTURE _ START

ALTERNATE _ SCAN

DATA

QUANT _ TABLE

All other tokens are passed through 1ZZ and do not change.

The PICTURE_START token resets the internal state of 1ZZ where either one of the two scan paths (eg, alternate_scan) indicates zero (indicative of MPEG-1 scan).

ALTERNATE_SCAN is a token that can assign the value Oxe6 to the mask Oxfe.

The ALTERNATE _ SCAN token is shown in Table 41.

Table 41

"S" is an indication of the scan to use for subsequent DATA, so it is sent into the 1ZZ register "alternate_scan".

The DATA token is rearranged according to the scan path zero (MPEC-1 scan path) regardless of the setting of alternate_scan. alternate_scan must be retained (ie, not set to zero) of any value, so that subsequent DATA tokens are correctly processed.

The QUANT_TABLE token is rearranged according to the scan path zero (MPEG-1 scan path), regardless of the setting of alternate_scan. alternate_scan must be retained at any value in order for subsequent DATA tokens to be processed correctly. (Ie it should not be set to zero)

[Hunger Token]

Both DATA and QUANT_TABLE may be malformed. Obviously, the DATA token must be accurate because it must be guaranteed that 1 model is formed correctly. However, this guarantee is not useful for QUANT_TABLE. Since malformed QUANT_TABLE processing must be implemented, this must be done for DATA tokens as well.

In accordance with the present invention, the DATA and QUANT_TABLE tokens are too short when appearing at the input to 1ZZ, so the exact number of 64 data words must be derived from the tokens at the output. The data contained in these words is not critical and is any waste material that will be generated in the rearranged RAM prior to the initiation of the token. Similarly, DATA and QUANT_TABLE tokens that are too long should derive exactly formed tokens in the output. The first 64 coefficients (matrix elements) should be used and the rest should be discarded.

Following the malformed token, all subsequent (exactly formed) tokens must be properly processed.

There is no requirement for a microprocessor interface error (interrupt) to be generated.

Raster Scanning Sequence

At the output of 1ZZ, the DATA and QUANT_TABLE tokens of the present invention represent two-dimensional data. However, the coefficient is still actually delivered as the number of one-dimensional series. The question arises whether the data should be passed in columns or in rows.

The prediction circuit requires that pixel-region data be organized in raster-scanning order. Since the IDCT displaces the data, it must be something else around it going into the IDCT. Table 42 shows the order of the coefficients passed in the output of 1ZZ for the DATA and QUANT_TABLE tokens.

Table 42

[Microprocessor Interface Access]

There is no requirement for microprocessor access in the normal function of 1ZZ. However, access may be required so that rearranged RAM can be tested. You can also predict the requirements for snoopers. One for one model start for both blocks is sufficient.

[Preface]

This section deals with forecasts. In this introduction, all possible prediction modes are listed and a diagram is provided to explain exactly what should be done.

This section does not give special attention to operations such as half-pixel filtering that occur in the horizontal dimension. This is because these operations are the same as those in Brolly. However, things are very different in the vertical dimension because of the interlaced picture format.

[Prediction in Framed Image]

[Frame-Based Prediction]

In this mode, prediction is formed from the reference frame. The result is that two reference fields are first combined into a frame and then prediction is made from this frame. This is exactly the same situation disclosed in Brawley.

Half-pixel filtering may be made in the vertical dimension, which is triggered by the least significant bit of the vector. In addition to the least significant bit, the next most significant bit (bit 1) is of special importance because the bit determines whether the upper line of the prediction is from the upper reference field or the lower reference field.

Therefore, four cases should be considered, each dependent on the least significant two-bit binary value of the vertical vector.

[1] = 0, vector [0] = 1

Similarly, as shown in FIG. 72, lines 17 (9) are read, lines 9 (5) are read from the upper reference field and lines 8 (4) are read from the lower reference field.

Vector [1] = 1, vector [0] = 0

Again, as shown in FIG. 73, only 16 (8) lines were read but the upper line of the prediction was read from the lower reference field.

Vector [1] = 1, vector [0] -1

And FIG. 74 shows that 17 (9) lines are read, 8 (4) lines are read from the upper reference field, and 9 (5) lines are read from the lower reference field.

Thus, bit 1 indicates which reference field holds the top line that should be read to generate prediction. Moreover, if bit 0 is also set, this indicates which reference field has an extra line so that half-pixel filtering can be done.

Obviously, half-pixel prediction cannot be done until both fields are read from the DRAM.

Great care must also be taken when scaling the vertical motion vector to obtain an offset in field storage. Table 43 below shows the effect.

Table 43

[Field-based prediction (frame picture)]

In this mode, each field is processed independently. Separate vectors are used for each of the two fields. Associated with each vector is an additional single bit flag (motion-vertical-field-select), which indicates whether prediction should be made from the upper reference field or from the lower reference field. The lower bits of the vector indicate the need for half-pixel filtering but have no particular significance of bit 1. The field vector measures frame vectors of different units; A field vector with a value of n represents the same actual displacement (on glass) as with a frame vector with a value of 2n.

However, there are 16 cases to consider. (The reason is that there are four binary variables; motion-field-select for each of the two vectors and 0 bits for each of the two vectors). There are too many cases to describe, so It deals only with the prediction of. The bottom field is obtained in a similar way.

As shown in FIG. 75, motion-vertical-field-select = 0, vector [0] = 0

Line 8 (4) is read from the upper reference field to form the upper field of prediction.

FIG. 76 shows motion-vertical-field-select = 0 and vector [0] = 1. Line 9 (5) is read from the upper reference field and then half-pixel filtered to form the upper field of prediction.

Similarly, Figure 77 depicts motion-vertical-field-select = 1, vector [0] = 0. Line 8 (4) is read from the lower reference field to form the upper field of prediction.

And, Figure 78 illustrates motion-vertical-field-select = 1, vector [0] = 1.

Line 99 (5) is read from the lower reference field and then half-pixel filtered to form the upper field of prediction.

[Double Prime (in frame image)]

Double prime is a special case of the field-based prediction of the previous part. In essence, double-prime combines two features.

Only one motion vector is effectively delivered by encoding the vector in a special way so that four independent field predictions are formed (to some extent they are independent of having different vectors). Thus the vector overhead is dramatically reduced.

For each field, prediction information is read from each reference field. This is then averaged to form the final prediction. This is very similar to the case of B-pictures when separate forward and backward predictions are made and then averaged.

In the present invention, vector decoding will all be done at the parser. Thus, when the prediction circuit receives the data, there will actually be four separation vectors. (For each field, prediction information is read from each reference field. This is then averaged to form the final prediction. This is very much like the case of B-pictures when separate forward and backward predictions are made and then averaged. similar.

In the present invention, vector decoding will all be done at the parser. Thus, when the prediction circuit receives the data, there will actually be four separation vectors. )

Double-prime averaging is done by reusing the B-frame averaging circuit (double-prime cannot itself be used for B-frames). Therefore, only relevant merging for the prediction circuit is included in the signaling, which indicates that backward prediction (using backward vector tokens, etc.) should be made from the forward reference field (as opposed to the backward reference field). Since the P-picture never normally requires backward prediction, the prediction circuit only needs to keep a record of the picture type (P or B) so that it can determine which reference store is used for the "backward" prediction.

[Prediction in Field Image]

[Field-based prediction]

This is very similar to field-based prediction in frame pictures. There are four cases depending on the motion-vertical-field-select and the least significant bit of the motion vector. Since the prediction is simply for a decoded picture, it is inappropriate to discuss the top-field and the bottom-field in the prediction that is made (this is either all top-field or all bottom-field).

FIG. 79 shows motion-vertical-field-select = 0 and vector [0] = 0.

Line 16 (8) is read from the upper reference field to form the prediction.

FIG. 80 shows motion-vertical-field-select = 0 and vector [0] = 1.

Line 17 (9) is read from the upper reference field and half-pixel filtered to provide prediction.

Figure 81 depicts motion_vertical_field_select = 1, vector [0] = 0.

Line 16 (8) is read from the lower reference field to form the prediction.

FIG. 82 shows motion_vertical_field_select = 0, vector [0] = 1.

Line 17 (9) is read from the lower reference field and half-pixel filtered to provide prediction.

[16 × 8 MC]

In this mode, the microblocks are divided into 16 × 8 regions overlapping each other. For each region, a separate field vector is passed. Again, there are 16 cases to consider (because there are four binary variables; motion_vertical_field_select for each of the two vectors and bit 0 for each of the two vectors). Again, there are too many cases to illustrate, so the description below only covers the upper 16x8 area. The lower region is obtained in a similar way.

FIG. 83 shows motion_vertical_field_select = 0, vector [0] = 0.

Line 8 (4) is read from the upper reference field to form a prediction of the upper 16x8 region.

FIG. 84 depicts motion_vertical_field_select = 0, vector [0] = 1.

Line 9 (5) is read from the upper reference field and half-pixel filtered to form a prediction of the upper 16x8 region.

FIG. 85 shows motion_vertical_field_select = 1, vector [0] = 0.

Line 8 (4) is read from the lower reference field to form a prediction of the upper 16x8 region.

Figure 86 depicts motion_vertical_field_select = 1, vector [0] = 1.

Line 9 (5) is read from the lower reference field and half-pixel filtered to form the prediction of the upper 16x8 region.

[Double Prime in Field Image]

Double prime in a field picture is simply a special case of field prediction in a field picture. Two field vectors are used (in addition to referring to the top reference field, see the bottom reference field and the parser guarantees this). One of the predictions appears to make a backward prediction, but since it is a P-picture, the prediction circuitry interrupts it as a second forward prediction. The two resulting predictions are then averaged using the same circuit used for B-frame averaging.

[General organization]

87 shows the overall organization of the display pipeline in accordance with the present invention. Data reaches from a DRAM interface to a single multiple interface. Moreover, the DRAM interface supplies data to the processed line up to the next 32 byte boundary over the correct number of bytes. However, the pixels are directed towards the end of the line, which may exist outside the intended display area.

In addition to the data, the DRAM interface supplies one bit for each channel Y, Cr and (b), each channel indicating whether the byte is last in the current display line. Another bit is supplied to indicate from which field the data comes.

The first block in the display pipeline of the present invention divides three channels. Chrominance (Cr and C6) data is fed to a vertical upsampler 210. Luminance (Y) data can be delayed in the FIFO as needed.

The vertical upsampler 210 is tasked to upsample the chrominance data by a 2: 1 factor so that the line of crossnanance data equals the luminance data. To do this, the vertical upsampler stores each line of chrominance data and generates an output pixel, which is inserted between this line and subsequent lines.

The next step in the display pipeline is named "Horizontal Alignment 370". This is done as part of the horizontal upsampler 212. Its task is to align the data so that each first pixel of each of the three channels at the start of each line is correctly fed to the horizontal upsampler 212.

At the end of each line, channels generally "consume data" at different times. “Horizontal Alignment” block 370 has the task of discarding redundant data from channels with too much data while stopping other channels to wait until all three channels are aligned and start the next display line.

In the present invention, the horizontal upsampler 212 fills the glass of the TV screen by stretching the data by up-sampling the data horizontally. To save silicon area, a filter is allocated between the three channels. This can be done because the total output ratio of the filter must be 27 Mbytes / s (clock ratio). As this data is multiplexed in CCIR 601 order, the generated data strips are simply multiplexed only into the final data stream.

Horizontal upsampler 212 simply takes the amount of data supplied by the DRAM interface and scales this by a selection factor. In general, they produce too little or too much data about the actual line length in the raster. This is handled in the output multiplex.

In addition, the “horizontal alignment” block 370 need not know how many pixels of each channel are required to complete the line. It is very difficult to calculate this number because the relationship between the number of input pixels to the output pixel is not very simple in the upsampling filter. Horizontal alignment block 370 simply supplies data to the horizontal upsampler 212 of each of its three channels “as required”. That is, the horizontal upsampler "pulls" the required number of pixels into it in the order required. At the end of the display line, one of the channels consumes data first, which indicates that residual data (if any) for the other channels should be discarded.

The VTG 333 simply counts through the raster and generates a series of timing signals that are fed to the output multiplex 371. Some of these signals are internal signals, and they tell how output multiplex 371 establishes the final raster. Other signals are "external" signals such as sync and blanking, which are also fed to the output multiplex 371 circuit and delayed by the same number of clock cycles as the data.

The output multiplex 371 block has several tasks. Perhaps the most important of these is the task of removing the two wire “interfaces” from the data. Data supplied from horizontal upsampler 212 still has an associated Valid signal (and the output multiplex provides an accept signal). The data at the output of the multiplex does not have a two-wire interface and is simply clocked by one byte per clock cycle.

The output multiplex 371 has the task of painting a border around the picture. The upper and left boundaries are painted under the control of VTG 333. The VTG 333 simply informs the output multiplex 371 to generate the required number of pixels of the border color. At the right and bottom of the picture, the output multiplex 371 paints its own border, which is done because it has consumed picture data.

The final block in the display pipeline is an 8-bit to 16-bit output mode converter 372. This is very simply a flip-flop and multiplexer. This is intended to be done on the output PAD itself. By doing this, one can simply define an 8-bit bus rather than a 16-bit bus. Each bit goes to two output pads.

[Horizontal Upsampler]

[Preface]

In accordance with the present invention, the horizontal upsampler 212 performs the task of upsampling or interpolating to stretch the decoded picture to fit the display raster. Upsampler 212 of the present invention can operate in four modes:

1) 1: 1-Output is same as input

2) 2: 1

3) 3: 2

4) 4: 3

After some image simulation and consideration of possible transitions, three tap filters are used to decide to interpolate.

A filter is a "polyphase" filter in that each successive output occurs using a different set of filter coefficients. The number of phases is always the same as the molecule of the upsampling ratio. Thus, a 4: 3 upsampler has four phases and every four output samples are generated using the same filter coefficients.

Upsampler 212 generates more output data than received as input data. In fact, the number of phases for which the filter does not receive new inputs differs between the numerator and denominator of the upsampling ratio. In each ratio (except 1: 1), this is one. Therefore, for each completion cycle around the phase, no new input data is received in one of the phases. In this case the data is the same as for the previous phase. However, the filter coefficient is different from the previous phase.

[4: 3 upsampling]

In 4: 3 upsampling, filter coefficients are shown in Table 44, and FIG. 88 shows a filter in operation. The output pixel is formed as the weighed average of the input pixels.

Table 44

Note that no new input data is received before the final phase (phase 3) is calculated.

[3: 2 upsampling]

Table 45 shows 3: 2 upsampling and FIG. 89 shows the filter behavior.

TABLE 45

[2: 1 upsampling]

Similarly, Table 46 shows 2: 1 upsampling and FIG. 90 shows its filtering.

TABLE 46

Note that Phase 1 is equally well described as having filter coefficients 128, 128, 0. This has the advantage that the filter coefficients are the same as for phase 2 of the 4: 3 upsampler. However, there is a disadvantage that the law of not receiving a new input is negated when calculating the "final phase".

Boundary effect

At the edge of the image, it is necessary to generate an output pixel formed from a pixel lying outside the image area. To avoid this problem, it is necessary to pixel repeat the edge pixels so that the filter proceeds without realizing at the edge of the image.

In the case of a three tap filter as in the present invention, it is necessary to repeat one on the left side of the image, only one on the right side (five tap filters on the left side and two on the right side). This is shown in FIG.

Therefore, conceptually, the transition appears to be formed of two boxes. Since data that is a product of the DRAM interface 16 pixels in width is always supplied, a plan is not properly performed when the image is not a product of 16 pixels in width.

[Number of output pixels]

In the present invention, the upsampler generates a limited number of output pixels for a predetermined number of input pixels. This is important because it allows the parser state to determine how many pixels occur at the output of the upsampler and therefore how many pixels should be finished (or border pixels added) to fit the image into the raster.

The first valid output from the horizontal upsampler occurs in response to the third pixel input to the upsampler (since it is a three tap filter). Since one pixel is repeated, this occurs when the second real pixel is input to the upsampler.

The final valid output occurs when all possible output samples have been generated in response to the last (i.e., repeated) pixel input. Since the final phase of the polyphase filter is calculated using the same input data as the second-final phase, one or two output pixels can be generated as a result of this last repeating pixel entering the upsampler.

If this is done, the upsampler will generate a "q" output sample:

Equation 1

q = N (pDIVM) + (pREMM)

In response to the “P” input sample for the N: M upsampler

For example, for a 4: 3 upsampler, Table 47 can be depicted as follows.

TABLE 47

[Position signal]

Two signals are delivered with the video data in the present invention. They allow output multiplexing to ensure that the data is painted into the proper location within the output raster.

This includes:

Last_in_line

Field_id

last_in_line responds to one pixel time and signal, with the associated pixel being the last pixel in the scan line.

field_id indicates which field the data belongs to. “0” spatially indicates the upper field. “1” spatially indicates the lower field. This designation is applied before any boundary lines are applied to the decoded image. field_id changes the state of one pixel too early between the second and last and last pixels of the field. This allows the last pixel of the field to be defined without waiting for the first pixel of the next field. However, if decoding stops for some reason, the "next field" does not exist. The field_id signal is shown in FIG.

If a true field indicator is required, it can be obtained by delaying the field-id by one pixel time.

Since these signals work their way with the data through the entire display pipeline, it is important to use two signals instead of three (allowing the final pixel in the field signal), because this saves a lot of flip-flops. Because.

Multiplexed data

Care should be taken when position signals are applied to the multiplexed data.

Data is multiplexed in the order of Cby Cry.

In the present invention, the three samples (Cby Cr) are incident together in time and thus appear inseparably. The residual byte y is located between the preceding (Cby Cr) pixel and the subsequent (Cby Cr) pixel.

As a result, the last byte in the line is Cr or y (upsampling by 3: 2 generates an odd number of Y pixels). If the last byte on the line is Cr, there is a discontinuity in the multiple signals because the first byte of the line is always Cb:

(CbY, Cr) (Y) (CbY, Cr) ＼ (CbY, Cr) (Y) (CbY, Cr)

[Horizontal alignment]

At the input of the upsampler, there is no guarantee that three different channels will be lined up.

In order to achieve alignment, in the present invention, the "protocol" between the horizontal upsampler and the horizontal alignment blocks must match. According to the invention, the protocol is carried out as follows:

Horizontal blocks feed the pixels to the horizontal upsampler as needed. When data is consumed for a given channel, a signal is output to the filter using a signal representing the last pixel of the line. This only happens for repetitive pixels.

The horizontal upsampler only supplies the last pixel from a given channel once and does not request another pixel from that channel in the current line. However, the filter continues to operate by taking any necessary pixels from other channels until just before requesting a pixel from a channel known to have consumed data. The filter marks the last pixel and can be generated as the last in the line at the output. At this point, it is reset itself in preparation for the next line of data.

The horizontal upsampler monitors whether the filter receives data for a channel that has already been exhausted, and the filter requires the first pixel of the next line. At this point, all remaining pixels on the other two channels are discarded. The next pixel to be supplied to each of these channels will be the first pixel of the line. Although it is convenient to consider two separate blocks (horizontal alignment block and horizontal upsampler block), the two are performed together to illustrate the operation.

[Upsampling ratio]

The upsampling ratio is supplied to the filter as a 2-bit binary number. In order for the filter to operate in a damping manner, the upsampling ratio must be sampled by its own upsampler once per field time. The circuit for supplying the ratio is allowed to update the sampling ratio in preparation for the next field at any time in the current field.

The ratio should be sampled immediately after the last field of the previous field when the first pixel of each field is actually received. In this way, the first field after reset (or after any stop in decoding) is not sampled at the correct ratio.

[Video Timing Generation Ratio]

[Preface]

This part discloses a video timing generator circuit VTG 333 according to the present invention. The VTG responds to the note to generate several similar video sync signals and also to maintain knowledge of the current raster position of the display system. This allows the VTG to provide control signals for the output multiplex and select the active video, boundary and blanking source for the output. Analog and digital standards are supported with two selectable frame sizes (PAL and NTSC) and associated sync behavior during setup. The boundary or trimming side is specified in the token that loads the wiring input to the VTG.

[Horizontal Timing]

Horizontal timing variables are illustrated in FIG. 94. These are divided into variances and fixed values (relative to PAL or NTSC) which are variables associated with any boundary or refinement that can be specified.

The ratio characteristic of the displayed video places a requirement on half-line based calculations, with several timing points shown separately for each half line.

The line includes the initial blanking cycle, the insertion of the SAV token, the activity cycle, the insertion of the EAV token and the trailing blanking cycle. Among the blanking lines, the active area has a blank value inserted in place of the boundary and data.

Line sync pulses appear at the beginning of every line HSYNC. In a given blanking line, two sync pulses appear, one at the start and the other after the first half line. Their width depends on which vertical area is active: equalization or serration (field sink).

During the initial horizontal blanking period, pixels are discarded according to the trim value (if the trim bit is set)-a fixed cycle of 120 cycles is allowed to discard the RHS trim pixel from the preceding line. The LHS pixel for the current line is discarded and the pixels are frozen until the start of the active area. There should be no gaps in the data stream where pixels are discarded or distortion will occur.

However, if the corp bit is not set, the boundary is constructed by reinserting the boundary value for the period of boundary L followed by the data for the picture width and the boundary at the end of the active area: the boundary R value is calculated. There is no need.

The total vertical boundary and the trim width are specified in pixels. The LHS boundary / smoothing values must be multiplexed to ensure two pixels for sampling. As a result, the value must be multiplexed to four in the item of the clock cycle. This can be accomplished by removing masking the least significant two bits from the original total threshold in the pixel. For example, if the specified boundary is 91 pixels, the left boundary will be 88 cycles long and the image width will be 2 cycles 720-91.

The pixel string reaching the output max max is filled to provide 32 pixel blocks.

Considering the scaling factor supported and this, the maximum number of pixels received in one line will be 832. This means that the maximum smoothing value is 112 pixels and the smoothing cycle is given 112 at the LHS and RHS.

[Vertical Timing-Arm (PAL)]

Vertical timing parameters for the PAL according to the present invention are shown in FIG. Two shields are shown separately and they have slightly different timing. Analysis parameters are represented by shaded areas and each field is the same, and digital parameters are shown by waveforms. For simplicity, the case of zero-boundary is shown. If a non-zero vertical boundary is specified, the boundary is inserted for the image height data for the period of the boundary T until the boundary becomes the boundary of the active area. The boundary T and the image height are calculated by analyzing the boundary L and the image width (horizontal timing), respectively. The initial boundary (boundary T) is multiplexed to 4, and for the half line item this time must be remultiplexed because the upper boundary must be multiplexed to 2.

MPEG encodes 576 lines of video for PAL, while the analog standard specifies 525 million. This difference is adjusted by selecting the output data for 576 half-lines per field and expressing the analog blanking signal for only the required 575 lines.

[Vertical Timing-NTSC]

Next, NTSC vertical timing is illustrated in FIG. 96 in accordance with the present invention. This is essentially similar to PAL timing, although slightly more complicated. MPEG encodes 480 lines of video for NTSC, while the analog standard specifies 483. This means that three lines of border must be inserted frame by frame to fill the gap (three half lines per field). Moreover, the fair vertical blanking indicator V is specified in a manner that requires additional boundary lines to be inserted as padding before the active video line. As explained earlier, non-zero vertical boundaries are inserted in addition to the lines already indicated. Moreover, vertical smoothing is not allowed in any standard.

There is currently some uncertainty about the digital blank signal V, because several reference sources provide contradictory information. There are two main timing possibilities, denoted V and V ', with associated boundary select signals SB and SB', respectively.

[VTG structure]

The video timing generator of the present invention includes separate machines for the horizontal and vertical timing regions. The vertical machine provides a control signal for the horizontal machine, which in turn provides a half-line incremental signal for the vertical counter.

Input to the VTG is:

Clock and reset

PAL, not NTSC

Horizontal boundary value by trim indicator

Vertical threshold

The output is:

Horizontal, vertical, and composite sink and blanking signals

Selection signal for data, boundary and blanking

Discard data bits for smoothing

Insert SAV and EVA

F and V values for the configuration of SAV and EAV

2-bit YUV position counter for SAV / EAV inserts

First line bit indicating the start of the initiator image

[Horizontal]

All outputs, including the sync signal, go to the output multiplex block, which can be kept in sync with the data. The horizontal machine is a counter with hardware to detect the arrival of various timing points as shown in FIG. The count runs from zero to half line length (this is different than for PAL and NTSC) and is repeated for each half line. There is a wire comparator for each fixed timing point, which is activated according to the standard. Furthermore, there are registers for the threshold value (one trimmed once per field), a subtractor for determining the pixel width, and an auxiliary counter for calculating from the threshold value to zero. This procedure occurs in parallel with the main half-line coining. The data path is 10 bits wide and 15 wire comparators are required to perform PAL and NTSC. The structure of this current embodiment is shown in FIG. 97 at an approximate size. The data path is evaluated as 360u × 330u.

In addition to the data path, most of the control logic in the VTG of the present invention is associated with a horizontal machine. This will probably amount to 100-200 gates.

The input to the horizontal machine is:

Clock and reset

Horizontal Threshold and Trim Bits

Line, Equalization, or Field Sink Indicators

PAL, not NTSC

Vertical blank

Insert vertical boundary

The output from the horizontal machine is:

Horizontal and synthetic blanks

Insert data

Insertion boundary

Insert blank value

. Discard input

Insert SAV or EAV and YUN Counts

(Hsync) vertical sync signal

Synthetic sink

· Start of line

Half-line increments

[Vertical machine]

The vertical data path has essentially the same structure as the horizontal data path, but has 22 hardware comparators (8 for PAL and 14 for NTSC). The main counter increments each half line, in turn counting half lines through each half line, and counting half-lines through each field. This is also 10 bits wide.

Furthermore, it is advantageous to multiplex the half-line pulse input with other more frequent clocks for testing purposes so that the vertical machine can operate independently of the horizontal machine.

The estimated size is 360u × 420u.

The input to the vertical machine is:

Clock and reset

PAL, not NTSC

Vertical threshold

Half-K line increment

The output from the vertical machine is:

Selective equivalence, field or line sink (synchronous)

Vertical blanks (analog)

Vertical sink

F, V, and V ′ bits for SAV / EAV configuration

Insert vertical boundary

Insert data

Insert blank value

Start of frame

Wiring Comparator Configuration

In the present invention, the wire comparator configuration is based on a string of a series of n-type transistors precharged or pulled up in a similar style as the memory string decoder. Typically, these comparators are about 8u high in a given evaluation area.

[Output multiplex]

The output multiplex of the present invention has the task of putting together data for display. This combines the data arriving from the front of the display pipeline with timing information obtained from the VTC.

Another input task of the output multiplex is to eliminate two wire interfacing. All pipeline stages up to the output multiplex have a 2-wire interface, in fact the data arriving at the input of the output multiplex always arrives too early and is stopped by taking low accept. However, there is no two-wire interface at the output of the device.

In order to achieve this elimination of two-wire interfacing, the data supply power must be separated so that the DRAM does not stop the data reaching the output of the horizontal upsampler.

Basically, the output multiplex determines on the field by field basis whether or not to output a field of data. At some point, near the beginning of the first active line of the field, the output multiplex makes a decision. If there is valid data waiting on its input (i.e. low in_accept), the data output starts. On the other hand, if there is no valid data (eg, before the first picture is decoded), it will paint the border color over the entire picture.

In practice, this procedure is rather complicated because the output multiplex must ensure that data is painted into the correct fields. That is, valid data belonging to the correct field must wait before the display starts.

If at some point the data is no longer valid and at the same time it is expected that the output multiplex has valid data useful for painting into the display (which never happens), the output multiplex returns to the output boundary color to This continues for the rest.

[Boundary occurrence]

Fig. 98 shows the generation of the border colors for the left and right sides of the image display according to the present invention.

As shown, the VTG generates a border region on the left side of the picture by assuming a signal to select a border color in the output multiplex. However, on the right side of the image, the border color is generated by the output multerplex itself. This is done by recognizing that it "consumes" the data and paints the remaining width of the image in the border color.

Two interpretations of the "consumption" of the data are possible. One is that the output data from the horizontal upsampler is not valid. However, this does not mean here. In this case, one consumes data after the pixel indicated by the last_in_line signal has been included in the output stream while proceeding to the last in the line. 99 shows an equivalent action when clipping of the firing occurs.

As shown, the VTG sends a signal to the output multiplex to assume the signal to clip the pixel to the left side of the image and to tell the output multiplex to discard the input pixel. Once this occurs, the VTG signals to start the output multiplex to output the residual pixels. At the end of the active line (ie after 720 pixels), the VTG does not present a signal and the output multiplex discards any residual pixels in the data on its input. In general, there is a gap (in time) between the time that the VTG indicates a trimming occurrence and the start of the activity line. This greatly simplifies the configuration of the VTG. The output multiplex discards the pixel when the trim signal appears and waits until the start of the active line period.

[Output multiplex]

The output multiplex controls the multiplexing of the data of different sources together to form a CCIR 601 8-bit multiplexed data stream.

Timing (ie when multiplexed) is significantly controlled by the VTG. Output multiplexes are related to their high level issuance. For example, at the start of decoding, when the picture is not useful for display, the output multiplex will paint the border color over the entire picture. As a result, the first decoded picture reaches the horizontal upsampler. Typically, this does not occur conveniently at the beginning of the field. The output multiplex asks once per field hour, "Is there a valid daka ready for display?" Otherwise, it waits for the next field to occur (and any valid data found in between must wait for the start of the next field).

The output multiplex also ensures that the correct fields of data arriving from the SDRAM interface are painted into the correct fields of the PAL or NTSC raster.

Moreover, with regard to data, the output multiplex also selects the correct sync and blanking signal for output to the pin.

This facilitates access to a wide range of synthesized encoders, DAC's and the like. The registers for the output multiplex are shown in Table 48. The bits for output multiplex control are shown in Table 49.

There are four bytes of the MPI register associated with the output multiplex:

TABLE 48

Table 49

a. Regardless of the setting of the bit, the chrominance data (b and Cr) will be 0x80 (128 decimal) during blanking.

[Video Decoder Specification and Features]

In addition to the foregoing detailed description, the following disclosure regarding a preferred embodiment of a video decoder suitable for the practice of the present invention is also provided.

The present invention includes a highly integrated MPEG-2 video decoder that is easy to use. It supports all the requirements of the MPEG-2 main profile at the main level.

The system of the present invention is also a body construction (a single pin selects between PAL and NTSC operation), and in many applications it is possible to initiate and maintain video decoding without external software support. Error concealment and recovery is fully automatic. More demanding applications may use advanced configurations controlled by software that functions on an external microprocessor.

The present invention stores its own microcode in an on-chip ROM, thus eliminating the need for external ROM or downlink microcode before decoding is initiated. See also FIG.

The following more detailed description of the systems of the present invention are set forth below for ease of organization, clarity, and description, under the headings set forth below.

signal

Register map

Power supply

Logic level

Clock signal

Reset signal

Coded Data Interface Signal

Supply data via microprocessor

Switching between input modes

Reception ratio of encoded data

Coded Data Interface Timing

CDCLOCK

Video output signal

Video output control register

Border, Scaling, and Trimming

Video output control register

Video signal timing

MPI Signal

MPI Electrical Specification

Interrupt

Page registers

SDRAM Interface Signal

SDRAM Configuration

Connection of JTAG Pin in Non-JTAG System

Support command

characteristic

Conformance level for IEEE 1149.1

Start code detection register

Detection of start code

discard_all function

flag_picture_end function

start_code_search function

SCD Example-Channel Conversion

Parser registers

Error code

Process as user data

System organization

Signals and registers

Electrical specification

Coded data interface

Video output interface

Microprocessor interface

Synchronous DRAM Interface

JTAG interface

Start code detector

Video parser

Time stamp management

Address generator configuration

Mechanical information

This section contains a list of all signals (pins) used in connection with the present invention and a list of all registers available through the microprocessor interface (see Tables 50 and 51).

[signal]

TABLE 50

Table 51

[Register Map]

The register map of the present invention is divided into regions. The first 32 location is required for normal operation of the system. There are only 5 bits of address here. The next setup of 32 locations is what is required to install a non-coupled SRAM map in the address generator circuit.

The rest of the register map is for registers used for testing and diagnostic purposes only. It may be paged instead of these address generator registers.

Table 52

a Page_Selection should be kept at zero in normal operation. In this case, locations 0x20 ... 0x3f would contain an address generation user register.

Table 53 describes the page select registers.

Table 53

Table 54 shows an interrupt providing area.

TABLE 54

Table 55 shows the input circuit register of the present invention.

TABLE 55

Table 56 shows the start sign detector registers of the present invention.

TABLE 56

Table 57 shows a time stamp insert register according to the present invention.

Table 57

Similarly, Table 58 lists the video parser registers.

TABLE 58

The output control registers are shown in Table 59.

Table 59

[Test register]

The completed register map is shown in Tables 60-69.

TABLE 60

TABLE 61

Table 62

TABLE 63

TABLE 64

TABLE 65

TABLE 66

TABLE 67

TABLE 68

TABLE 69

[Power supply]

The present invention essentially operates with a 5V signal supply.

However, a 3.3V power supply is also supplied to enable simple connection to the synchronous DRAM.

TABLE 70

a D [15: 0], DA [11.0], DCKE, DCLKOUT, DCLKIN, DWE '; DCAS ′, DRAS ′, DCS ′ [1: 0] and TDCLK.

b The stresses that cause permanent damage to the device are greater than those listed here. This is only a stress ratio and none of these mentions the functional operation of the device or other conditions indicated in the operating part of this specification. Providing an absolute maximum rate condition for the extension of length affects reliability.

TABLE 71

Three different interface types are performed in accordance with the present invention. The standard (5V) TTL level is used as the microprocessor interface. Moreover, the 5V CMOS level is used as the coded data interface and the video output interface. The 3V LVTTL level is also used as the SDRAM interface.

[TTL (5V) level]

TABLE 72

a AC input parameter is measured at 1.4V measurement level.

b I _O ≤ I _OOC min

c This is the possibility of driving a steady state of the interface.

d When the open collector is maintained, the IRQ output pulls down to an impedance of 100Ω or less.

CMOS (5V) level

Since the CMOS input V _IHmin is approximately 70% of V _DD , V _ILmax is approximately 30% of V _DD . The values shown in Table 73 are for V _IH and V _IL at their respective operating limits.

TABLE 73

ai ^oh ≤ 1mA

b I _oH ≤ 4 mA

c I _OL ≤ 1 mA

d I _OL ≤ 4 mA

TABLE 74

a AC input parameter is measured at 1.4V measurement level.

b This is the possibility of driving a steady state of the interface. The transient current will be much larger.

[Clock signal]

The present invention uses one clock (SYSCLOCK) for almost all on-chip functions. Since this clock is used by the video output circuit, it is assumed that the 27 MHz clock is used so that the Video Timing Generator (VTG) generates the image at the calibration rate.

The second clock (CDCLOCK) may be used for the data clock encoded in the present invention. This clock synchronizes SYSCLOCK to allow data to be transferred to the system from a circuit that is not operating at a 27 MHz clock (perhaps a clock derived from a disk or network interface circuit).

Internally, the present invention derives a high speed clock for driving SDRAM using a phase closed loop (PLL). This clock outputs SDRAH as DCLKOUT. On-chip PLLs are used to derive an even display-space ratio. The requirements for SYSCLOCK are shown in FIG.

Table 75

It should be noted that the tolerance and stability of a clock should be desirable to meet the desired standard video line frequency.

[Reset signal]

The present invention uses three reset signals.

1) RESET ′

2) VTGRESET ′

3) TIMERESET ′

RESET 'is the main chip reset signal. All circuits are reset and in the reset states shown in the various tables as described herein. RESET 'must be LOW for at least four cycles after the power and clock are stable and correctly reset.

VTGRESET 'is used to reset the video timing generator of the present invention without affecting other aspects of the present invention.

TIMERESET 'is used as a time stamp processing circuit according to the present invention.

[Preface]

The coded data interface according to the invention is provided with a tweezers for use in supplying coded video data to the system. Alternatively, the encoded data can be recorded via the micro interface. This section discusses both methods.

If a dedicated pin is used, the coded data may be supplied as a simple stream of bytes or token. The token is added to the encoded code to enable the supply of other forms of information. For example, time stamp information can be transmitted using this scheme.

If a micro interface is used for the encoded data, then a token can be used. If the tokenhead is written to represent coded data (two registers are required for writing) and subsequent data, the coded data is simply written to the register.

Coded Data Interface Signals

Table 76 defines the coded data interface signals used in the present invention.

Table 76

CDVALID and CDACCEPT are used to control the transmission of data in accordance with the present invention. This type of protocol is referred to as a "two-wire" interface. Both signals must be at the rising edge of CDCLOCK to generate data transfer. Figure 102 shows the relationship between data (CD [7: 0] CDEXTN and BMODE) and CDVALID and CDACCEPT.

Note: If data is supplied via the encoded data interface pins, the microprocessor interface register “enable_mpi_input” must be zero (the microprocessor is in reset).

[Byte mode]

In the present invention, if BMODE is sampled high on the rising edge of CDCLOCK (and both CDVALID and CDACCEPT high), then the data is treated as simple incubated data. In fact, data is embedded directly in DATA. In this case, CDEXTN is ignored.

[Token Mode]

If BMODE is sampled low, the data at the rising edge of CDCLOCK (and both CDVALID and CDACCEPT high) is treated as a token.

Tokens are widely used in the present invention to control the flow of data and control signals through the system. In theory, it is possible to supply any token to the encoded data input.

Every token in accordance with the present invention consists of a respective serial byte (CD [7: 0]) associated with the extension bit (CDEXTN) of the token. The first byte of the token indicates the type of information carried by the token. The last byte of the token is indicated by the extension bit, which is low.

For example, encoded data is supplied using a DATA token. This is shown in FIG. As shown, the first byte is 0x04 (which indicates a DATA token). This information is followed by bytes of encoded data that are extended until CDEXTN is sampled low. The next data sampled may be interpreted as the first byte of the new token (assuming BMODE is still low).

Another token that is particularly useful is the FLUSH token. This token acts like a "reset" and is used after preparing the end of one video stream for the system for the next video stream.

[Data supplied via microprocessor interface]

In the present invention, the token may be supplied to the system via a microprocessor interface (MPI) by accessing the encoded data of the input register. Table 77 defines the encoded data of the input registers.

Table 77

[Record token in MPI]

The coded data registers can be grouped in two bytes in the memory map for efficient data transfer. The 8-bit data coded_data [7: 0] is in one location, and the control register, coded_busy, enable_mpi_input and coded_extn are in the second location (see Table 56).

When a token is configured to be entered via MPI, the current token is extended with the current value of coded_extn, where each time value is recorded in coded_data [7: 0]. The software may respond to set coded_extn to 0 before the last word of any token is written to coded_data [7: 0].

For example, a DATA token is started by writing 1 in coded_extn so that 0x04 is written to coded_data [7: 0]. At this point, the start of this new DATA token passes through the system for processing.

Every time a new 8-bit value is written to coded_data [7: 0], and the current token is expanded. Coded_extn needs to be accessed again only when the current token (eg, the introduction of another token) is terminated. The last word of the current token indicates that zero is written to code_extn as the word of the last token is written in coded_data [7: 0].

Furthermore, before each time data is written to coded_data [7: 0], coded_busy should check to see if the interface is ready to accept more data.

[Switching between input modes]

Appropriate precautions presented have been considered and should be implemented to dynamically change the data entry mode. In general, the transfer of tokens via any one path must complete switching before the switching mode. This switching mode is shown in Table 78.

Table 78

The first byte is fed to byte mode, which causes a DATA token header to generate on-chip. Any bytes transferred in addition to byte mode are appended with this DATA token until the input mode is changed. The MPI register bit coded_busy and the signal coded_accept indicate that the system accepts and interfaces data. This signal ensures that correct observation does not cause data loss.

[Ratio of encoded data accepted]

The input circuit of the present invention passes the token to the start encoding detector. The analysis data in the DATA token and its normal processing rate is 1 byte per clock (CDCLOCK). However, extra processing cycles are sometimes required. For example, the start code is encountered in the encoded data. When this happens, CDACCEPT goes low to indicate that data is not acceptable.

CDCLOCK must have a clock frequency higher than the rate at which bytes of data are supplied to the system. In many applications, it may be desirable to use the same clock (typically 27 MHz) for SYSCLOCK and CDCLOCK. One example is shown in FIG.

Similarly, Table 79 shows the interface timing of the encoded data of the present invention.

Table 79

a This timing need not be observed in any situation.

b Maximum load signal is 20PF.

The coded data interface uses the CMOS level.

CDCLOCK

The transmission of data that intersects with the encoded data interface is controlled by CDCLOCK, which synchronizes the main video decoder clock (SYSCLOCK). Such a facility would be useful to enable the system recorder to run the video clock to another clock.

However, CDCLOCK is used in the present invention for clock circuits such as start code detectors. CDCLOCK does not have the advantage of a phase closed loop (PLL) that guarantees good mark-space ratio, and an external circuit should be used to ensure timing parameters 2 and 3 shown in FIG.

In situations where CDCLOCK and SYSCLOCK do not need to be synchronized, there is an ease of driving an internal circuit such as an initiation detector from the PLL rather than CDCLOCK. This frees the external circuitry from the need to guarantee a good marked space ratio.

FIG. 106 shows the internal arrangement in which the even indication-space ratio generated by the PLL can be sent to the start code detector at the location of the CDCLOCK.

If un_named_register is 0 (reset condition), the start code detector is clocked from the PLL. In this case, both CDCLOCK and SYSCLOCK must be connected to the same signal.

AC timing is required for SYSCLOCK.

If un_named_register is 1, the start code detector uses CDCLOCK. In this case, CDCLOCK is synchronized with SYSCLOCK. The CDCLOCK should follow the timing defined in FIG.

[Preface]

The video output interface of the present invention consists of a digital output interface allowing CCIR recommissionation 6 to allow 656. All synchronization and blanking information is contained in the same byte-width stream of data, such as the form of special sign words (SAV and EAV), video information.

Moreover, separation of the synchronization and blanking pins is provided by the system being directly connected to a wide range of devices (video DAC or NTSC encoder). The timing of this signal is suitable for generation of a video signal that satisfies CCIR recommissionation 624.

Video data is time multiplexed onto a bus with wide signal bytes. Alternatively, if a 16-bit output mode is provided, the luminance data is output on a one byte wide bus while two different color signals are time multiplexed on a wide second byte bus.

[Video output signal]

Table 80 provides a signal for a video output interface according to the present invention.

TABLE 80

107 shows output timing in the 16-bit mode. 108 shows output timing in the 8-bit mode.

[Video output adjustment signal]

The video output adjustment signals associated with the present invention are shown in Table 81.

TABLE 81

a Color data (Cb and Cr) irrespective of the setting of this bit will be 0x80 (128 decimal) during the blanking period.

Edge scaling and cropping

The present invention attempts to generate an image for displaying 720 pixels with either 480 lines (525 lines raster) or 576 lines (625 lines raster). The present invention automatically enlarges the decoded picture to attempt to fill this area.

Since only a limited number of scale elements are supported, this is not always possible to precisely fill this area. If the final picture is too small, the edges will paint around the decoded picture. This edge will be like a decoded picture in the center of the screen.

Conversely, if the scaling produces an image that is too large, then the image is trimmed so that it can be displayed properly. The displayed area is the center of the decoded picture. This cropping is limited to approximately 10% or less of the cropped decoded picture. If this cropping is greater than this, a smaller scaling factor is used.

The edge color can be selected by writing the registers border_cb, border_y and border_cr. After the device is reset and after any picture is decoded, the entire screen will be filled with edge color. Furthermore, it is possible to paint edge colors across the entire screen by writing blank_screen. This may be used, for example, to hide video on channel change.

[Video Output Characteristics]

[Characteristic]

109 illustrates the timing of a video output interface in accordance with the present invention. Similarly, Table 82 shows video output interface timing.

Table 82

a Maximum load signal is 50PF.

b This timing parameter failure will cause a reset by inducing uncertainty in the precise clock cycle. VTGRESET 'is provided as an on-chip synchronizer that protects the quasi-safety problem in the event of no timing parameter observation.

Table 83 defines the video mode signal. 110 shows a video output mode signal.

TABLE 83

a If the NTSC / PAL or V1618 has changed after reset, the behavior is undefined.

[Video signal timing]

The video timing of the present invention is the result of the video output satisfying the next CCIR recommissionation.

CCIR Recommendation 601

CCIR Recommendation 656

CCIR Recommendation 624

[Horizontal Timing]

The horizontal timing is shown in FIG. The number is the SYSCLOCK cycle for the 525 line system (625 line system under the 625 line system insert).

During the equalization period, the HSYNC 'signal is low for 62 cycles (66 cycles in the 625-line system).

During the field synchronization period, the HSYNC 'signal is low for 732 cycles (738 cycles in the 625 line system).

[Vertical timing]

Vertical timing is shown in FIG. 12 for a 525-line (NTSC) system and in FIG. 113 for a 625-line (PAL) system. In these figures, the numbers are provided with CCIR Rec 656 channel lines down to the left. On the right two columns were provided so that the “F” and “V” bits were found in the SAV and EAV codes (see CCIR Rec. 601).

Smaller numbers at the center of thick, solid and black lines are provided as the logical lines of the decoded MPEG picture. Thus, numbers 0 to 479 for 480 lines are used in 525 lines (NTSC), and numbers 90 to 575 for 576 lines are used in 625 lines (PAL) systems.

FIG. 114 shows the timing of the sync and blanking pins for the 525 line system, and FIG. 115 shows for the 625 line system. Only one of HSYNC 'or CSYNC' can be output (hs_not_cs_) and the polarity of each of these signals can be reversed (see cblank_ah, etc.).

[VTG Reset Status]

In the present invention, the VTG is reset to start four lines for a 525 line (NTSC) system and one line for a 625 line (PAL) system.

[Preface]

Standard byte wide microprocessor interface (MPI) has been used in the present invention. The MPI operates to synchronize chip clocks of various decoders.

[HPI signal]

Table 84 describes the MPI interface signals.

TABLE 84

[Electrical Specifications of MPI]

[DC characteristics]

See “TTL (5V) Level”.

123 and 124 show the read and write timing of the MPI, respectively.

AC characteristics

Table 85 shows the read timing of the MPI.

TABLE 85

a Selection of ME '[0] in this embodiment initiates the cycle and selection of ME' [1] arbitrarily terminates the cycle.

b Access time is specified for the maximum load of 50PF in each MD [7: 0]. Larger loads increase access time.

Similarly, Table 86 shows the recording timing for MPI.

TABLE 86

a In this embodiment the selection of enable '[0] initiates the cycle and the selection of enable' [1] terminates the cycle arbitrarily.

[Interrupt]

“Imaginary” is a term used to describe an on-chip condition that you want to observe. An event may indicate an error condition or may indicate user software.

There are two single bit registers, each associated with an interrupt or "ideal". These are the condition mapping register and the condition mask register.

[Condition mapping register]

A 1-bit read / write register whose value is set to 1 by generating a condition in the mapping register circuit. The register is set to 1 bit even if the condition exists temporarily. The register is guaranteed to remain set to 1 until the user register is reset or the entire chip is reset.

The register is set to zero by writing the value 1.

Write zeros to keep the registers unchanged.

The register must be set to zero by the user software before the occurrence of this condition is observed.

The register will be reset to zero until reset.

[Condition mask register]

The condition mask register is a 1-bit read / write register that enables generation of interrupt requests if a matching condition mapping register is set. When a condition is already set when 1 is written to the condition mask register, an interrupt request occurs immediately.

A value of 1 turns on interrupts.

The register is cleared to zero until it is reset.

Needless to say otherwise, the block stops working after generating an interrupt request, and resumes immediately after the condition mapping or condition mask register is cleared.

[Thoughts and Mask Bits]

In the present invention, the mapping bits and mask bits are always grouped into matching bit positions in consecutive bytes in the register map (including Table 55). This makes it possible to interrupt the service software to use the value read from the mask register as the register for the value in the matching register that generated the interrupt.

[Chip Mapping and Masks]

The present invention has a single "global" mapping bit that summarizes the mapping behavior of the chip. Chip mapping registers present the OR of all on-chip mappings with 1s in their mask bits.

A1 in the chip mask bit enables the chip to generate an interrupt. A0 in the chip mask bit suggests some on-chip mapping that generates an interrupt request.

Writing 1 or 0 on a chip is ineffective. It is cleared only when all events (enabled with 1 in their mask bits) are cleared.

[IRQ ′ signal]

In the present invention, the IRQ 'signal appears when the chip mapping bit and the chip mask mapping mask are set. The IRQ ′ signal is active low, an “open collector” output that requires an off-chip pullup resistor. When active, the IRQ 'output is pulled down by an impedance of 100Ω or less. A pull-up resistor of approximately 4 kΩ can be applied most suitably.

[Page register]

The page register is applied to enable more than 64 addressed registers to reduce the number of address signals in the registers required by the present invention. This page register has a location of 0x1f. Register locations of 0x00 to 0x1f are not affected by the contents of the page register and always appear within the register map. The registers at locations 0x20 through 0x3f depend on the page registers.

Here, no paginated registers are required for normal operation of the device. Finally, the paginated registers are used for testing purposes.

In the present invention, the page register is set to zero value. The user cannot guarantee any other value not written to this register.

[Preface]

[SDRAM interface signal]

Table 87 shows the SDRAM interface signals.

TABLE 87

[SDRAM Configuration]

Table 88 shows the SDRAM configuration.

TABLE 88

[Zero configuration]

See Figure 116 for SDRAM connection with configuration.

FIG. 117 shows a configuration for one SDRAM connection. Similarly, Figures 118 and 119 show the configuration of two and three SDRAM connections, respectively.

[Introduction]

The system according to the invention is fully supported by the Joint Test Action Group (JTAG) “Standard Test Access Ports and Boundary Scan Structures” and has been adopted by 1EEE as standard 1149.1.

All JTAG operations are performed via the test access port (TAP), which consists of five pins. The TREST (test reset) pin resets the JTAG circuit to prevent the device from powering up in test mode. The TCK (test clock) pin is used for the clock sequential pattern on the TDI (test data input) pin and external to the TDO (test data output) pin. Moreover, the operating mode of the JTAG circuit is set clocked in the desired bit order in the TMS (test mode select) pin.

The JIAG standard can be extended to provide additional features in the chip manufacturer's description. According to the present invention, there are nine user introductions, including three JTAG delegations here. The remainder of the introduction enables testing of internal devices and provides the ease of additional external testing. For example, the output of all devices is made to float by a simple JTAG sequence. See Table 89.

[JTAG connection in NON_JTAG system]

Table 89

[Supported Commands]

This section describes the commands supported in the practice of the present invention. See Tables 90, 91 and 92.

Table 90

TABLE 91

The following optional JTAG commands are not supported.

1) IDCODE

2) RUNBIST

Table 92

[Command code assignment]

In total, 14 commands were defined.

Thus, there is a 4-bit long instruction register with two unallocated instructions. Unassigned commands are aliases for BYPASS commands according to IEEE 1149.1.

The full list of commands and their symbols are shown in Table 93.

TABLE 93

[Levels consistent with IEEE 11149.1]

[rule]

All rules are as set out below.

Table 94

[Recommended]

Table 95

TABLE 96

[permission]

TABLE 97

[Introduction]

The start code detector (SCD) according to the invention is responsible for detecting the start code in the encoded data stream. SCD converts start codes into tokens for internal processing of the system.

In addition, a series of functions, such as channel conversion, are supported.

[Initial Detector Detector Register]

Table 98 shows the start code detector register of the present invention.

TABLE 98

The a bit is not a simple R / W register bit.

b All interrupts are condition that chip_mask is set to 1.

[Start code detected]

The initiator detector of the present invention will detect only the initiator code, which is a correctly aligned byte.

The present invention deals only with video initiation. An unauthorized start code is detected and generates an unrecognized_start_code mapping. The unacceptable start codes are system start codes (0xb9 through 0xoff) in which start codes (0xb0, 0xb1 and 0xb6) and sequence_error_code (0xb4) are reversed.

[discard_all function]

The discard_all function is used to discard all data contained in the system. It is possible to select the discard_all function "manually" by setting the register discard_all to 1. However, scdp_access is first set to 1, and needs to be polled until it reads the next one. In general, this mode is typically inserted as part of the flag_picture_end function.

The present invention will continue to discard all data until a value of 0 is written to discard_all or a FLUSH token is encountered. The reset discard_all is a FLUSH token that is discarded from the stream of tokens and does not affect the parser or the circuit's contiguous block.

[flag_picture_end feature]

The flag_picture_end function according to the invention waits until it stops in the system of the last data flow of a picture to complete decoding. Thus, it can be seen that the parser does not complete the image.

120 is shown as a flowchart of the flag_picture_end function. As shown in the figure, it is possible to generate an interrupt (flag_picture_end_event) when the last picture is detected. This generates an SCD that stops processing data until an interrupt is provided. SCD may also be allowed to run.

If after_picture_discard is set to 1, all subsequent data may be discarded after the last picture is detected. This is most useful to discard data following one channel that is "rising" in the system multiplexer prior to channel change.

In this embodiment, the start_code_search function precedes the flag_picutre_end function. In this way, start_code_search is discarded because it has not been tested to determine if the last picture has arrived.

[start_code_search function]

In the present invention, the SCD may be set to search for a special type of start code. For example, it is used after changing the channel to search for the sequential start code before decoding the start.

TABLE 99

Search mode is initiated by writing a non-zero value to start_code_search. At this time, the start mode detector will search for a suitable start code as shown in Table 99. All data and tokens are discarded while the search continues. When one suitable start sign is encountered, start_code_search is set to zero and an interrupt is optionally generated to terminate the search.

It should also be noted that the search ends when it encounters the opening code indicated by the FLUSH token. However, the search does not end in the special case where the FLUSH token terminates the discard_all function. This further enables a direct transition between discard_all and a preselected search mode when a FLUSH token is encountered.

121 is shown as a flowchart of the start_code_search function according to the present invention.

[SCD Example-Channel Change]

An example of using the SCD function in the present invention is shown in the following sequence operation affecting the channel conversion operation.

1) It can be seen that the controlled microprocessor is required for channel conversion (response to the signal from the remote control device). The microprocessor uses the flag_picture_end function of the SCD by writing.

1 in flag_picture_end

1 to after_picutre_discard

Write 1 to flag_picture_end_mask.

2) When the start detector detects the end of the current picture, the detector is immediately started to discard subsequent data. The microprocessor is interrupted to determine whether the flag_picture_event interrupt has occurred. The microprocessor prepares the start detector for the new channel by writing.

Write 3 (search for sequence_start) to start_code_search

Record 1 in flag_picture_end_event (Clear thought)

3) The microprocessor then returns to the tuner to select a new channel.

4) After the last data from the previous channel has been transferred into the system (before the first data from the new channel), the FLUSH token is inserted (otherwise the value 0 is written to discard_all). Stop discarding (from the previous channel) and start searching for the sequential start code (from the new channel).

5) If a sequential start code is detected, the start code detector finishes discarding the data and re-executes normal decoding.

[Preface]

The video parser according to the present invention allows decoding of the video data flow. This is done with a micro programmed processor.

A simple path of thought leaves many simple devices to work with the decoded video itself without having to interact with the video parser.

However, the video parser can inform the controlling microprocessor when it detects an abnormal or unexpected, such as a bitstream error. In all cases, the micro code contains a sign that overcomes (and cancels) the error and is safe enough to ignore the bitstream error. However, generating a bitstream error is useful for diagnostic purposes.

Also, another feature of time stamp management is that it is handled by the parser's micro code processor. This is described in Chapter 10.

Parser Register

Registers used by the parser shown in Table 100.

TABLE 100

a mapping bit is not a simple R / W register bit.

b All interrupts are conditional on a chip-mask that is set to one.

[Error code]

Whenever the parser detects a mapping condition, it sets the parser-imaging. If the parser-mask is set to indicate that the IC user system is involved in servicing the parser mapping, the parser stops processing (assuming that the chip-mask is set to 1) and an interrupt is generated.

In response to the interrupt, the controlling microprocessor reads the parser-error-sign to determine the cause of the event. Table 101 provides a complete list of error codes defined in this regard.

The parser of the present invention takes over the processing after the controlling microprocessor has responded to the idea in some manner. This is done by clearing the mapping by writing the value 1 into the parser-ideology.

TABLE 101

[User Data Processing]

A small amount of user data is read from the parser. If wrong, all user data will be discarded by the start code detector. This is to protect the system from improper use of large amounts of user data beyond its capacity.

In order for user data to reach the parser, the register discarder-user must be set to zero. Each time user data meets in the bit stream, the data byte is buffered in the on-chip user data RAM. RAM has an interval for 192 bytes of data to be buffered. When all the bytes of user data have been read (or the RAM is full), the parser generates a mapping (ERR_USER_DATA) that causes the control microprocessor to read the data from RAM.

Before the user data RAM can be read, the microprocessor must first set the parser-access to 1 to gain access to the register inside the parser and poll until this bit is read back to 1. The number of bytes in the user data RAM is represented by the parser-state. User-data programs are not directly accessible. Instead, you need to record the address read by user_keyhole_addr (usually zero) and the data read from user_keyhole_data. user_keyhole_addr is automatically incremented every hour, and reading is performed from user_keyhole_data so that a predetermined number of user data can be read very quickly.

If it is smaller than 192 bytes of user data, all data is processed by one mapping. If it is larger than 192 bytes, the parser-status first contains 192 bytes, resulting in error-user-data. After the mapping is cleared (by writing zero to the parser-access and writing one to the parser-ideal), the microsignal relates the parser-continuation to determine what to do next.

If the parser-continuation is 1, the parser continues processing the user data. The process repeats if the remaining bytes (or next 192 bytes) of user data are parsed from the stream. However, if the parser-continuity is zero, the parser discards the residual user data and proceeds to normal video decoding. Note that the primary ERR_USER_DATA mapping will always occur even if the parser-continue is zero.

[Limit the amount of user data]

If it is desired to use user data, it is important to limit it so that the actual time of decoding the video data is guaranteed according to the invention. It is very difficult to specify acceptable limits of user data. This is because it depends on many external constraints, such as the interrupt response time of the control microprocessor and the time it takes to read a byte of data from the system. For reference, the amount of user data is limited to an amount that is guaranteed to be about 50 ms (including interrupt response time) readable by the system.

[Data user RAM]

During the decoding of the picture data, the user RAM is used by the micro decode processor for other purposes (eg, storing the concealed motion vector). Because of this, it is impossible to leave data out of RAM and will be reserved for use on the secondary side.

[Preface]

The present invention includes circuitry to assist in the management of video time stamps. External circuitry associated with the MPEG system strip parser returns a stable 27 MHz clock using a clock reference (programmed clock reference or appropriate system clock reference).

Thus, the circuit according to the present invention synchronizes the audio with respect to the starting video decoding at a predetermined time and then monitors the video time stamp for continuous synchronization. If there is no error, no continuous calibration is required.

It is desirable to avoid having to move the clock reference information to the video decoder. The hardware is divided into two areas: the circuit that loads the video time stamp with respect to the input stage of the system, and the real time-counter associated with the video parser circuit.

[Configuration system]

The present invention includes a counter that increments with a constant interval that results from a 27 MHz SYSCLOCK. The time stamp management system is conceptually dependent on a second copy of this counter maintained outside of the system. These two counters start with the same value by reset by the same signal. Then the two counters are free to recommend.

The present invention performs its time stamp management on its internal time counter, denoted as "video time". The video time stamp is changed by the system decoder to ensure proper comparison is made. It is not necessary to know the absolute time.

You only need to know the difference between the actual time the picture is to be decoded and the face time to be decoded.

Equation 1 below expresses this by setting the difference between the video time counter and the changed time stamp that is equal to the difference between the actual “time” (from the clock reference) and the time stamp, and Equation 2 is merely used to derive the changed time stamp. It is to recognize variables.

Equation 1:

Video Time-Changed Timestamp = Timestamp-Time

Equation 2:

Time stamp changed = video time + (time stamp-time)

Figure 122 shows one possible arithmetic scheme for leaking modified time stamps. Indeed, substantial additions (and shifts) will be performed on the processor rather than on the given hardware. Of course, you can derive the same number of modified time stamps in some other way. For example, rather than having a copy of video time, it is better to simply record the “time” value when the reset-time pin of the present invention was last demonstrated. From this information and the current "time" value, you can always derive the current content of video time within the system.

Any predetermined rearranged arithmetic operation may be used that yields a predetermined value of the modified time.

As shown in FIG. 122, the modified time stamp used in the present invention is only 16 bits. This is accomplished in two ways. First, the difference between time and time stamp (used to find the modified time stamp-see Equation 2) is always small and can discard more significant bits. The second is that the invention only controls the presence of video to the nearest frame-time, so it does not need any non-significant bits and shifts to the right with 4 bits to discard.

The 16-bit time information thus held can process errors up to about 11.5 seconds with an accuracy of about 180 ms (about 10% of field time) in timing.

Additional drawings, which are easily understood by those skilled in the art, include this apparatus to enable the user to know the detailed structure and operation of the surroundings in which the present invention operates.

The above-described pipeline system of the present invention includes an MPEG video decompression method and apparatus using a plurality of stages interconnected by a 2-wire interface installed as a pipeline processing apparatus, thereby providing a long time for various characteristics of the video decoding system. Satisfy the desire for another improvement of time. Control tokens and data tokens carry both token format controls and data over a single two-wire interface.

The token decode circuit is located at a given stage to recognize the given token as the control token corresponding to that stage and to pass the unrecognized control token along the pipeline. The reconstruction processing circuitry is located at the selected stage and reconstructs the stage in response to the recognized control token to process the confirmed data token. A wide variety of single support auxiliary system circuits and processing techniques include system implementation techniques including memory addressing, transforming data using conventional processing blocks, time synchronization, asynchronous, swing buffering, storage of video information, parallel Huffman decoders, and the like. It is out.

Although the present invention has been described in particular forms, various modifications are possible without departing from the spirit and scope of the invention. Accordingly, the invention is not particularly limited to the appended claims.

Claims (41)

A time synchronization device in a multiplexed data stream, comprising: a plurality of elementary data streams that contain a stream of multiplexed data, each containing a series of access units and having a series of time stamps associated therewith; Output demultiplexer; A reference clock for initializing the system time of the first circuit; A first time counter in communication with the reference clock to maintain a system time in the first circuit; A second time counter initialized by the reference clock in a second circuit synchronized with the first time counter, the second time counter retaining a local copy of the system time and the time stamp and a second time. Compare a counter to determine a presentation timing error between the local copy and the system time. An apparatus for synchronizing a video decoder with a system decoder, comprising: a system decoder; A time stamp for determining a display time; A reference clock for initializing system time in the system decoder; A first time counter for communicating with the reference clock to maintain system time of the system decoder; A second time counter initialized by the reference clock in the video decoder synchronized with the first time counter, wherein the second time counter maintains a local copy of system time while maintaining the time stamp and second time. And comparing a counter to determine a display timing error between the system time and a local copy of the system time. 20. An apparatus for synchronizing first and second circuits, the first circuit having a reference clock for initializing system time, said first circuit having a time counter to communicate with this reference clock and retain system time. Will; A first elementary stream time counter in said first circuit for granting elementary stream time; A first circuit configured to receive a time stamp and adapted to generate a synchronization time by adding an elementary stream time to the time stamp and subtracting a system time; Receiving a synchronization time from the first circuit and synchronizing with the elementary stream time counter to give a local copy of the elementary stream time and comparing the local time with the synchronization time to determine a timing error between the system time and the time stamp. And a second circuit, wherein the reference clock need not be passed directly to the second circuit to determine a timing error. 11. An apparatus for synchronizing first and second circuits, comprising: a reference clock for initializing system time of the first circuit; The first circuit communicating with the reference clock and having a time counter for maintaining system time; A first video time counter for providing video decoding time; A first circuit adapted to generate a synchronous time by receiving a video time stamp and adding a video decoding time to the video time stamp and subtracting a system time; A timing between the system time and the video time stamp by suitable for receiving a synchronization time from the first circuit and synchronizing with the first video time counter to give a local copy of the video decoding time and comparing the local copy with the synchronization time. And a second circuit having a second video time counter for determining an error, wherein said reference clock need not be passed directly to said second circuit to determine timing error. Device for CLAIMS 1. A method for setting timing information, the method comprising: preparing a video data stream having a time stamp transmitted through a packet header; The time stamp designates the first picture in the packet data; Setting a register having a flag indicating valid time stamp information; The flag is information obtained from the packet header and written to this register; Removing the time stamp from the video data stream and writing it to the register; And checking a flag to check a state of the register to determine whether valid time stamp information is included in the register at an image start state. CLAIMS 1. A method for picture decoding, comprising: determining a display time error for a setting value; Separating the video data into tokens for subsequent processing; Confirming whether a time stamp token is indicated; Comparing the time stamp token with video time; Indicating occurrence of a timing error by generating a comparison value; When a timing error occurs, determining whether the comparison value is in an acceptable range compared to the set value; And displaying the comparison value when it is outside the allowable range. 11. An apparatus for using a system decoder and a video decoder, comprising: a system decoder suitable for receiving an MPEG system stream and demultiplexing video data and video time stamps from the stream; The system decoder has a first time counter representative of the system time; A video decoder for receiving the video data and the video time stamp; The video system has a second time counter synchronized with the first time counter; The video decoder also includes a video decoder buffer for receiving the video data at a fairly constant rate and outputting it at a fluid rate to pass the video time stamp. Device for. CLAIMS 1. A method for determining timing error between a first circuit and a second circuit, the method comprising: setting a system time (SY), a time stamp (TS), and an elementary stream time (ET) in a first circuit; Obtaining a synchronizing time (X) using a basic trim time (ET), a time stamp (TS), a system time (SY) and the expression X = ET + TS-SY; Providing a synchronizing time (X) to a second circuit; Generating a synchronized elementary stream time (ET2); Obtaining a timing error using the synchronizing time (X) and the equation ET2-X, wherein the first circuit can be synchronized with the second circuit without transferring system time to the second circuit. A timing error determination method between one circuit and a second circuit. CLAIMS 1. A method for determining timing error between a first circuit and a second circuit, the method comprising: setting a time stamp (TS) and an initial time (IT) in a first circuit; Obtaining a synchronization time (X) using a time stamp (TS), an initial time (IT), and an expression X = TS-IT; Transferring a synchronizing time (X) to a second circuit; Generating a synchronized elementary stream time (ET); Obtaining a timing error using the synchronizing time (X) and the equation ET-X, wherein the first circuit and the second circuit can be synchronized with the second circuit without passing time. How to determine timing error between circuits. CLAIMS 1. A method for determining timing error between a first circuit and a second circuit, the method comprising: giving a system time (SY), a video time stamp (VTS), and a video decoding time (VT) to the first circuit; Obtaining a synchronizing time (X) using the video decoding time (VT), the video time stamp (VTS), the system time (SY) and the expression X = VT + VTS-SY; Transferring a synchronizing time (X) to a second circuit; Generating a video decoding time VT2 of a second circuit synchronized with the decoding time VT of the first circuit; Calculating a timing error using the synchronizing time (X) and equation (VT2-X), wherein the first circuit can be synchronized without transferring system time to the second circuit. How to determine timing error between two circuits. CLAIMS 1. A memory addressing method, comprising: preparing a fixed width word having a predetermined number of bits to be used for addressing variable width data; Defining the word of fixed width into a field of tyranny and an address field; Having at least one bit in the field of tyranny as an end marker; Defining the address field with a plurality of bits that address data; Changing the number of bits of the address field in inverse proportion to the size of the variable width data; And changing the number of bits of the ganged field in direct connection with the size of the variable-width data, and maintaining a fixed-width word even when the size of the ganged and address fields changes in addressing the variable-width data. A memory addressing method, characterized in that. CLAIMS 1. A memory addressing method, comprising: having a fixed width word having a predetermined number of bits to be used as addressing data; Defining the fixed-width word as an address field and a replacement field; Defining the address field with a plurality of bits defining an address of the data; Defining a variable width replacement field as at least one replacement bit; The replacement field has at least one bit for writing as an end marker between the address field and the replacement field; Using a replacement field to indicate replacement bits from a separate addressing source, and maintaining a fixed width word in addressing variable width data even if the address field width and the replacement field width change in inverse proportion. Memory addressing method. CLAIMS What is claimed is: 1. A method for addressing variable width data in a memory, comprising: having a memory having words of a predetermined width and consisting of partial words; Rotating the partial word to be accessed at the least significant bit end; Extending the remainder of the word so that the accessed word is recognized as a partial word; Restoring the remainder of the word; And rotating the word such that the partial word returns to its original position. A parallel Huffman decoder comprising: a selector; A pair of input registers for receiving Huffman code data, the two registers providing inputs in parallel to the selector; And a Huffman code ROM receiving an input from a ROM table selection input separate from the selector, wherein the Huffman decoder obtains a decoded output from the ROM. A RAM interface for connecting a bus to RAM, comprising: means for receiving a plurality of datawords from a bus and buffering the received datawords; Means for receiving an address associated with the plurality of datawords from the bus; Means for generating a contiguous address of a RAM into which the stored dataword is to be written; The consecutive address is extracted from the receiving address; Means for writing said data word to said address of the generated RAM. A RAM interface for connecting a bus to a RAM, comprising: a plurality of datawords stored in a RAM having a preset address; Means for receiving a RAM address associated with the plurality of data words from a bus; Means for generating a RAM address column for addressing the plurality of data words stored in the RAM; The address string is extracted from the receiving address; Means for buffering datawords read from the RAM; And a means for reading said plurality of data words from said RAM, wherein said data words are written to said buffer means using a RAM address generated by said address generating means. CLAIMS 1. A method for controlling buffering of coded video data composed of frames, comprising: determining a picture number of a frame; Determining a preferred representation number of the frame; And displaying a buffer in a ready state when the image number is equal to or later than a preferred representation number. An apparatus for data conversion, comprising: a first latch defining a first data stream source and a second latch defining a second data stream; The first and second latches communicate with the arithmetic processing unit; The arithmetic processing unit communicates data with the transposer; A transposer for transposing or communicating said data with said second latch; The second latch is configured to receive data; The second and first latches communicate the arithmetic processing unit with the first and second data streams in an interleaved manner so that the second latch does not interrupt communication from the first latch in the interleaved communication. As defined; Wherein a normal arithmetic processing unit is used for the first and second data streams. A method for converting data using a conventional arithmetic processing unit, comprising: loading the data into a first latch, transferring the data to the arithmetic processing unit at a predetermined number of cycles, and transferring a first marker bit to a control shift register; Dropping; Loading data into a second latch, the second latch being suitable for receiving data; Transferring data of the second latch to the arithmetic processing unit when the first control shift register reaches a set state and the second latch reaches a preset amount of data; Invalidating the data transfer from the second latch if the second latch is not filled by the data already set; Restoring the second latch when the first latch receives non-data. A swing buffer device, comprising: at least two memory arrays; One write control circuit for communicating with the memory array and controlling data input to the memory array; A read control circuit for communicating with the memory array and controlling data output from the memory array; And the write and read control circuits communicate with each other for synchronized control of the memory array. A swing buffer device, comprising: a memory array; A write control circuit in communication with the memory array via a bit line; A read control circuit in communication with the memory array through the bit line; And a write low decoder and a read low decoder arranged to access the memory array through a pair of rows so that individual cells are read. A method of accessing a memory cell asynchronously, comprising: using a decoder to decode at least a pair of cells; Reading one of the cells and recording the other of the cells. A method for storing video information, the method comprising: dividing video information into I frames, P frames, B ₁ frames, and B ₂ frames; Store the I frame in a first frame store, and store the P frame in a second frame store; Providing a third frame store having first and second field stores; The first and second field stores are each divided into at least two memory areas; Store a B ₁ frame in the first or second field store from a selected portion of the memory area; And recording a portion of the B ₂ frame in the selected memory region portion from which the B1 frame is read, and reducing the amount of memory used for storing the video information. A memory for handling Don't care, comprising: a group of address lines, inverted address lines, and data lines, wherein the address lines and inverted address lines store information addressed in the form of datawords. And connected to a decoding format for access, wherein the Don Carr address position on the data line is separated from the associated address line and the inverted address line. With regard to a DRAM access method for storing and reproducing data words associated with a two-dimensional image, the DRAM includes two separate banks, each of which is capable of page mode operation for writing and reading data words. The two-dimensional image consists of a two-dimensional grid pattern of cells, each cell containing an M * N pixel matrix, and the word occupies one page or less of a bank in association with each cell. A method of access, comprising: (a) assigning each cell a particular one of two banks, such that all datawords associated with that particular cell are read and written from a given page of that particular bank, Assigning a bank assigns the banks to be associated differently than for any cell that borders each cell appearing in the same row as well as in the same column. Wow; (b) DRAM access comprising a matrix of pixels and reading the datawords associated with cells not aligned to the two-dimensional grid pattern but aligned as pixels in the cells of the two-dimensional grid pattern. Way. With regard to a DRAM access method for storing and reproducing data words associated with a two-dimensional image, the DRAM includes two separate banks, each of which is capable of page mode operation for writing and reading data words. And a method in which each cell includes the two-dimensional grid pattern of a cell, an M * N pixel matrix, and the word occupies one page or less of a bank in association with each cell. Assigning each cell a particular one of the two banks such that all datawords associated with that particular cell are read and written from a given page of that particular bank, and the assignment of the bank to that cell Assigning banks to be associated differently than in the case of any bordering cell appearing in the same column as well as in the same column; and (b) reading said dataword associated with a cell consisting of an M * N pixel matrix, said cells being aligned as pixels in the cells of said two-dimensional grid pattern but not aligned to said two-dimensional grid pattern. DRAM access method. With respect to a method of accessing M words less than a predetermined burst length N of RAM from RAM, for having an enable line for selectively enabling / disabling writing and reading to the RAM. CLAIMS 1. An access method, comprising: requesting N words to be written or read from the RAM; Determining whether M words from the RAM have been written or read; M is a value less than N; Disabling the RAM according to whether M words have been written or read. With respect to a method of accessing M words less than a predetermined burst length N of RAM from RAM, for having an enable line for selectively enabling / disabling writing and reading to the RAM. An access method comprising: requesting N words to be read from the RAM; Determining whether M words have been read from the RAM; M is a value less than N; Disabling said RAM in accordance with a determination of whether or not M words have been read from the RAM. With respect to a method of accessing M words less than a predetermined burst length N of RAM from RAM, for having an enable line for selectively enabling / disabling writing and reading to the RAM. CLAIMS 1. An access method, comprising: requesting N words to be written to the RAM; Determining whether M words have been written to the RAM; M is a value less than N; Disabling said RAM in accordance with a determination of whether M words have been written to RAM. A system for converting an arrayed digital signal of N data input words, comprising: performing a predetermined pairing operation on an odd number of input words and pre-common on an even number of input words. Pre-common processing circuitry (PREC) arranged to transmit to the outputs; A common processing circuit (CBLK) for receiving even-numbered data and odd-numbered data from the pre-common processing circuit (PREC) to form an odd common processing output value and an even common processing output value, respectively; And perform predetermined output scaling operations on the odd common processing output values to form post-process odd values and arithmetically combine the post-process odd values with the even common processing output values to generate high and low order output words. A post-common processing circuit (POSTC) arranged to cause the system to be arranged such that the output words include conversion values corresponding to the input data word, wherein the post-common processing circuit is: A first latch defining a first data stream source and a second latch defining a second data stream; The first and second latches communicate with an arithmetic processing unit; The arithmetic unit communicates data with a transposer; The transposer transposes and communicates the data with the second latch; The second latch is arranged to receive data; The second and first latches communicate the arithmetic unit with the first and second data streams in an interleaved manner so that the second latch does not interrupt communication from the first latch in the interleaved communication. Defined; And a common arithmetic unit is used for said first and second data streams. 31. The method of claim 30, wherein the second latch comprises a series of interconnected latches for forming a buffer, wherein the buffer can be sized to varying rates of receipt and transmission of data. Digital signal conversion system. 32. The digital signal conversion system according to claim 31, wherein said second latch communicates said arithmetic unit and said second data stream only when it is filled with a predetermined amount of data. A system for converting a digital signal from a frequency into a time domain in which the digital signal is arranged in groups of N data input words: a predetermined pairing operation for an odd number of the input words. A pre-common processing circuit (PREC) arranged to implement a P and transmit an even number of said input words to pre-common outputs; A common processing circuit (CBLK) for receiving even-numbered data and odd-numbered data from the pre-common processing circuit (PREC) to form an odd common processing output value and an even common processing output value, respectively; And perform predetermined output scaling operations on the odd common processed output values to form post-processed odd values and arithmetically combine the post-processed odd values with the even common processed output values to obtain higher and lower output words. And a post-common processing circuit (POSTC) arranged to generate the data, wherein the system is arranged such that the output words include conversion values corresponding to the input data word, and wherein the system outputs the input data to the input data. Arranged to include inverse discrete cosine transform values corresponding to a word, wherein the post-common processing circuitry comprises: a first latch defining a first data stream source and a second latch defining a second data stream source; The first and second latches communicate with an arithmetic unit; The arithmetic unit communicates data with the transposer; The transposer transposes and communicates the data with the second latch; The second latch is arranged to receive data; The second and first latches communicate the arithmetic unit with the first and second data streams in an interleaved manner so that the second latch does not interrupt communication from the first latch in the interleaved communication. Defined; And a common arithmetic unit is used for said first and second data streams. 34. The method of claim 33, wherein the second latch comprises a series of interconnected latches for forming a buffer, wherein the buffer can be sized to varying rates of receipt and transmission of data. Digital signal conversion system. 35. The digital signal conversion system according to claim 34, wherein said second latch communicates said arithmetic unit and said second data stream only if said second latch is filled with a predetermined amount of data. A time synchronization device in a multiplexed data stream, comprising: a token source for generating a time-multiplexed stream of tokens, each of the tokens comprising a plurality of data words, each of which is added in the token; A token source containing an extension bit to indicate the presence of significant words; A demultiplexer for accepting the multiplexed data streams and outputting a plurality of elementary data streams each comprising a series of access units and having a series of time stamps associated therewith; A first circuit connected to the demultiplexer including a first counter; A second circuit connected to the demultiplexer including a second counter, and a third circuit connected to the first counter and the second counter to initialize system time and responsive to a SYNC_TIME token generated in the token source. And the first counter counts independently of the second counter to maintain first and second local versions of the system time in the first circuit and the second circuit. 37. The apparatus of claim 36, further comprising a fourth circuit for calibrating the time stamps according to the processing time of the token in the second circuit. 37. The apparatus of claim 36, further comprising a fifth circuit for receiving the time stamps and generating a signal connected to the first counter and a second counter to indicate whether an access unit is output in a timely manner from the second circuit. Time synchronization device, characterized in that. 1. A time synchronization apparatus in a multiplexed data stream, comprising: a demultiplexer for receiving a stream of multiplexed data and outputting a plurality of elementary data streams each comprising a series of access units and having a series of time stamps associated therewith; A reference clock for initializing the system time of the first circuit; A first time counter for communicating with the reference clock to maintain a system time in a first circuit; An elementary stream time counter coupled to the demultiplexer; Circuitry for generating a synchronization time X in response to the time stamp, the elementary stream time counter and the first time counter; A second time counter in a second circuit in synchronization with the elementary stream time counter to maintain a local copy of the elementary stream time and determine a presentation timing error between the local copy of the elementary stream time and the synchronization time X Time synchronization device comprising a. 40. The apparatus of claim 39 wherein the elementary stream time counter generates a signal indicative of a carry out and the second time counter is reset in response to the signal. 40. The early / late-indicator circuit of claim 39, wherein in response to the synchronization time X and the second time counter, an early / late-indicator circuit for generating a signal indicating whether an access unit is output in a timely manner from the second circuit. and an indicator circuit.