KR100270057B1 - Rom circuit - Google Patents

Abstract

An object of the present invention is to provide a ROM circuit which can read data at high speed while reducing current consumption, and to provide a ROM circuit which can reduce the number of address pins.

The present invention for achieving the above object is selected by the address data so that a plurality of pieces of data having a fixed length are stored and one data corresponding to the address data in the data is read when the address data is input. In a ROM circuit for outputting component data of the data stored in a plurality of memory cells, component data constituting each of the data is stored in a memory cell arranged in a single row, and the address data A ROM circuit characterized by dividing into upper address data and lower address data, specifying a single row by upper address data, and continuously specifying component data in a single row by lower address data. That's the point.

Description

ROM circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM circuit for storing data having a certain bit length, such as character data or kanji font data. In particular, the stored data is read at low power consumption and at high speed. The present invention relates to a ROM circuit that can be produced.

In general, a ROM circuit has a plurality of memory cells arranged two-dimensionally, and data stored in the specific memory cell by designating the specific memory cell with address information. Is read. Since the memory cells are arranged two-dimensionally, the address information is divided into two address data groups, and one memory address is specified by these two address data groups.

1 is a block diagram of a conventional ROM circuit. In the ROM circuit 201 shown in FIG. 1, a memory address to be output is designated by two address data groups.

The ROM circuit 201 includes address buffer circuits 202 and 205, an X decoder circuit 203, a memory cell array circuit 204, and a Y decoder circuit. 206, Y gate circuit 207, output control circuit 208, and output buffer circuit 209. In FIG. In the ROM circuit 201, address data A0 to A16 are input as address information.

The address data A3 to A16 of the address data A0 to A16 are input to the address buffer circuit 202. The address buffer circuit 202 outputs the inputted address data group as the address data X to the X decoder circuit 203. The address data A0 to A2, A10 and A11 are input to the address buffer circuit 205. The address buffer circuit 205 outputs the inputted address data group as the address data Y to the Y decoder circuit 206.

The X decoder circuit 203 decodes the address data X input from the address buffer circuit 202 to generate row selection data, and outputs it to the memory cell array circuit 204. The memory cell array circuit 204 has a plurality of memory cells arranged in a matrix, and stores the data stored in the memory cells corresponding to the row selection data input from the X decoder circuit 203 to the Y gate circuit ( 207). The Y decoder circuit 206 decodes the address data Y input from the address buffer circuit 205 to generate column selection data, and outputs it to the Y gate circuit 207. The Y gate circuit 207 passes the data corresponding to the column selection data output from the Y decoder circuit 206 among the data output from the memory cell array circuit 204 and supplies it to the output buffer circuit 209. The output control circuit 208 generates an output timing signal based on the signals CEB, OE, OEB, and the like input from the outside, and outputs it to the output buffer circuit 209. The output buffer circuit 209 outputs data output from the Y gate circuit 207 as output data 00 to 07 when output permission is issued from the output control circuit 208.

That is, when the address data A0 to A16 are input, the ROM circuit 201 decodes the address data to generate address data X and Y, and extracts data from the memory cells at the memory addresses corresponding to these address data X and Y. It reads and outputs them externally as output data 00-07.

For example, when the ROM circuit 201 is used as a Chinese character ROM for storing Chinese character data, as shown in FIG. 2, a plurality of word data (here, 8 bits of data is regarded as one word data). ) Is combined to form one Chinese character font data.

That is, as shown in Fig. 2, for example, the Chinese character "light" is composed of 256 dots of 16 left and right and 16 up and down, and one word data is continuous in the horizontal direction (row direction). It corresponds to eight dots. Therefore, in order to read Chinese character font data corresponding to one Chinese character, word data stored in the memory array circuit 204 is read 32 times (for 32 words) in the order of access as shown in FIG. You must.

In the Chinese character ROM circuit 201 shown in FIG. 1, the word data for 32 consecutive words is set in a predetermined matrix format, for example, eight in the horizontal direction and four in the longitudinal direction as shown in FIG. It is stored in the memory cell array circuit 204 in the form of a matrix. Therefore, when reading the font data in the access order, the word data stored in the memory cell of # 7 expressed in hexadecimal (HEX) is read, and then the word data stored in the memory cell of # 8 is read. When exiting, the memory address of the memory cell must be shifted by reading not only in the horizontal direction but also in the longitudinal direction.

In addition, when reading word data stored in the memory cell of #F and then reading word data stored in the memory cell of # 10, the memory address of the memory cell is similarly read not only in the horizontal direction but also in the longitudinal direction. You must make a transition.

In addition, when reading word data stored in the memory cell of # 17 and then reading the word data stored in the memory cell of # 18, the memory address of the memory cell is shifted by reading not only in the horizontal direction but also in the longitudinal direction. You must do it. In FIG. 4, "←" indicates that the content is the same as the content described in the left column.

As described above, when reading the word data constituting one Kanji font data, the entire circuit must be activated 31 times in the horizontal direction and 3 times in the longitudinal direction. Therefore, since the current is consumed to activate the circuit, there is a problem that the current consumption increases in proportion to the number of activations. In addition, there is a problem that the access time is increased because of the time required for activation.

In addition, there is a problem that the address pins of the device constituting the ROM circuit are required as many as the required address data.

Japanese Patent Laid-Open Nos. 63-53639 and 1-5397 disclose ROM circuits that can be used as Chinese character ROM. However, when the ROM circuit disclosed in these publications reads out each word data constituting one Chinese character font data, 31 times in the transverse direction and three times in the longitudinal direction do not activate the entire circuit as in the conventional ROM circuit. Since it does not, it also has the above-mentioned problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved ROM circuit which solves the above-mentioned problems, and more specifically, to provide a ROM circuit capable of reading data at high speed while reducing current consumption. It is to provide a ROM circuit that can reduce the number of.

1 is a block diagram showing an example of a conventional ROM circuit.

FIG. 2 is a schematic diagram showing an example of a Chinese character font shown in FIG. 1 and stored in a ROM circuit.

FIG. 3 is a schematic diagram showing a reading procedure of word data constituting the Chinese character font shown in FIG.

4 is a schematic diagram showing a reading operation for reading word data of a Chinese character font from a memory cell array circuit.

5 is a block diagram showing a Chinese character ROM circuit according to the first embodiment of the present invention.

FIG. 6 is a schematic diagram showing an arrangement example of the Chinese character font data stored in the memory cell array circuit shown in FIG.

FIG. 7 is a schematic diagram showing address data input to the Chinese character ROM circuit shown in FIG.

FIG. 8 is a circuit diagram of the address buffer circuit shown in FIG.

9 is a timing chart of signals input to the address buffer circuit shown in FIG.

10 is a circuit diagram of an address buffer circuit used in Embodiment 2 of the present invention.

11 is a circuit diagram of an address buffer circuit used in Embodiment 2 of the present invention.

FIG. 12 is a timing diagram showing an example of signals for explaining the improvement of the Chinese character ROM circuit shown in FIG.

FIG. 13 is a circuit diagram showing an example of signals for explaining the improvement of the Chinese character ROM circuit shown in FIG.

14 is a circuit diagram of a memory cell array circuit used in Embodiment 4 of the present invention.

FIG. 15 is a circuit diagram showing a memory cell of the memory cell array circuit used in Embodiment 5 of the present invention.

16 is a circuit diagram of a ROM circuit according to Embodiment 6 of the present invention.

17 is a circuit diagram of a ROM circuit according to Embodiment 7 of the present invention.

FIG. 18 is a block diagram showing a circuit configuration example in which the ROM circuit shown in FIG. 17 is applied to a conventional system.

According to the present invention, a plurality of memory cells are selected by the address data such that a plurality of pieces of data having a fixed length are stored and one data corresponding to the address data among the data is read when address data is input. In a ROM circuit for outputting component data of the data stored therein, component data constituting each of the data is stored in a memory cell arranged in a single row, and the address data is associated with upper address data. A ROM circuit is characterized by dividing into lower address data, specifying a single row by upper address data, and continuously specifying component data in a single row by lower address data.

Hereinafter, the present invention will be described in detail.

According to the present invention described above, since all the component data contained in one data is stored in a memory cell arranged in a single row, when reading one data, the component is divided across a plurality of rows. There is no need to read it. Therefore, the number of times of activating the memory cell array circuit is reduced, and the current consumption by that much is reduced. In addition, the time required for activation is also shortened.

In one embodiment of the present invention, when the chip activation signal transitions to the inactive state, the upper address data is held and the same fixed length data is continuously designated by the upper address data. As a result, even when the chip activation signal transitions to the inactive state, it is possible to hold the row of the component data included in one fixed length data while activating it continuously. Therefore, it is possible to suppress an increase in current consumption due to repetition of activation.

In another embodiment, the word line wiring resistance of the memory cell selected when the lower address data is a predetermined value is set to be smaller than the word line wiring resistance of the other memory cells. As a result, for example, the wiring resistance of the memory cell storing the component data read first from the component data can be reduced, the activation of the memory cell can be made faster, and the operating speed of the entire ROM circuit can be made faster. .

In another embodiment of the present invention, the channel width of the memory cell selected when the lower address data is a predetermined value is set to be larger than the channel width of other memory cells. As a result, for example, the channel width of the memory cell storing the component data first read out of the component data can be increased, the activation of the memory cell can be made faster, and the operating speed of the entire ROM circuit can be made faster.

Further, according to another embodiment of the present invention, when the memory cell array is other than the first memory cell array selected when the lower address data is preset, and the lower address data is other than the predetermined value preset, The characteristics of each of the first and second memory cell arrays are set so that they are divided into the selected second memory cell array and the reading speed of the first memory cell array is faster than the reading speed of the second memory cell array. This makes it possible to speed up the operation speed of the entire ROM circuit, for example, by using the memory cell array including the memory cells storing the first element data read out of the component data as the first memory cell array.

Further, according to another embodiment of the present invention, a clock signal is input together with the upper address data, one of the data is designated by the upper address data, and the upper level is based on a count value obtained by counting the clock signal. The component data constituting the data designated by the address data is continuously specified. As a result, the address line for transmitting the lower address data can be replaced with only the clock signal line for transmitting the clock signal. Therefore, the pins for the lower address data are not necessary, so that the number of pins of the entire device forming the ROM circuit is reduced, and the package area of the device is also reduced.

Hereinafter, the present invention will be described in more detail with reference to Examples.

Example 1

5 is a block diagram showing a Chinese character ROM circuit to which Embodiment 1 of the present invention is applied.

The Chinese character ROM circuit 1 shown in FIG. 5 includes the address buffer circuits 2 and 5, the X decoder circuit 3, the memory cell array circuit 4, the Y decoder circuit 6, and the Y. The gate circuit 7, the output control circuit 8, and the output buffer circuit 9 are comprised. The address data A0 to A16 are input to the ROM circuit 1 as address information. The address data A5 to A16 of the address data A0 to A16 are input to the address buffer circuit 2. The address buffer circuit 2 outputs the inputted address data group as the address data X to the X decoder circuit 3. The address data A0 to A4 are input to the address buffer circuit 5. The address buffer circuit 5 inputs the input address data group as the address data Y to the Y decoder circuit 6.

The X decoder circuit 3 decodes the address data X input from the address buffer circuit 2 to generate row selection data, and outputs it to the memory cell array circuit 4. The memory cell array circuit 4 has a plurality of memory cells 20 (refer to FIG. 13) arranged in a matrix, and has a memory cell 20 corresponding to the row selection data input from the X decoder circuit 3. The stored font data is read in word units and output to the Y gate circuit 7. The Y decoder circuit 6 decodes the address data Y input from the address buffer circuit 5 to generate column selection data, and outputs it to the Y gate circuit 7. The Y gate circuit 7 passes the data corresponding to the column selection data output from the Y decoder circuit 6 among the data output from the memory cell array circuit 4 and supplies it to the output buffer circuit 9. The output control circuit 8 generates an output timing signal based on the signals CEB, OE, OEB, and the like input from the outside, and outputs it to the output buffer circuit 9.

When the output buffer circuit 9 is allowed to output from the output control circuit 8, the output buffer circuit 9 receives data output from the Y gate circuit 7 and outputs it as output data 00 to 07.

In the above-described Chinese character ROM circuit 1, when storing word data for 32 words constituting a Chinese character font corresponding to a single Chinese character code in the memory cell array circuit 4, a matrix format that is set in advance, for example For example, as shown in FIG. 6, the word data for these 32 words is stored in the memory cell array circuit 4 in a matrix format such that there are 32 (FF (HEX)) in the lateral direction. In Fig. 6, the same contents as those written in the left column are indicated by "←".

When an instruction to read by the signals CEB, OE, and OEB is input to the Chinese character ROM circuit 1, and address data A5 to A16 indicating the Chinese character code are input as shown in FIG. A5 to A16 are decoded to generate address data X. As shown in Fig. 7 (a), whenever the number (address data A0 to A4) of each word data constituting the Chinese character font is input, the address data A0 to A4 are decoded to generate address data Y. .

The font data is read in word units from the memory cells 20 at the memory addresses corresponding to these address data X and Y, and the read word data is output to the outside as output data 00 to 07.

When reading the word data, read the word data from the memory cell corresponding to the memory order of # 0 until reading the word data from the memory cell 20 corresponding to the memory address of # 1F. By simply shifting the position 31 times in the lateral direction without shifting the position in the longitudinal direction, all word data of the Chinese character font data corresponding to a single Chinese character code can be read.

As described above, in the first embodiment according to the present invention, word data for 32 words constituting a single Chinese character font data is stored in the memory cell array circuit 4 so as to be horizontally aligned. When reading Chinese character font data, the word data number is designated as the address data A0 to A4 to read the font data in word units, and the address data A5 to A16 are fixed to increment only the address data A0 to A4. (increment), word data stored in the memory cell array circuit 4 is read out. Therefore, the number of times of activating the Chinese character ROM circuit 1 is smaller than the number of times of activation of the conventional ROM circuit, whereby the current consumed by the Chinese character ROM circuit 1 is reduced.

In addition, as the number of activations decreases, the reading speed becomes faster, so that the Chinese character display speed of the device using the Chinese character ROM circuit 1 can be increased.

Example 2

In the first embodiment, the address buffer circuit 5 on the lower address data side is divided into an inverter circuit 10, a NAND gate circuit 11, and an inverter circuit 12, as shown in FIG. It is composed. The inverter circuit 10 receives the signal CEB (chip activation signal), inverts it, and outputs the signal ICE. The NAND gate circuit 11 takes the logic of the signal ICE output from the inverter circuit 10 and the address data A0 to A4 and outputs it as address data A0B to A4B. The inverter circuit 12 receives the address data A0B to A4B and inverts them.

In the case of the above-described address buffer configuration, when address numbers # 0, # 1, # 2, ... are designated by the address data A0 to A4, Fig. 9 (a) is shown in FIG. As shown, each time the signal CEB returns from "0" to "1", all of the address data A0B to A4B output from the NAND gate circuit 11 becomes "1". Therefore, the memory address is designated in the order of # 0 → # 0, # 1 → # 0, # 2 → # 0, # 3 → # 0 ....

Therefore, even when the signal CEB changes from "0" to "1" during the change of the address data A0 to A4 in this way, when it is not necessary to change the address data A0B to A4B output from the address buffer circuit 5, the address The buffer 5 may be configured as shown in FIG. The address buffer circuit shown in FIG. 10 is composed of a latch circuit 13 and an inverter 14. The latch circuit 13 receives and latches the address data A0 to A4 when the signal ICE is changed from "0" to "1". The inverter circuit 14 receives and inverts the address data A0 to A4 output from the latch circuit 13.

With the address buffer circuit 5 as shown in FIG. 10, the address data A0 to A4 are latched by the latch circuit 13 only when the signal ICE changes from "0" to "1". . Even if the signal ICE changes from "1" to "0" before the address data A0 to A4 are replaced, the address data A0 to A4 output from the latch circuit 13 does not change. As a result, word data can be output from only the memory address designated by the address data A0 to A4 input to the latch circuit 13.

In addition, the address buffer circuit 2 that processes the upper address can also be configured as shown in FIG. That is, since the latch circuit 13 latches the address data A5 to A16, the subsequent address output from the Y decoder circuit 6 without flowing unnecessary current to the circuit even if the signal CEB changes to "1". By simply changing the data Y, the word data constituting the Chinese character font data can be read.

Example 3

In Example 2 mentioned above, each buffer address circuit 2 and 5 is comprised by the circuit shown in FIG. With this circuit configuration, address data A0 to A4 (A5 to Al6) and address data A0B to A4B (A5B to A16B) are output even when the signal CEB is "1".

Therefore, when the signal CEB is "1", in order to deactivate each address buffer circuit, each address buffer 2 (5) is set as the structure shown in FIG. The address buffer circuit shown in FIG. 11 includes a delay circuit 15, a NAND gate circuit 16, a latch circuit 17, and an inverter circuit 18. The delay circuit 15 delays the signal ICE and supplies it to the NAND gate circuit 16. The HAND gate circuit 16 takes the logic of the delayed signal ICE supplied from the delay circuit and the address data A0 to A4 (A5 to A16). The latch circuit 17 receives and latches the address data A0 to A4 (A5 to A16) when the signal ICE is changed from "0" to "1". The inverter circuit 18 receives and inverts the address data A0 to A4 (A5 to Al6) output from the latch circuit 17.

By setting the address buffer circuits 2 and 5 as shown in FIG. 11, when the signal CEB becomes "1" and the signal ICE becomes "0", the delayed signal ICE becomes a delay circuit ( 15) to the NAND gate circuit 16. By this delayed signal ICE, the address buffer circuits 2 and 5 can be made inactive by turning off the NAND gate.

Example 4

In the first embodiment described above, as shown in Figs. 12A to 12B, when the memory address designated by the lower address data A0 to A4 is 0, the upper address data A5 to A16 are also replaced at the same time. As a result, as shown in FIG. 13, the row select data (word line signal WL (i) to word line signal WL (k)) output from the X decoder circuit 3 is replaced. Therefore, when specifying the memory address of memory address # 0 designated by the lower addresses A0 to A4, the word line signals WL (i) to WL (k) and the bit line signals BL0 to BL31 must be replaced together. Therefore, it takes time for these signals to stabilize together, the reading time by that time becomes long, and the reading time of the whole Chinese character ROM circuit 1 becomes long.

Therefore, in order to improve the reading speed with respect to the memory address of the memory address # 0 designated by the lower addresses A0 to A4, as shown in FIG. 14, each memory cell constituting the memory cell array circuit 4 ( The memory cell 20 corresponding to the memory address of # 0 by the wiring 22 having a relatively low resistance such as metal, so as to be parallel to the wiring 21 such as polysilicon having a relatively high resistance for connecting the 20). And a wiring 22 for connecting the output terminal of the X decoder circuit 3 to each other may be provided.

With this configuration, when selecting the memory address of memory address # 0 designated by the lower addresses A0 to A4, the time until the gate voltage of each memory cell 20 is stabilized is shortened, and the time required for reading This can shorten the speed of reading the entire Chinese character ROM circuit 1.

Example 5

As a method other than the above-described improvement method, for example, as shown in FIG. 15, the channel width W1 of the memory cell 20a corresponding to the memory address of # 0 is made larger than the channel width W2 of the other memory cells 20b. The driving force of the memory cell 20a corresponding to the memory address of memory address # 0 designated by the lower addresses A0 to A4 may be improved.

As such, when only the memory cell 20a corresponding to the memory address of memory address # 0 designated by the lower addresses A0 to A4 is made larger in the channel side W1, the memory address designated by the lower addresses A0 to A4 is suppressed while increasing the chip surface. When selecting the memory address of # 0, the reading speed can be increased.

Example 6

As a method other than the above-described improvement method, for example, as shown in FIG. 16, a memory constituted by memory cells 20 corresponding to memory addresses of memory address # 0 designated by lower addresses A0 to A4, respectively. In the cell array circuit 4a, the memory cell array circuit 4b constituted by the memory cells 20 corresponding to the memory address of the memory address # 0 designated by the lower addresses A0 to A4 may be separately provided. . By constituting the memory cell array 4b with a device having a high operating speed, the time required for reading is shortened when selecting the memory address of memory address # 0 designated by the lower addresses A0 to A4. The reading speed of the entire circuit 1 can be increased.

In this case, the address data X specifying the Chinese character code output from the address buffer circuit 2 is supplied to the X decoder circuit 3, and the memory address # designated by the lower addresses A0 to A4 from the memory cell array circuit 4a. Outputs word data stored in memory address other than 0. The address data X is also supplied to the memory cell array circuit 4b to output word data stored in the memory address of the memory address # 0 designated by the lower addresses A0 to A4 from the memory cell array circuit 4b.

In this state, when the column selection data YG0 is output from the Y decoder circuit 6, the word data output from the memory cell array circuit 4b is selected. When one of the column selection data YG1 to YG31 is output from the Y decoder circuit 6, word data output from the memory cell array circuit 4a is selected to designate the address data A5 to A16. Each word data of the Chinese character font data is read.

Example 7

In the first to sixth embodiments, the Chinese character codes are designated by the upper address data A5 to A16, the lower address data A0 to A4 are replaced, and each word data of the Chinese character font designated by the Chinese character code is sequentially designated. However, as shown in FIG. 17, the counter circuit 26 may be provided in place of the address buffer circuit 5. As shown in FIG. The counter circuit 26 is configured to count the clock signal CK input from the outside and input the count result to the Y decoder circuit 6 as address data Y.

With such a configuration, the lower addresses A0 to A4 can be generated in the Chinese character ROM 1. Thereby, the five address data lines necessary for transferring the address data A0 to A4 can be replaced with only one clock signal line for transmitting the clock signal CK.

As a result, four signal lines are deleted, and the number of terminals of the chip can be reduced by that amount.

When using the kanji ROM circuit 1 of the seventh embodiment instead of the kanji ROM circuit used in a normal system, as shown in FIG. 18, the address circuit A0 output from the system side is used as a clock signal CK as a counter circuit. It may be configured to input to the clock input terminal of (26). In this case, a NOR gate circuit 27 is provided to calculate the logical sum of the address data A0 to A4 supplied from the system side, to generate a reset signal LTR, and to the reset terminal of the counter circuit 26. It is set as input structure.

Incidentally, in the above-described embodiments 1 to 7, the word data constituting the Chinese character font is read from the Chinese character ROM circuit 1 using the address data A0 to A16, but according to the required storage capacity of the ROM circuit, the MSB It may be configured to determine (least significant bit).

As described above, according to the present invention, it is possible to provide a ROM circuit which can read font data at high speed while reducing the power consumption of the circuit, the package area of the chip, the number of address pins, and the like. It can greatly improve the display speed of Chinese characters.

Claims (6)

A memory cell array circuit for arranging and holding one of the component data constituting each of the data in a single row of memory cell groups; A first circuit for designating a single row in the memory cell array circuit by upper address data; And a second circuit that designates each memory in a single row in the memory cell array circuit by the lower address data, and continuously designates one component data by designating the upper address and subsequently specifying the lower address. ROM circuit comprising a configuration for reading. 2. The ROM circuit according to claim 1, wherein when the chip activation signal transitions to an inactive state, upper address data is held in the first circuit, and the same fixed length data is continuously designated by the upper address data. . The ROM circuit according to claim 1 or 2, wherein the word line wiring resistance of the memory cell selected when the lower address data is a predetermined value is smaller than the word line wiring resistance of the other memory cells. The ROM circuit according to claim 1 or 2, wherein a channel width of a memory cell selected when the lower address data is a predetermined value is made larger than a channel width of another memory cell. 3. The first memory cell array according to claim 1 or 2, wherein the memory cell array is selected when the lower address data is set to a predetermined value, and the first memory cell array is selected when the lower address data is other than a predetermined value. The characteristics of the first and second memory cell arrays are set in two memory cell arrays so that the first memory cell array reads the first memory cell array faster than the second memory cell array reads. ROM circuit. The clock signal according to claim 1 or 2, wherein a clock signal is input together with the upper address data, one of the data is designated by the upper address data, and the count value is obtained by counting the clock signal. And consecutively designating component data constituting the data specified by the upper address data.

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