KR100269630B1 - A method of fabricating semiconductor device - Google Patents
A method of fabricating semiconductor device Download PDFInfo
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- KR100269630B1 KR100269630B1 KR1019980040427A KR19980040427A KR100269630B1 KR 100269630 B1 KR100269630 B1 KR 100269630B1 KR 1019980040427 A KR1019980040427 A KR 1019980040427A KR 19980040427 A KR19980040427 A KR 19980040427A KR 100269630 B1 KR100269630 B1 KR 100269630B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000011810 insulating material Substances 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims 1
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 229910017052 cobalt Inorganic materials 0.000 abstract description 8
- 239000010941 cobalt Substances 0.000 abstract description 8
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 abstract description 8
- 238000012421 spiking Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 238000005530 etching Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 코발트 살리사이드 형성시 발생하는 스파이킹 현상을 정합 산화막(conformal oxide)을 형성하므로서 방지하는데 적합하도록 한 반도체장치의 살리사이드 형성공정에 관한 것이다. 본 발명의 반도체장치의 제조방법은 게이트절연막이 형성된 제 1 도전형의 반도체기판 상에 게이트절연막을 개재시켜 제 1 간격과 제 1 간격보다 큰 제 2 간격으로 이격된 복수의 게이트를 형성하는 공정과, 게이트를 마스크로 사용하여 반도체기판에 제 2 도전형의 저농도불순물 매몰층을 형성하는 공정과, 게이트 및 게이트절연막 측면에 절연물질로 측벽을 형성하는 단계와, 게이트 및 측벽을 마스크로 사용하여 반도체기판에 제 2 도전형의 고농도 불순물 매몰층을 형성하는 단계와, 제 1 간격으로 이격된 게이트 사이의 기판 표면에 정합절연막을 형성하는 단계와, 게이트 상부 표면과 측벽 그리고 정합절연막 표면을 포함하는 기판 표면에 금속층을 형성하는 단계와, 금속층을 열처리하여 게이트 상부 표면과 제 2 간격에 있는 고농도 불순물 매몰층 표면에 실리사이드층을 형성하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a process for forming a salicide of a semiconductor device, which is suitable for preventing spiking phenomena generated during formation of cobalt salicide by forming a conformal oxide. A method of manufacturing a semiconductor device of the present invention comprises the steps of forming a plurality of gates spaced apart from a first interval and a second interval larger than the first interval by interposing a gate insulating layer on a first conductive semiconductor substrate having a gate insulating layer formed thereon; Forming a low-concentration impurity buried layer of a second conductivity type on the semiconductor substrate using the gate as a mask; forming a sidewall of an insulating material on the side of the gate and the gate insulating film; and using the gate and the sidewall as a mask. Forming a second conductivity type impurity buried layer in the substrate, forming a matched insulating film on the surface of the substrate between the gates spaced at a first interval, and a substrate including a gate upper surface, sidewalls, and a matched insulating film surface Forming a metal layer on the surface, and heat treating the metal layer to form a high concentration impurity buried layer at a second distance from the gate upper surface. It comprises the step of forming a silicide layer on a surface.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 코발트 살리사이드 형성시 발생하는 스파이킹 현상을 정합 산화막(conformal oxide)을 형성하므로서 방지하는데 적합하도록 한 반도체장치의 살리사이드 형성공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a process for forming a salicide of a semiconductor device, which is suitable for preventing spiking phenomena generated during formation of cobalt salicide by forming a conformal oxide.
반도체장치가 고집적화됨에 따라 소오스 및 드레인영역으로 이용되는 불순물영역과 게이트의 폭이 감소되고 있다. 이에 따라, 반도체장치는 불순물영역의 접촉 저항 및 게이트의 시트 저항이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.As semiconductor devices are highly integrated, the widths of impurity regions and gates used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance of a gate.
그러므로, 반도체장치 내의 소자들의 배선을 알루미늄 합금 및 텅스텐 등의 저저항 물질로 형성하거나, 또는, 게이트와 같이 다결정실리콘으로 형성하는 경우에 실리사이드층을 형성하여 저항을 감소시킨다. 상기에서 다결정실리콘으로 형성된 게이트에 실리사이드층을 형성할 때 불순물영역의 표면에도 실리사이드층을 형성하여 접촉 저항을 감소시킨다.Therefore, when the wirings of the elements in the semiconductor device are formed of low-resistance materials such as aluminum alloy and tungsten, or formed of polycrystalline silicon such as a gate, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate formed of polycrystalline silicon, a silicide layer is also formed on the surface of the impurity region to reduce the contact resistance.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.
도 1a를 참조하면, P형의 반도체기판(1)의 소정 부분에 LOCOS(Local Oxidation of Silicon) 방법 등의 소자격리방법에 의해 필드산화막(도시안함)을 형성하여 소자의 활성영역과 소자격리영역을 형성한다.Referring to FIG. 1A, a field oxide film (not shown) is formed on a predetermined portion of a P-type semiconductor substrate 1 by a device isolation method such as LOCOS (Local Oxidation of Silicon) method to form an active region and a device isolation region of the device. To form.
그리고 반도체기판(1)의 표면을 열산화하여 게이트산화막(2)을 형성한다. 그리고, 게이트산화막(2)의 상부에 불순물이 도핑된 다결정실리콘을 증착하고 패터닝하여 게이트(3)를 한정한다. 게이트(3)를 마스크로 사용하여 반도체기판(1)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 저농도로 이온 주입하여 LDD(Lightly Doped Drain) 구조를 형성하기 위한 저농도영역(도시안함)을 형성한다.The surface of the semiconductor substrate 1 is thermally oxidized to form a gate oxide film 2. The gate 3 is defined by depositing and patterning polycrystalline silicon doped with impurities on the gate oxide film 2. Low concentration region for forming LDD (Lightly Doped Drain) structure by ion implanting N-type impurities such as asic (As) or phosphorus (P) into the semiconductor substrate 1 at low concentration using the gate 3 as a mask ( Not shown).
그다음, 게이트(3)와 게이트산화막(2)의 측면에 측벽(4)을 형성한다. 상기에서 측벽(4)은 반도체기판(1) 상에 게이트(3)를 덮도록 산화실리콘을 증착하고 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법 등으로 에치백(etchback)하므로써 형성된다. 그리고, 게이트(3)와 측벽(4)을 마스크로 사용하여 반도체기판(1)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 고농도로 이온 주입하여 소오스 및 드레인영역으로 이용되는 고농도영역을 저농도영역과 중첩되게 형성한다.Next, sidewalls 4 are formed on the side surfaces of the gate 3 and the gate oxide film 2. The side wall 4 is formed by depositing silicon oxide on the semiconductor substrate 1 so as to cover the gate 3 and etching back by a reactive ion etching (hereinafter referred to as RIE) method. do. Then, using the gate 3 and the sidewall 4 as a mask, the semiconductor substrate 1 is ion-implanted with high concentration of N-type impurities such as an asic (As) or phosphorus (P) to serve as a source and a drain region. The high concentration region is formed to overlap with the low concentration region.
이와 같이 형성된 게이트간의 간격은 그 사이가 0.2 ㎛ 이하의 좁은 부위(50)와 넓은 부위(51)로 구분된다.The spacing between the gates thus formed is divided into a narrow portion 50 and a wide portion 51 having a thickness of 0.2 μm or less therebetween.
도 1b를 참조하면, 반도체기판(1) 게이트(3) 및 측벽(4)를 덮도록 Co 등의 고융점 금속(6)을 증착한다.Referring to FIG. 1B, a high melting point metal 6 such as Co is deposited to cover the gate 3 and the sidewall 4 of the semiconductor substrate 1.
도 1c를 참조하면, 반도체 기판을 RTA(Rapid Thermal Annealing) 방법으로 2번의 열처리하여 게이트(3) 및 고농도영역의 표면에만 자기 정렬된 실리사이드층(6)을 형성한다. 이때, 스파이킹부위(7)가 형성된다.Referring to FIG. 1C, the semiconductor substrate is heat treated twice using a rapid thermal annealing (RTA) method to form a silicide layer 6 self-aligned only on the surface of the gate 3 and the high concentration region. At this time, the spiking portion 7 is formed.
상기에서, 실리사이드층(6)은 750℃ 이하의 온도에서 1차 열처리하고 게이트(3) 및 고농도영역의 표면에만 잔류하도록 필드산화막 및 측벽(4) 상에 반응하지 않은 고융점금속을 에치 백하여 제거한 후, 다시, 게이트(3) 및 고농도영역 상에 잔류하는 것을 850∼950℃의 온도에서 2차 열처리하므로써 형성된다. 이때, 좁은 부위(50)와 넓은 부위(51)에서의 살리시데이션(salicidation)시 특히 좁은 부위(50)에서는 Co 특성상 다량의 실리콘이 반응에 참여하므로 Co의 Si에 대한 상대적인 양의 차이에 기인하여 활성영역에서 스파이킹(spiking) 현상이 일어나게 되며 그 깊이는 약 600Å 정도 된다.In the above, the silicide layer 6 is subjected to a first heat treatment at a temperature of 750 ° C. or lower and etched back unreacted high melting point metal on the field oxide film and the sidewall 4 so as to remain only on the surface of the gate 3 and the high concentration region. After removal, the residue remaining on the gate 3 and the high concentration region is formed by secondary heat treatment at a temperature of 850 to 950 ° C. At this time, in the case of salicidation in the narrow region 50 and the wide region 51, particularly in the narrow region 50, a large amount of silicon participates in the reaction due to the difference in the relative amount of Co to Si. Spikes occur in the active region and are about 600 microns deep.
상술한 바와 같이 종래 기술에서 Co-살리사이드층은 소자가 고집적화됨에 따라 후속 열공정에서 전술한 스파이킹 현상이 일어나는 깊이보다 깊어지게 되어 졍션 누설전류의 특성을 저하시키는 문제점이 있다.As described above, in the prior art, the Co-salicide layer is deeper than the depth at which the above-described spiking occurs in a subsequent thermal process as the device is highly integrated, thereby degrading the characteristic of the leakage leakage current.
따라서, 본 발명의 목적은 코발트 살리사이드 형성시 발생하는 스파이킹 현상을 정합 산화막(conformal oxide)을 형성하므로서 방지하는데 적합하도록 한 반도체장치의 살리사이드 형성공정을 제공하는데 있다.Accordingly, an object of the present invention is to provide a salicide forming process of a semiconductor device, which is suitable for preventing the spiking phenomenon occurring during cobalt salicide formation by forming a conformal oxide.
상기 목적들을 달성하기 위한 본 발명의 반도체장치의 제조방법은 게이트절연막이 형성된 제 1 도전형의 반도체기판 상에 게이트절연막을 개재시켜 제 1 간격과 제 1 간격보다 큰 제 2 간격으로 이격된 복수의 게이트를 형성하는 공정과, 게이트를 마스크로 사용하여 반도체기판에 제 2 도전형의 저농도불순물 매몰층을 형성하는 공정과, 게이트 및 게이트절연막 측면에 절연물질로 측벽을 형성하는 단계와, 게이트 및 측벽을 마스크로 사용하여 반도체기판에 제 2 도전형의 고농도 불순물 매몰층을 형성하는 단계와, 제 1 간격으로 이격된 게이트 사이의 기판 표면에 정합절연막을 형성하는 단계와, 게이트 상부 표면과 측벽 그리고 정합절연막 표면을 포함하는 기판 표면에 금속층을 형성하는 단계와, 금속층을 열처리하여 게이트 상부 표면과 제 2 간격에 있는 고농도 불순물 매몰층 표면에 실리사이드층을 형성하는 단계를 포함하여 이루어진다.A semiconductor device manufacturing method of the present invention for achieving the above object is a plurality of spaced apart at a first interval and a second interval larger than the first interval by interposing a gate insulating film on a first conductive semiconductor substrate having a gate insulating film formed; Forming a gate, forming a low-concentration impurity buried layer of a second conductivity type on a semiconductor substrate using the gate as a mask, forming a sidewall of an insulating material on the side of the gate and the gate insulating film, and forming the gate and the sidewall. Forming a second conductivity type impurity buried layer in a semiconductor substrate using a mask as a mask, and forming a matched insulating film on the surface of the substrate between the gates spaced at a first interval, the gate upper surface, sidewalls, and matching Forming a metal layer on the surface of the substrate including the insulating film surface, and heat treating the metal layer to form a second gap with the gate upper surface. A high concentration impurity buried layer surface, which comprises the step of forming a silicide layer.
도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 살리사이드 형성공정 단면도1A to 1C are cross-sectional views of a salicide forming process of a semiconductor device according to the related art.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체장치의 살리사이드 형성공정 단면도2A to 2D are cross-sectional views of a salicide forming process of a semiconductor device according to an embodiment of the present invention.
본 발명은 코발트 살리사이드 형성전에 정합산화막을 증착한 후 이를 비등방성 식각으로 소정 부위를 제거하므로서 게이트패턴 사이의 넓은 부위의 활성영역을 개방시키고 좁은 부위는 정합산화막으로 매립하므로서 이후 증착되는 코발트층에 의해 살리사이드가 선택적으로 증착되게 한다.The present invention deposits a matched oxide film before forming cobalt salicide and then removes a predetermined region by anisotropic etching, thereby opening the active region of the wide region between the gate patterns and filling the narrow region with the matched oxide layer, thereby depositing the covalent layer. Thereby allowing salicide to be selectively deposited.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 반도체장치의 살리사이드 형성공정 단면도이다.2A to 2D are cross-sectional views of a salicide forming process of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, P형의 반도체기판(21)의 소정 부분에 LOCOS(Local Oxidation of Silicon) 방법 등의 소자격리방법에 의해 필드산화막(도시안함)을 형성하여 소자의 활성영역과 소자격리영역을 형성한다.Referring to FIG. 2A, a field oxide film (not shown) is formed on a predetermined portion of a P-type semiconductor substrate 21 by a device isolation method such as LOCOS (Local Oxidation of Silicon) method to form an active region and an isolation region of a device. To form.
그리고 반도체기판(21)의 표면을 열산화하여 게이트산화막(22)을 형성한다. 그리고, 게이트산화막(22)의 상부에 불순물이 도핑된 다결정실리콘을 증착하고 패터닝하여 게이트(23)를 한정한다. 게이트(23)를 마스크로 사용하여 반도체기판(21)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 저농도로 이온 주입하여 LDD(Lightly Doped Drain) 구조를 형성하기 위한 저농도영역(도시안함)을 형성한다.The surface of the semiconductor substrate 21 is thermally oxidized to form a gate oxide film 22. The gate 23 is defined by depositing and patterning polycrystalline silicon doped with impurities on the gate oxide layer 22. Low concentration region for forming LDD (Lightly Doped Drain) structure by ion implantation of N-type impurities such as asic (As) or phosphorus (P) into the semiconductor substrate 21 at low concentration using the gate 23 as a mask ( Not shown).
그다음, 게이트(23)와 게이트산화막(22)의 측면에 측벽(24)을 형성한다. 상기에서 측벽(24)은 반도체기판(21) 상에 게이트(23)를 덮도록 산화실리콘을 증착하고 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법 등으로 에치백(etchback)하므로써 형성된다. 그리고, 게이트(23)와 측벽(24)을 마스크로 사용하여 반도체기판(21)에 아세닉(As) 또는 인(P) 등의 N형 불순물을 고농도로 이온 주입하여 소오스 및 드레인영역으로 이용되는 고농도영역을 저농도영역과 중첩되게 형성한다.Next, sidewalls 24 are formed on the side surfaces of the gate 23 and the gate oxide film 22. The side wall 24 is formed by depositing silicon oxide on the semiconductor substrate 21 to cover the gate 23 and etching back by a reactive ion etching (hereinafter referred to as RIE) method. do. Then, using the gate 23 and the sidewall 24 as a mask, ion implantation of high concentrations of N-type impurities such as an asic (As) or phosphorus (P) into the semiconductor substrate 21 is used as a source and a drain region. The high concentration region is formed to overlap with the low concentration region.
이와 같이 형성된 게이트간의 간격은 그 사이가 0.2 ㎛ 이하의 좁은 부위(250)와 넓은 부위(251)로 구분된다.The gap between the gates formed as described above is divided into a narrow portion 250 and a wide portion 251 having a thickness of 0.2 μm or less therebetween.
도 2b를 참조하면, 게이트(23) 등을 포함하는 기판(21)의 표면에 정합산화막(conformal oxide layer, 26)을 에이치디피(HDP) 또는 에이치엘디(HLD)를 증착하여 형성한다. 이때, 정합산화막(26)은 게이트(23) 패턴 사이의 좁은 부위(250)를 매립하여 이후 증착되는 코발트층이 선택적으로 증착되게 한다.Referring to FIG. 2B, a conformal oxide layer 26 is formed on the surface of the substrate 21 including the gate 23 by depositing HDP or HLD. In this case, the matching oxide layer 26 fills the narrow portion 250 between the gate 23 patterns to selectively deposit the cobalt layer to be deposited.
도 2c를 참조하면, 좁은부위(250)를 덮는 식각보호마스크를 정합산화막(26) 위에 형성한 다음, 이로 부터 보호되지 아니하는 부위의 정합산화막을 비등방성식각 또는 에치백하여 제거한다. 그리고 식각보호마스크를 제거한다. 따라서, 좁은 부위(250)의 기판(21) 표면은 잔류한 정합산화막(26)으로 덮혀있기 때문에 이후, 코발트층이 기판 표면에 형성되는 것을 방지하여 이 부위에(250) 살리사이드층의 형성을 방해하므로서 스파이킹 현상이 발생하는 것을 방지한다.Referring to FIG. 2C, an etch protection mask covering the narrow portion 250 is formed on the matched oxide layer 26, and then the matched oxide layer is removed by anisotropic etching or etch back. Then remove the etch protection mask. Therefore, since the surface of the substrate 21 of the narrow portion 250 is covered with the remaining matched oxide film 26, the cobalt layer is prevented from being formed on the surface of the substrate, thereby forming the salicide layer 250 at this portion. This prevents spiking from occurring.
도 2d를 참조하면, 정합산화막(26) 표면을 포함하는 게이트(23) 및 측벽(24)를 덮도록 Co 등의 고융점 금속(6)을 기판(21) 위에 증착한다.Referring to FIG. 2D, a high melting point metal 6 such as Co is deposited on the substrate 21 to cover the gate 23 and the sidewalls 24 including the surface of the matching oxide film 26.
그리고, 반도체 기판(21)을 RTA(Rapid Thermal Annealing) 방법으로 2번의 열처리하여 게이트(23) 상부 표면 및 고농도영역의 표면에만 자기 정렬된 실리사이드층(26)을 형성한다. 이때, 정합산화막(26)이 형성된 기판 표면에는 살리사이드가 형성되지 아니하므로 스파이킹부위의 생성이 방지된다.The semiconductor substrate 21 is heat treated twice using a rapid thermal annealing (RTA) method to form a silicide layer 26 self-aligned only on the upper surface of the gate 23 and the surface of the high concentration region. In this case, since no salicide is formed on the surface of the substrate on which the matching oxide film 26 is formed, the generation of the spiking portion is prevented.
따라서, 본 발명은 게이트 사이의 상대적으로 좁은 부위의 활성층 표면에 코발트 살리사이드층의 형성을 방지하므로서 코발트 살라시데이션에 의한 스파이킹 문제를 해결하고 좁은 부위의 매립을 위한 정합산화막 식각공정시 게이트 측벽을 선택적으로 식각하므로서 살리사이드가 형성되는 게이트 표면적을 크게하여 게이트 저항을 감소시키는 장점이 있다.Accordingly, the present invention solves the problem of cobalt salicide formation by preventing the formation of a cobalt salicide layer on the surface of the active layer of the relatively narrow region between the gates and gate sidewalls during the matching oxide etching process for embedding the narrow region. By selectively etching to increase the gate surface area on which the salicide is formed to reduce the gate resistance.
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