KR100269430B1 - Randomizer of the cable modem system in the downstream direction - Google Patents

Abstract

The present invention relates to a randomization apparatus for transforming data in order to obtain synchronization of symbol data during demodulation, wherein the constant term of the randomized polynomial F (X) on the galloace field GF (2 ^m ) is excluded from '1'. In the feedback register section for implementing a randomized polynomial in the case of the element α ^{K in the} Aceh field, a galloise constant term processing for feeding back the highest order output of the register section and the constant term α ^K is fed back to the lowest order input section of the register section. It is about. Galoache constant term processing consists of K elementary element (α) processing units for multiplying the input element with the elemental element (α) in the corresponding Galoache field, and is connected in series. The bits of the input elements are manipulated appropriately according to the multiplication rule determined to obtain a galloche element multiplied by the α operation by a logical operation. In order to process α ^K galloache multiplication, conventionally, all of the galloache field elements are stored, which requires considerable memory and has difficulty in addressing the memory. However, the present invention performs the galloise multiplication operation by bit logic operation. This eliminates the need for memory, eases implementation, and enables high-speed processing.

Description

Randomizer of the cable modem system in the downstream direction

The present invention relates to a randomization apparatus for transforming and transmitting transmission symbol data to obtain synchronization of symbol data during demodulation.

Data transmitted from a digital transmission system is distorted due to crosstalk with other channels or exposure to various noises while being transmitted through a channel. The receiving side must recover the correct original data from the distorted data. To this end, the transmitting side randomizes and transmits data so that the receiving side maintains an optimal reception state. In other words, by randomizing the information data by the pseudo noise code promised between the transmitting and receiving sides, it is possible to prevent the other side from being confused with other channels during transmission and to extract a specific synchronization from the receiving side.

The pseudo-noise code may be generated by a specific Galois polynomial on the Galois field, and an application thereof may include a randomization / derandomization apparatus for downstream transmission of a cable modem network.

Cable modem network provides various services such as telecommuting, video conferencing, and web search to subscribers by connecting to internet and intranet together with Integrated Information Communication Network (ISDN) and Multi-Digital Subscriber Line (xDSL).

1 is a reference diagram of a cable modem network that supports broadband service. A headend 110 including a cable modem termination system (hereinafter referred to as CMTS) is connected to a backbone network 100 including a private network or a public network provided by a communication network operator. The cable modem 130 (hereinafter referred to as CM) is connected. Between the head end 110 and the CM (130) is located a photoelectric converter (120, Optic / Electro Converter) is connected by the optical cable to convert the optical signal and the electrical signal, the photoelectric converter 120 and the CM (130), The CM 130 and the subscriber side 140 are connected by coaxial cable. Bi-directional communication is possible between the service provider and the subscriber side, and the two bidirectional communication paths are combined at the headend 110. The headend 110 includes a CMTS 111 that enables bidirectional communication, an operation support system for the CMTS 111 (not shown), and a combiner 112 that transmits various application services of an information provider by combining data signals. And a transmission buffer 114, a reception buffer 115 and a distributor 113 for receiving and distributing subscriber request data, and a security and access control unit 116. The CMTS 111 includes a network terminal 111-1 in charge of the CMTS and a network interface, a modulator 111-2 for modulating application service data (downstream data) of an information provider, and request data of a subscriber ( Demodulation section 111-3 for demodulating upstream data). The cable modem network shown in FIG. 1 is a broadband system using RF signals, and an RF interface exists between the CM and the cable network, between the CMTS and the cable network downstream, and between the CMTS and the cable network upstream.

The downstream channel transmitted from CMTS to each CM broadcasts broadband service data at a transmission rate of 50 to 860 MHz, and the upstream channel transmitted from CM to CMTS is 5 to 42 MHz. Send in a point-to-point fashion

The downstream protocol of the cable modem transmission system is as defined in ITU-T Recommendations J.83, Annex B. The downstream signal processing is shown in FIG. The downstream modulation process is performed by framing the MPEG-2 data stream input in the packet unit from the MPEG frame unit 200, and then performing a forward error correction algorithm in the FEC encoder 210 to perform a channel ( To obtain reliable data. The FEC code output from the FEC encoder 210 is QAM modulated by the QAM modulator 220 and then transmitted through the cable channel 230 as an RF signal. The downstream demodulation is performed through the QAM demodulator 240, the FEC decoder 250, and the MPEG frame unit 260 in a reverse process to modulation. The MPEG framing process provides a parity check pattern for packet synchronization between the transmitter and the receiver. The QAM modulation process supports 64QAM mode and 256QAM mode. The FEC encoding process uses a concatenated coding technique, and an outer coder uses a Reed-Solomon code having T error correction capabilities, and an inner coder. By using the TCM codeword to generate the coded modulation code, the error that is not corrected by the internal decoder is usually corrected by the external decoder so that the error rate is almost zero.

3, the FEC encoder 210 (see FIG. 2) is composed of a Reed Solomon encoder 300, an interleaver 310, a randomizer 320, and a trellis encoder 330. The FEC decoder 250 includes a trellis decoder 350, an inverse randomizer 360, a deinterleaver 370, and a Reed Solomon decoder 380.

The Reed Solomon encoder 300 encodes the MPEG transport stream using a (128,122) RS block code. The (128,122) RS block code consists of 128 symbols per block, of which only 122 symbols are information symbols and 6 symbols are parity for error correction, so up to 3 symbols per RS block are error corrected. The RS block code is used identically in the 64QAM mode and the 256QAM mode.

The interleaver 310 convolutionally interleaves the (128, 122) RS block codes to rearrange the data streams. The interleaver 310 is for efficiently coping with successive error symbols (cluster errors, burst errors) generated during channel transmission. The convolutional interleaver structure supports a programmable structure, that is, various interleaving modes in 64QAM mode and 256QAM mode.

The randomization unit 320 randomizes the interleaved data so that the interleaved data does not have a specific pattern, thereby preventing the RF-modulated signal from interfering with other channels and extracting synchronization from the receiver. Randomized data is output by generating a pseudo noise code promised with the receiver and adding it to the input data.

The trellis encoder 330 performs trellis coded modulation (TCM). TCM is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel and is implemented by combining a coding technique and a modulation technique. The TCM structure is composed of a convolutional encoder having a finite state and a QAM modulator (64 / 256QAM).

Particularly, the randomization unit 320 randomizes the data and transmits the data by using the QAM modulation technique. The carrier phase is converted by input bits, and the receiver side compares the phase shift value of the current symbol with the phase value of the next symbol. This is because the transmitting side and the receiving side for decoding the original data are synchronized. If the receiving side attempts to synchronize, if data bits of "1" or "0" are long, data burst errors that cannot synchronize each data burst occur. Therefore, the data bit stream is randomized and transmitted so that a sufficient phase change occurs in the receiver so as to synchronize the reception clock. In addition, it is important that the algorithm of the FEC demodulation circuit of a general receiver cannot be demodulated properly unless the modulated data string is a random pattern.

The randomization unit 320 randomizes the input data stream by adding input data, that is, 7-bit RS symbols, using a 7-bit symbol as a pseudo noise (PN) code on the galloche field GF 128. In addition, while the synchronization signal of the FEC frame is inserted, the randomization unit 320 is initialized and operates from when the first symbol is actually input to output a randomized symbol.

The randomization polynomial of the randomizer is F (X) = X ³ + X + α ³ , The constant α ³ Is a polynomial of the seventh order in Galoache α ⁷ + α ³ + 1 = 0 Is implemented by applying The randomization apparatus is basically composed of a feedback register section according to the order and an adder for performing an exclusive logic sum operation on the pseudo noise generated by the feedback register and the input data to be randomized.

In the conventional randomization apparatus filed by the present inventors, the feedback register unit includes a galloach constant processing unit for multiplying the highest order output of the register by the galloace constant α ³ and inputting the lowest order term of the register. The Galoache constant processing unit includes a memory that stores all the elements on the Galoache field, and multiplies the Galois elements increased by the third order from the matched elements after matching the Galoache elements corresponding to the highest order term input. Output the result.

Therefore, the conventional randomizer has a disadvantage in that a considerable amount of memory is required to process the Galoache constant, and the processing time is delayed because the memory must be accessed.

Accordingly, the present invention provides a randomization apparatus for presenting regularity between galloache field table elements for constant term processing of a randomized polynomial, and performing galloa multiplication operation with a simple bit logic combination according to the regularity. There is a purpose.

The present invention for achieving the above object is to modify the input symbol when the constant term of the randomized polynomial F (X) on the galloche field GF (2 ^m ) is the element α ^{K in the} galloche field except for '1' A randomization apparatus comprising: a feedback register section for providing a predetermined code to make a predetermined code;

The feedback register section includes a plurality of register groups determined according to a randomized polynomial order; The first element processing unit outputs the highest order of the plurality of register groups while K is provided in series with the K element processing unit (α) for multiplying the input element and the element (α) in the corresponding Galoache field. Is provided to provide the result of α times operation to the second basic element processing unit, and the output of the K-th α processing unit includes a Galoiche constant (α ^K ) processing unit which provides the lowest difference input among the plurality of register groups. It is characterized by.

1 is a reference configuration diagram of a cable modem network supporting broadband services;

2 is a block diagram showing a downstream signal processing procedure of a cable modem transmission system;

3 is a block diagram of a forward error correction unit of FIG. 2;

4 is an element table on Galoache field GF (2 ⁷ ),

5 is a block diagram illustrating a randomization apparatus implementing the randomized polynomial F (X) = X ³ + X + α ³ according to the present invention;

6 is a detailed embodiment of the basic element (α) processing unit of the galloche constant treatment unit of FIG.

Explanation of symbols on the main parts of the drawings

500: feedback register section FR1 to FR3: register

510: Galoache constant (α ^K ) processing unit 520, 530: Exclusive logic gate

540: initialization unit 600,610,620: basic element (α) processing unit

700, 710: Register 720: Exclusive logic gate

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

First, to describe the galloache field in which the randomization unit operates, the galloache field is a number system having only a finite number of elements, and the galloache field denoted by GF (q) performs various operations while having q elements. The resulting value is also a number system with one of q elements. In particular, in finite galloise water systems, since no overflow occurs, it is useful for processing digital data. In addition, the number of elements of galloache field GF (2 ^m ) in which the GF (2) having {0,1} as an element is expanded by m order is 2 ^m , and only m bases are required to express all these elements. . In other words, hardware can be implemented with m-bit binary digits. At this time, the base set is {α ⁰ , α ¹ , α ² , α ³ ,... , α ^q } As can be expressed by the power of α, the base α, which is the most basic, is called a primitive element, and the polynomial having the root is called a primitive polynomial. Polynomials that are no longer divided by other expressions among primitive polynomials are called prime primitive polynomials, and prime primitive polynomials make field distinctions. Prime primitive polynomials are generally called field generator polynomials.

The result of the addition or multiplication operation on the Galoache field GF (2 ^m ) is also the field generation polynomial F (x) which determines to be the value on the field is determined according to the value of m. Field generation polynomials are shown in.

Field generation polynomial F (x) of GF (2 ^m ) according to ^m m F (x) m F (x) 2 x ² + x + 1 6 x ⁶ + x + 1 3 x ³ + x + 1 7 x ⁷ + x ³ +1 4 x ⁴ + x + 1 8 x ⁸ + x ⁴ + x ³ + x ² +1 5 x ⁵ + x ² +1 9 x ⁹ + x ⁴ +1

This embodiment is applied to a randomization device or a derandomization device implemented for cable modem network downstream transmission. The randomized polynomial of this embodiment is F (X) = X ³ + X + α ³ , Where the constant term α ³ Is a polynomial of the seventh order in Galoache α ⁷ + α ³ + 1 = 0 Is implemented by applying

Galoache Field GF (2⁷The table of all the elements on) is shown in FIG. 4. Each element is represented by the power of base element α. Element αⁱ(Integer with 0≤i≤126) is a 7-bit binary tuple (a₀, a_One, a₂, a₃, a₄, a₅, a₆), Which is αⁱ= a₀+ a_Oneα^One+ a₂α²+ a₃α³+ a₄α⁴+ a₅α⁵+ a₆α⁶It is expressed as The 7-bit binary value of each element shown in FIG. 4 is the leftmost a₀ this LSB, far right a₆ This is MSB.

The Galoache multiplication rule on the Galoache field is explained as follows. For example, multiply α ⁸ = (0,1,0,0,1,0,0) multiplied by multiplier α = (0,1,0,0,0,0,0) is α ⁹ , The result of multiplying the multiplier α ² is α ¹⁰ . By the prime primitive polynomial, α ⁷ = α ³ +1 and α ⁸ α = (α ³ +1) α ² = α ⁵ + α ² = (0000010) + (0010000) = (0010010) = α ⁹ . As a result, an element multiplied by the order of the element corresponding to the multiplier from the element corresponding to the multiplier corresponds to the result of multiplication.

5 is a block diagram of a randomization apparatus implementing the randomized polynomial F (X) = X ³ + X + α ³ according to the present invention.

The randomization apparatus includes a feedback register unit 500 for providing a predetermined pseudo noise for transforming an input symbol, an adder 530 for performing an exclusive logic operation on the input symbol and the pseudo noise of the feedback register unit, and outputting every frame synchronization. Is composed of an initialization unit 540 which provides an initial value of the feedback register.

The feedback register unit 500 is the polynomial F (X) = X ³ + X + α ³ It consists of three 7-bit registers (FR1, FR2, FR3), a Galloche constant (α ³ ) processing unit 510, and an exclusive logic gate 520 that satisfy. In the galoache constant processing unit 510, three basic element (α) processing units 600, 610, and 620 are connected in series. The first exclusive logic gate 520 adds the contents of the first register FR1 and the contents of the third register FR3 to the second register FR2. The content of the second register FR2 is provided to the third register FR3, and the content of the third register FR3 is multiplied by the Galoache constant term α ³ (via the Galloache constant processing unit 510). Provided by one register (FR1).

The value output from the third register FR3 of the feedback register unit 500 and the input RS symbol data to be actually randomized are subjected to an exclusive logic operation through the adder 530 to be transformed into a randomized symbol.

The initialization unit 540 receives a control signal for initializing the entire receiving system and initializes the first to third registers FR1 to FR3 and the Galois constant processor 510 to "1", respectively. The initialization time is performed every frame. The reason is that the synchronization signal of the FEC frame should be transmitted as it is without being randomized. Therefore, the registers FR1 to FR3 and the Galloiche constant processing unit 510 remain disabled while the synchronization signal is inserted. This is because it must be enabled at the point of entry to generate a pseudo-noise code.

Performing the α ³ multiplication operation in the Galoache constant (α ³ ) processing unit 510 is the same as multiplying α three times, so that the three basic element (α) processing units 600, 610, and 620 performing the multiplication operation are serially connected. It is possible to implement. When the element input to the basic element processing unit is α ⁱ , the output thereof has been described as α ^{i + 1} . In other words. It is clear that the result obtained by multiplying the galloise by a fixed multiplier is a galloache element increased by the order of the multiplier and the element is already determined, so that the desired result can be obtained by appropriately manipulating the bits of the multiplicand. .

The rules for obtaining the multiplying result of a fixed multiplier α for any multiplier α ⁱ on the Galloise field are as follows.

In GF (2 ³ ): multiplication result if any multiplier α ⁱ = (a ₀ , a ₁ , a ₂ ) β = α ^{i + 1} = (a ₂ , a ₀ ⊕ a ₁ , a ₁ ).

In GF (2 ⁴ ): multiplication result if any multiplier α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ ) β = α ^{i + 1} = (a ₃ , a ₀ ⊕ a ₃ , a ₁ , a ₂ ).

In GF (2 ⁵ ): multiplication result if any multiplier α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ ) β = α ^{i + 1} = (a ₄ , a ₀ , a ₁ ⊕ a ₄ , a ₂ , a ₃ ).

In GF (2 ⁶ ): multiplication result if any multiplier α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ ) β = α ^{i + 1} = (a ₅ , a ₀ ⊕ a ₅ , a ₁ , a ₂ , a ₃ , a ₄ ).

In GF (2 ⁷ ): multiplication result if any multiplier α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ ) β = α ^{i + 1} = (a ₆ , a ₀ , a ₁ , a ₂ ⊕ a ₆ , a ₃ , a ₄ , a ₅ ).

FIG. 6 is a detailed embodiment of the basic element α processing unit 600 of the galloche constant processing unit 510 of FIG. 5. This embodiment applies the multiplication rule on GF 2 ⁷ .

The basic element processor 600 converts the MSB bit value among the outputs of the fourth register 700 and the third register FR3 into the MSB-3 bit value, which receives the output of the third register FR3 (see FIG. 5). The fifth register 710 receives an input and a logic operation unit 720. The fourth register 700 shifts the 7-bit input bit into the upper bit by one digit and outputs the MSB bit value by shifting to the LSB digit. The fifth register 710 is a seven bit register initialized to "0". The logic operation unit 720 performs a bit width exclusive logical sum operation on the output 7 bits of the fourth register 700 and the output 7 bits of the fifth register 710.

That is, when the element α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ ) is input to the basic element processing unit 600, the output of the fourth register 700 (a ₆ , a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ ) and the output (0,0,0, a ₆ , 0,0,0) of the fifth register 710 are bit-width exclusive Operation and the result (a ₆ , a ₀ , a ₁ , a ₂ ⊕ a ₆ , a ₄ , a ₅ ) = α ^{i + 1} .

The non-described second and third basic element processing units 610 and 620 may also be configured in the same manner as illustrated in FIG. 6.

As a result, the highest order output of the third register FR3 in the feedback register unit 500 is α ³ times multiplied by three basic element processing units 600, 610, and 620 connected in series, and then the result is output to the first register. Provided as the lowest difference input of (FR1).

The Galoache multiplication rules presented above may be effectively applied in various systems performing operations on the Galoache field. For example, it is applicable to systems using ReedSolomon encoders / decoders or ReedSolomon symbols.

As described above, in processing the constant term of a randomized polynomial, it has a disadvantage of increasing the cost and slowing the processing time because it requires a large amount of memory by storing all the galloach field elements and reading out the multiplied result. . The present invention presents the regularity of the result of performing a Galoache multiplication on the Galoache field, and it can be seen that the result of the multiplication operation by a bit manipulation of any multiplicand for a fixed multiplier is processed by a simple logical operation. The Galoache constant processing unit is a simple logical combination that performs an exclusive logical sum operation on shifted multiplicand bits and specific bits of a multiplicand, and is easy to implement.

Claims (4)

If the constant term of the randomized polynomial F (X) on the galloche field GF ( ^2m ) is an element α ^{K in the} galloise field except '1', the feedback register section provides a predetermined code for modifying the input symbol. A randomization device comprising: an exclusive logic sum operation of the highest order output and an input symbol of the feedback register unit to output a randomized symbol, The feedback register section A plurality of register groups determined according to a randomized polynomial order; The first element processing unit outputs the highest order of the plurality of register groups while K is provided in series with the K element processing unit (α) for multiplying the input element and the element (α) in the corresponding Galoache field. Is provided to provide the result of α times operation to the second basic element processing unit, and the output of the K-th α processing unit includes a Galoiche constant (α ^K ) processing unit which provides the lowest difference input among the plurality of register groups. Randomizing device, characterized in that. The method of claim 1, wherein the element processing unit (α) is characterized in that the logical operation of the bits of the input element in accordance with a predetermined rule determined by the galloach field in which the galoache constant is present, characterized in that for outputting the multiplication operation result. Randomizer. 2. The apparatus of claim 1, wherein the basic element (α) processor comprises: a first register configured to move an MSB bit value of an input element to an LSB bit position, move the remaining bits one position to an upper bit position, and output the results in parallel; A second register having an initial value of '0' and having the same bit width as that of the first register and loading the MSB bit value of the input element in a specific bit position and outputting the result in parallel; And a logic operation unit configured to output an output of the first register and the second register by performing a bit width exclusive OR operation. 3. The predetermined rule of claim 2, wherein the predetermined rule for obtaining a multiplied result of a fixed multiplier α for any multiplier α ⁱ present on the galloise field is In GF (2 ³ ): multiplication result if α ⁱ = (a ₀ , a ₁ , a ₂ ) β = α ^{i + 1} = (a ₂ , a ₀ ⊕ a ₁ , a ₁ ) In GF (2 ⁴ ): multiplication result if α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ ) β = α ^{i + 1} = (a ₃ , a ₀ ⊕ a ₃ , a ₁ , a ₂ ) In GF (2 ⁵ ): multiplication result if α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ ) β = α ^{i + 1} = (a ₄ , a ₀ , a ₁ ⊕ a ₄ , a ₂ , a ₃ ) In GF (2 ⁶ ): multiplication result if α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ ) β = α ^{i + 1} = (a ₅ , a ₀ ⊕ a ₅ , a ₁ , a ₂ , a ₃ , a ₄ ) In GF (2 ⁷ ): multiplication result when α ⁱ = (a ₀ , a ₁ , a ₂ , a ₃ , a ₄ , a ₅ , a ₆ ) β = α ^{i + 1} = (a ₆ , a ₀ , a ₁ , a ₂ ⊕ a ₆ , a ₃ , a ₄ , a ₅ ).