KR100269290B1 - Method for fabricating a Thin Film Transistor having a self-aligned offset structure and method for fabricating a Liquid Crystal Display using the same - Google Patents

Abstract

Disclosed are a thin film transistor having a fully self-aligned offset structure and a method of manufacturing a liquid crystal display using the same. The manufacturing method of the thin film transistor includes the steps of forming a gate electrode on the substrate, a storage capacitor electrode spaced a predetermined distance from the gate electrode, forming a gate insulating film and a semiconductor film on the resultant in turn, and a gate electrode and the storage capacitor electrode on the resultant. Forming an insulating film pattern for opening the formed region, implanting impurity ions into the semiconductor film using the insulating film pattern as a mask, forming a source / drain, and forming an insulating film on the resultant, Forming a contact hole exposing a portion of the source and the drain, and forming a source electrode / drain electrode connected to the source / drain through the contact hole.

Description

Method for fabricating a Thin Film Transistor having a self-aligned offset structure and method for fabricating a Liquid Crystal Display using the same

The present invention relates to a method of manufacturing a liquid crystal display, and more particularly, to a thin film transistor having a fully self-aligned offset structure and a method of manufacturing a liquid crystal display using the same.

Thin Film Transistors (LCDs) using thin film transistors as active elements (hereinafter referred to as "TFT-LCDs") have the advantages of low power consumption, low voltage driving force, thinness, and light weight. Among the thin film transistors, polysilicon TFTs using polysilicon as an active layer material have a high mobility and an on current, and thus are used in an active matrix LCD (hereinafter referred to as "AMLCD"). It is widely used.

In order to realize a large-area polysilicon TFT LCD technology, not only the unit processes such as laser crystallization technology, gate oxide film deposition technology, and ion doping implantation technology but also high contrast are required to stabilize the leakage current of the TFT. In particular, polysilicon TFTs have a lot of problems to be applied as a switching device of a real pixel because the leakage current is very large despite high mobility and on current. As the main mechanism of the leakage current of such polysilicon TFTs, it is known that a strong electric field is formed near the drain, which causes the release of free electrons. In order to suppress the formation of a strong electric field in the drain, an off-set gate structure, a lightly doped drain (LDD) structure, a multi-gate structure, and the like have been proposed. The trend is to employ an offset structure. Since the offset or LDD structure must be formed in a self-aligned manner to minimize degradation of image quality due to parasitic capacitance, much research has been conducted on this.

1A to 1C are cross-sectional views for explaining a method of forming a self-aligned offset structure of a top gate type TFT.

Referring to FIG. 1A, amorphous silicon is deposited on a light transmissive substrate 2 made of glass or quartz, for example, at a low temperature of about 350 ° C. using a plasma enhanced chemical vapor deposition (PECVD) method. After depositing a predetermined thickness, the deposited amorphous silicon film is crystallized by a conventional method, and then patterned by a photolithography process to form a semiconductor film 4.

Subsequently, an oxide film having a predetermined thickness is deposited on the resultant on which the semiconductor film 4 is formed, for example, by using a PECVD method to form a gate insulating film 6, and as a gate electrode material on the gate insulating film 6, for example, aluminum. After depositing (Al) (8), the deposited aluminum film is anodized to form a first anodized film 10 on the surface of the aluminum film.

Referring to FIG. 1B, a photoresist is applied on a resultant on which the first anodization film 10 is formed, a photoresist pattern 12 is formed through mask exposure and development, and then the photoresist pattern 12 is masked. The first anodic oxide film 10 and the aluminum film 8 are patterned by using. Next, the exposed side of the aluminum film 8 is anodized to form a second anodized film 14.

Referring to FIG. 1C, after the photoresist pattern is removed, additional anodization is performed to secure an appropriate offset length to form a final anodization film 15 that completely encloses the gate. Subsequently, an N-type impurity such as phosphorus (P) is injected into the semiconductor layer 4 to form a source 4a / drain 4b spaced apart from the aluminum gate 8 by a predetermined distance. The thickness of the anodization film 15 formed on the side surface of the aluminum gate 8 is the offset length. Subsequent processes proceed in the same manner as a conventional polysilicon TFT manufacturing process.

The conventional method described above has the disadvantage of requiring two to three anodization processes, which increases the processing time and adds a mask.

2A to 2E are cross-sectional views illustrating a method of forming a self-aligned offset structure of a bottom gate type TFT.

Referring to FIG. 2A, a gate electrode 22 is formed by depositing a metal such as aluminum (Al) or an aluminum alloy on a light transmissive substrate 20 such as glass, and then patterning the deposited metal film.

Referring to FIG. 2B, a gate insulating film 24 is formed by stacking, for example, a nitride film, an oxide film, or a composite film of a nitride film and an oxide film on the resultant product on which the gate electrode 22 is formed. Subsequently, an amorphous silicon and an amorphous silicon doped with impurities are sequentially deposited on the gate insulating layer 24 to form a semiconductor film 26 to be used as an active layer.

Referring to FIG. 2C, an oxide film is formed on the semiconductor layer 26, and then patterned to form an etching stopper 28. Then, the etching stop layer is used as an ion implantation mask to the resultant. The semiconductor film 26 is doped by implanting impurity ions at low concentration.

Referring to FIG. 2D, after the photoresist is coated on the resultant, a mask exposure and development are performed to form a photoresist pattern 30 covering the channel region and the low concentration source / drain region, and then the photoresist pattern 30. By implanting a high concentration of impurity ions using the ion implantation mask, a high concentration source / drain 26a spaced from the gate electrode 22 by a predetermined distance is formed.

Referring to FIG. 2E, a silicon nitride film (SiNx) is deposited on the resultant to form an interlayer insulating film 32, and then the interlayer insulating film 32 is selectively etched to form a high concentration source / drain 26a. To form a contact hole exposing Next, after depositing aluminum (Al) as an electrode material on the resultant formed contact hole, the deposited aluminum film is patterned and then annealed at a temperature of 400 ° C. for about 30 minutes to form the source electrode / drain electrode 34. . Thereafter, the process of forming the protective film 36 and the pixel electrode 38 proceeds in the same manner as in the normal polysilicon TFT manufacturing process.

As mentioned, the conventional method requires two ion implantation processes to form LDD, which makes the process complicated and high production cost. In addition, at least 0.5 μm or more of misalignment is inevitable in forming the photoresist pattern for defining the source / drain region.

Accordingly, the technical problem to be achieved by the present invention is to provide a method of manufacturing a thin film transistor having a self-aligned offset structure without the addition of a process. Another object of the present invention is to provide a method of manufacturing a liquid crystal display device employing the thin film transistor.

1A to 1C are cross-sectional views for explaining a method of forming a self-aligned offset structure of a top gate type TFT.

2A to 2E are cross-sectional views illustrating a method of forming a self-aligned offset structure of a bottom gate type TFT.

3 is a simplified plan view for manufacturing a thin film transistor-liquid crystal display device according to the present invention.

4A through 4F are cross-sectional views illustrating a method of manufacturing a thin film transistor-liquid crystal display device according to the present invention, according to a process sequence.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor having a self-aligned offset structure, the method including: forming a gate electrode on a substrate and conductive layer patterns spaced a predetermined distance from the gate electrode; Sequentially forming a gate insulating film and a semiconductor film on the resultant material; Forming an insulating film pattern on the resultant product to open a portion where the gate electrode and the conductive film pattern are formed; Implanting impurity ions into the semiconductor layer using the insulating layer pattern as a mask to form a source / drain region; After forming an insulating film on the resultant, forming a contact hole exposing a portion of the source region and the drain region; And forming a source electrode / drain electrode connected to the source region / drain region through the contact hole.

In the present invention, the conductive film patterns may be formed to be spaced apart from the gate electrode by the length of an offset region, and one of the conductive film patterns may be used as a storage capacitor electrode.

The forming of the insulating layer pattern may include forming an insulating layer on the resultant semiconductor layer, forming a photoresist layer by applying photoresist on the insulating layer, exposing and developing the photoresist layer, and forming a gate electrode and It is preferable to form a photoresist pattern for opening a portion where the conductive film pattern is formed, and patterning the insulating film using the photoresist pattern as a mask. In this case, it is preferable that the photoresist pattern is formed using a negative photoresist and exposed by back exposure to irradiate light from the substrate.

The insulating film pattern is preferably formed of an oxide film or a nitride film.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including: forming a gate electrode on a substrate and a conductive film pattern spaced apart from the gate electrode by a predetermined distance; Sequentially forming a gate insulating film and a semiconductor film on the resultant material; Forming an insulating film pattern on the resultant product to open a portion where the gate electrode and the conductive film pattern are formed; Implanting impurity ions into the semiconductor film using the insulating film pattern as a mask to form a source region / drain region; After forming an insulating film on the resultant, forming a contact hole exposing a portion of the source region and the drain region; Forming a source electrode / drain electrode connected to the source region / drain region through the contact hole; Forming a via layer exposing a portion of the drain electrode after forming a passivation layer on the resultant material; And forming a transparent conductive film on the resultant, and then patterning the transparent conductive film to form a pixel electrode connected to the drain electrode.

According to the present invention, a fully self-aligned offset structure can be realized by forming a mask layer for forming an offset region on both sides of the gate electrode and employing back exposure using a negative photoresist. This can simplify the process compared to the upper gate type TFT manufacturing process using the conventional anodization process, can prevent misalignment compared to the lower gate type TFT manufacturing process using the conventional photo process, and prevent ion implantation. There is an advantage that can be realized with low energy.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a simplified plan view for manufacturing a thin film transistor-liquid crystal display device according to the present invention.

Reference numeral "P1" denotes a mask pattern for forming a gate line, "P2" denotes a mask pattern for forming a storage capacitor electrode, "P3" denotes a mask pattern for defining an offset region, and "P4" denotes A mask pattern for forming a semiconductor film pattern, " P5 " for forming a contact hole for connecting a source / drain region and an electrode, and " P6 " for forming a metal wiring layer such as a source / drain electrode, etc. And a mask pattern for forming a via hole for connecting the drain electrode and the pixel electrode, respectively.

Referring to FIG. 3, the storage capacitor electrode P2 and the conductive film pattern P3 are laid out to be spaced apart from the gate line P3 by the length of the offset region. The conductive layer pattern P3 is a pattern for forming the offset region in a self-aligned manner, and the conductive layer pattern P3 is formed simultaneously with the gate line P1 and the storage capacitor electrode P2. Thus, no further photographic process for defining the offset area is required.

4A through 4F are cross-sectional views illustrating a method of manufacturing a liquid crystal display using a thin film transistor having a self-aligned offset structure according to the present invention.

Referring to FIG. 4A, after depositing a metal such as aluminum or an aluminum alloy on the transparent substrate 40, patterning the deposited metal film by performing a photolithography process using the mask patterns P1, P2, and P3 of FIG. 3. As a result, the gate electrode 42, the storage capacitor electrode 43, and the conductive film pattern 44 are formed. In this case, as illustrated, the storage capacitor electrode 43 and the conductive film pattern 44 are formed to be spaced apart from the gate electrode 42 by the length of the offset region.

Referring to FIG. 4B, a gate insulating film 46 is formed by depositing, for example, an oxide film or a double film of an oxide film and a nitride film on the entire surface of the resultant product. Subsequently, an amorphous silicon film is deposited on the gate insulating film 46 by using plasma enhanced CVD (PECVD) or LPCVD method, and then the amorphous silicon film is crystallized by irradiating a laser of a predetermined pulse. Let's do it. Next, a photolithography process using the mask pattern P4 of FIG. 3 is performed to pattern the crystallized amorphous silicon film to form a semiconductor film 48 to be used as an active layer of the TFT.

Referring to FIG. 4C, an insulating film 50 is formed by depositing an oxide film or a nitride film on the entire surface of the product on which the semiconductor film 48 is formed. The insulating film 50 is used as an ion implantation mask during ion implantation for forming a source / drain region to be subsequently formed to prevent impurities from being injected into the offset region. Subsequently, a photoresist is applied to the entire surface of the resultant in which the insulating film 50 is formed. In this case, a negative photoresist is used as the photoresist, in which non-exposed portions are removed during development.

Next, exposure and development are performed on the coated photoresist film, and as shown, back exposure is performed to irradiate light from the rear surface of the substrate 40. In this case, light does not pass through the portion where the gate electrode 42, the storage capacitor electrode 43, and the conductive film pattern 44 are formed, and light passes through only the other portion. When the exposed photoresist film is developed, a portion of the gate electrode 42, the storage capacitor electrode 43, and the conductive film pattern 44 is opened as shown in the figure, that is, the shape covering the offset region. The photoresist pattern 52 is formed.

Referring to FIG. 4D, the insulating layer pattern 50a is formed by anisotropically etching the insulating layer using the photoresist pattern 52 as a mask. The insulating layer pattern 50a is formed in a shape in which a portion where the gate electrode 42, the storage capacitor electrode 43, and the conductive layer pattern 44 are formed is opened.

Referring to FIG. 4E, the source / drain region 48a is formed by implanting impurity ions at a high concentration into the resultant product in which the insulating film pattern 50a is formed. At this time, the offset region is masked by the insulating film pattern 50a so that impurity ions are not implanted. Unexplained reference numeral 54 denotes a material layer used as a mask for ion implantation for forming a high concentration (N ⁺ ) source / drain, and the material layer (not shown) in the semiconductor film 48 on the gate electrode 42. The area masked by 54 becomes a channel of the TFT.

Referring to FIG. 4F, after removing the material layer, an insulating material is deposited on the entire surface of the resultant to form an interlayer insulating film 56. Subsequently, by applying the photolithography process using the mask pattern P5 of FIG. 3, the interlayer insulating layer 56 is partially etched to form a contact hole exposing the source / drain 48a. As a result, a metal film is formed on the water. The metal film is patterned using the mask pattern P6 of 3 to form a source electrode / drain electrode 58.

Next, a protective film 60 is formed by depositing, for example, a nitride film on the entire surface of the resultant source / drain electrode 58, and then patterning the protective film 60 to expose a portion of the drain electrode 58. The pixel electrode 62 connected to the drain electrode 58 is formed by depositing and patterning a transparent conductive film such as indium tin oxide (ITO) on the entire surface of the resultant. This completes a TFT-LCD having an offset region of a predetermined length on both sides of the gate electrode 42.

Although the present invention has been described in detail above, the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea to which the present invention pertains.

According to the above-described thin film transistor having a self-aligned offset structure according to the present invention and a method of manufacturing a liquid crystal display device using the same, an ion implantation mask is formed on a semiconductor film at a portion where an offset region is to be formed by employing a back exposure using a negative photoresist. By forming the layer, a fully self-aligned offset structure can be realized without the addition of a mask. This can simplify the process compared to the upper gate type TFT manufacturing process using the conventional anodizing process, and prevents misalignment compared to the lower gate type TFT manufacturing process using the conventional photo process to secure accurate offset length. There is an advantage to this. In addition, since ion implantation is performed as it is without any other material layer on the semiconductor film, ion implantation can be realized with low energy.

Claims (5)

Forming a gate electrode on the substrate and conductive film patterns spaced a predetermined distance from both sides of the gate electrode; Sequentially forming a gate insulating film and a semiconductor film on the resultant material; Forming an insulating film for a mask covering the resultant product; Applying a negative photoresist on the insulating film; Back exposing the negative photoresist from a rear surface of the substrate to form a photoresist pattern for opening a portion where the gate electrode and the conductive layer patterns are formed; Patterning the insulating film for a mask using the photoresist pattern; Implanting impurity ions into the semiconductor film using the mask insulating film; Forming an insulating film on the resultant, and forming a contact hole exposing a portion of the source and the drain; And And forming a source electrode / drain electrode connected to the source / drain via the contact hole. The method of claim 1, wherein the conductive film pattern, A method of manufacturing a thin film transistor having a self-aligned offset structure, characterized in that formed to be spaced apart from the gate electrode by the length of the offset region. The method of claim 1, wherein one of the conductive film pattern, A method of manufacturing a thin film transistor having a self-aligned offset structure, characterized in that it is used as a storage capacitor electrode. The insulating film for a mask according to claim 1, A method of manufacturing a thin film transistor having a self-aligned offset structure, characterized in that it is formed of an oxide film or a nitride film. Forming a gate electrode on the substrate and a conductive film pattern spaced apart from the gate electrode by a predetermined distance; Sequentially forming a gate insulating film and a semiconductor film on the resultant material; Forming an insulating film for a mask covering the resultant product; Applying a negative photoresist on the insulating film; Back exposing the negative photoresist from a rear surface of the substrate to form a photoresist pattern for opening a portion where the gate electrode and the conductive layer patterns are formed; Patterning the insulating film for a mask using the photoresist pattern; Implanting impurity ions into the semiconductor film using the mask insulating film; After forming an insulating film on the resultant, forming a contact hole exposing a portion of the source and drain; Forming a source electrode / drain electrode connected to the source / drain through the contact hole; Forming a via layer exposing a portion of the drain electrode after forming a passivation layer on the resultant material; And And forming a transparent conductive film on the resultant material and then patterning the transparent conductive film to form a pixel electrode connected to the drain electrode.

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