KR100263165B1 - Video mode detector - Google Patents

Abstract

The discrimination apparatus disclosed is for discriminating the video mode of an image signal input from a computer system with hardware of a simple configuration.

The present invention is to count the number of horizontal sync signals in a period of the vertical sync signal by using the frequency of the vertical sync signal and the horizontal sync signal different from the computer system according to the video mode, and determine the video mode by the count value. The negative count unit counts the number of clocks of the horizontal synchronizing signal during the high potential period of the vertical synchronizing signal, and the positive count unit counts the number of clocks of the horizontal synchronizing signal during the low potential period of the vertical synchronizing signal; After comparing the count value of the count unit and the count value of the positive count unit, the video mode is determined by comparing the larger value among them with a pre-stored reference value, and outputting a mode control signal according to the determined video mode to operate the video display device. To control.

Description

Video mode determination device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a video mode determination device for determining a video mode of a video signal output from a video card of a computer system in a video display device such as a monitor connected to a computer system such as a personal computer and used as a screen display device. .

In general, an image display device such as a monitor allows a user to simply monitor and confirm an operation state of a computer system.

The computer system incorporates a video card to output a predetermined video signal according to an operation currently performed by the computer system, and the video display device inputs and displays a predetermined video signal output from the computer system on the screen.

In order for a video display device to display a predetermined video signal output from a video card of a computer system, a vertical sync signal and a horizontal sync signal that the computer system outputs along with a predetermined video signal to be displayed on the video display device must be used. do.

The frequencies of the horizontal synchronizing signal and the vertical synchronizing signal output from the computer system to the image display device differ depending on the video mode.

For example, the VGA compatible video graphic array (VGA) mode having a resolution of 640 x 480 has a frequency of 31.47 KHz and a 60 Hz vertical sync signal.

In addition, the SVGA (Super Video Graphic Array) mode, which has an 800-by-600 resolution of VESA type, is 37.88KHz for horizontal sync signal and 60Hz for vertical sync signal.

In the XGA mode, the horizontal synchronization signal has a frequency of 48.36 KHz and the vertical synchronization signal has a frequency of 60 Hz.

In addition to the video modes described above, there are various video modes, and the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal differ according to these video modes.

The user may operate and set the image display device according to the video mode of the image signal output from the computer system.

However, setting the video mode of the video display device causes a lot of inconvenience and inconvenience for the user.

In addition, users who lack the knowledge of the video mode did not correctly set the video mode of the video display device according to the video mode of the video signal output from the computer system.

Therefore, it is preferable to automatically set the video mode of the video display device according to the video mode of the video signal output from the video card of the computer system.

In order to determine the video mode of the video signal output from the video card of the computer system, conventionally, the frequency of the horizontal sync signal and the vertical sync signal output together with the video signal from the video card is measured, and the corresponding operation mode is determined based on the measured frequency. An operation according to the determined operation mode is performed.

Conventional techniques for determining the video mode use software or hardware.

The use of the software is to input a horizontal synchronizing signal and a vertical synchronizing signal input from a computer system to a microcomputer to count frequencies, and determine the video mode by the counted frequencies.

Therefore, using the software has a problem that the production cost of the product is increased by using an expensive microcomputer, and the production of the software is difficult.

The hardware is used to input a horizontal sync signal and a vertical sync signal from a computer system to a frequency / voltage converter, convert the voltage into a voltage, input the converted voltage to a plurality of comparators, and determine a video mode. The switching element is controlled accordingly to perform the operation corresponding to the video mode determined by each part of the circuit.

In addition, since the polarity of the horizontal synchronizing signal and the vertical synchronizing signal inputted from the computer system are different, the use of hardware includes a separate polarity discriminating unit for determining the polarity of the horizontal synchronizing signal and the vertical synchronizing signal.

Therefore, using the hardware described above has a problem in that the circuit configuration is very complicated and many parts are difficult to manufacture.

Accordingly, an object of the present invention is to provide a video mode discrimination apparatus for discriminating a video mode of an image signal input from a computer system with hardware having a simple configuration.

1 is a circuit diagram showing the configuration of the discriminating apparatus of the present invention;

2A to 2G are operation waveform diagrams of each part of FIG. 1 even in VGA mode;

3A to 3G are operation waveform diagrams of respective parts of FIG. 1 in the SVGA mode.

* Explanation of symbols for main parts of the drawings

100: horizontal synchronizing signal counting unit 110: negative polarity counting unit

111: first counter 112: first register

120: positive count unit 121: second counter

122: second register 200: mode detector

VSYNC: Vertical Sync Signal HSYNC: Horizontal Sync Signal

In order to achieve the above object, the video mode discriminating apparatus of the present invention uses a different frequency of the vertical synchronizing signal and the horizontal synchronizing signal according to the video mode. Determine.

In some video modes, the number of clocks of the horizontal sync signal may be the same during the vertical sync signal period.

For example, a video mode having a resolution of 640x480 in an IBM compatible model and a video mode having a resolution of 640x480 in a Macintosh compatible model has a clock count of 525 horizontal sync signals during the vertical sync signal period.

However, the video mode with 640 × 480 resolution in IBM compatible model has 523 horizontal sync signals during the high potential period of vertical sync signal, and the video mode with 640 × 480 resolution in Macintosh compatible model is used for vertical sync signal. During the high potential period, the number of clocks of the horizontal synchronization signal is different from 522.

In addition, the polarity of the vertical synchronizing signal and the horizontal synchronizing signal is not constant, and differs depending on the video mode.

Therefore, according to the video mode determination apparatus of the present invention, the video counter is determined by counting the number of clocks of the horizontal synchronization signal during the high potential period and the low potential period of the vertical synchronization signal inputted from the computer system. The number of clocks of the horizontal synchronizing signal is counted during the high potential period of the synchronizing signal, and the second counter counts the number of clocks of the horizontal synchronizing signal during the low potential period of the vertical synchronizing signal, so that the counted values are first and second, respectively. Registers are stored and output.

The mode detecting unit compares the values output by the first and second registers, compares a larger value among them with a preset reference value, determines a video mode, and outputs a control signal according to the determined video mode to display the image display device. Control the operation.

Hereinafter, a video mode determination apparatus of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing the configuration of the discriminating apparatus of the present invention.

Here, reference numeral 100 denotes a counting unit for counting the number of clocks of the horizontal synchronization signal HSYNC during the high potential period and the low potential period of the vertical synchronization signal VSYNC input from a computer system (not shown in the figure), Reference numeral 200 stores a reference value according to each video mode in advance, compares the counted value with the counted value during the low potential period during the high potential period, and compares the larger value with the pre-stored reference value. It is a mode detection part to judge.

The horizontal sync signal counting unit 100 counts the number of clocks of the horizontal sync signal HSYNC during the high potential period of the vertical sync signal VSYNC, and outputs the counted value to the mode detector 200. And a positive counting unit 120 for counting the number of clocks of the horizontal synchronizing signal HSYNC during the low potential period of the vertical synchronizing signal VSYNC and outputting the counted value to the mode detecting unit 200. Is done.

The negative counting unit 110 is enabled by the high potential vertical synchronizing signal VSYNC, and includes a first counter 111 for counting the number of clocks of the horizontal synchronizing signal HSYNC, and a low potential vertical synchronizing signal. And a first register 112 for storing the output signal of the first counter 111 by the VSYNC and outputting the output signal to the mode detector 200.

The positive counting unit 120 is enabled by a low potential vertical synchronizing signal VSYNC, and a second counter 121 for counting the number of clocks of the horizontal synchronizing signal HSYNC, and a high potential vertical synchronizing signal. And a second register 122 for storing the output signal of the second counter 121 by the VSYNC and outputting the output signal to the mode detector 200.

In the drawing description of FIG. 1, reference numeral EN1 is an enable terminal enabled when the vertical sync signal VSYNC is at high potential, and / EN2 is enabled when the vertical sync signal VSYNC is at a low potential. Terminal, CK1 and CK4 are clock terminals operating in the rising edge of the horizontal synchronization signal HSYNC, and / CK2 and / CK3 are clock terminals operating in the falling edge of the horizontal synchronization signal HSYNC. It is a terminal.

And D1 and D2 are input terminals of the first and second registers 112 and 122.

The video mode determination apparatus of the present invention configured as described above will be described by taking an example of a VGA mode having a resolution of 640 × 480 in the IBM method and an SVGA mode having a resolution of 800 × 600 in the VESA method.

1. VGA mode with 640 × 480 resolution using IBM method

In the IBM mode, the VGA mode having a resolution of 640 × 480 has a frequency of 31.47 KHz, a frequency of 60 Hz, and a pixel frequency of 25.18 MHz.

The polarity of the vertical synchronizing signal and the horizontal synchronizing signal is negative.

When the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC having negative polarity are input from the computer system as shown in Figs. 2A and 2B, the second counter 121 during the low potential period of the vertical synchronizing signal VSYNC. Is enabled, the second counter 121 counts the number of clocks of the horizontal synchronization signal HSYNC during the low potential period of the vertical synchronization signal VSYNC, as shown in FIG. 2C.

In this state, when the vertical synchronization signal VSYNC is switched to the high potential, the second counter 121 is not enabled and the counting operation is stopped.

In addition, since the high potential vertical synchronizing signal VSYNC is applied to the clock terminal CK4 of the second register 122 as a clock signal, the second register 122 operates to '2' which is a count value of the second counter 121. 'Is stored as shown in FIG. 2D and output to the mode detector 200.

Since the first counter 111 is enabled as the vertical synchronization signal VSYNC is switched to the high potential, the first counter 111 clocks the horizontal synchronization signal HSYNC during the high potential period of the vertical synchronization signal VSYNC. The number is counted as shown in FIG. 2E.

When the vertical synchronizing signal VSYNC is switched to the low potential in this state, the first counter 111 is not enabled and the counting operation is stopped.

In addition, since the low potential vertical synchronizing signal VSYNC is applied to the clock terminal / CK3 of the first register 112 as a clock signal, the second register 112 operates to form a count value of the first counter 111. 523 'is stored as shown in FIG. 2F and outputted to the mode detector 200.

Then, the mode detection unit 200 stores in advance the signal having the larger value among the output signals of the first register 112 and the second register 122, that is, the output signal of the first register 112 in accordance with the video mode. Compared with the reference value, it is determined that the video mode is a VGA mode having a resolution of 640x480 by the IBM method as shown in FIG. 2G, and outputs a mode determination signal.

2. SVGA mode with 800 × 600 resolution by VESA

In the SVGA mode having a resolution of 800 × 600 in the VESA method, the frequency of the horizontal synchronization signal is 37.88 KHz, the frequency of the vertical synchronization signal is 60 Hz, and the pixel frequency is 40 MHz.

The polarity of the vertical synchronizing signal and the horizontal synchronizing signal is positive.

When the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC having positive polarity are input from the computer system as shown in Figs. 3A and 3B, the first counter 111 during the high potential period of the vertical synchronizing signal VSYNC. Is enabled, the first counter 111 counts the number of clocks of the horizontal synchronization signal HSYNC during the high potential period of the vertical synchronization signal VSYNC, as shown in FIG. 3E.

In this state, when the vertical synchronization signal VSYNC is switched to the low potential, the first counter 111 is not enabled and the counting operation is stopped.

In addition, since the low potential vertical synchronizing signal VSYNC is applied to the clock terminal / CK3 of the first register 112 as a clock signal, the first register 112 is operated so that the count value of the first counter 111 is'. 4 'is stored as shown in FIG. 2F and output to the mode detector 200.

Since the second counter 121 is enabled as the vertical synchronizing signal VSYNC is switched to the low potential, the second counter l21 clocks the horizontal synchronizing signal HSYNC during the low potential period of the vertical synchronizing signal VSYNC. The number is counted as shown in FIG. 3C.

In this state, when the vertical synchronizing signal VSYNC is switched to the high potential again, the second counter 121 is not enabled and the counting operation is stopped.

In addition, since the high potential vertical synchronizing signal VSYNC is applied to the clock terminal CK4 of the second register 122 as a clock signal, the second register 122 operates to '624, which is a count value of the second counter 121. 'Is stored as shown in FIG. 3D and output to the mode detector 200.

Then, the mode detection unit 200 stores in advance the signal of the larger value among the output signals of the first register 112 and the second register 122, that is, the output signal of the second register 122 in accordance with the video mode. Compared with the reference value, it is determined that the video mode is the SVGA mode having a resolution of 800x600 by the VESA method as shown in FIG. 3G, and outputs a mode determination signal.

As described above, the present invention is to determine the video mode by counting the number of clocks of the horizontal synchronizing signal during the vertical synchronizing signal inputted from the computer system. This can be produced easily and inexpensively.

Claims (4)

A counting unit for counting the number of clocks of the horizontal synchronization signal during the high potential period and the low potential period of the vertical synchronization signal input from the computer system; And And a mode detector which compares the counted value during the high potential period and the counted value during the low potential period, and compares the larger value with a pre-stored reference value to determine a video mode. According to claim 1, The counting unit; A negative counting unit for counting the number of clocks of the horizontal synchronizing signal during the high potential period of the vertical synchronizing signal inputted from the computer system and outputting the counted value to the mode detecting unit; And And a positive polarity counting unit for counting the number of clocks of the horizontal synchronizing signal during the low potential period of the vertical synchronizing signal input from the computer system and outputting the counted value to the mode detecting unit. The display device of claim 2, wherein the negative count unit comprises: a negative count unit; A first counter enabled by the high potential vertical synchronization signal to count the number of clocks of the horizontal synchronization signal; And And a first register for storing the output signal of the first counter and outputting the output signal of the first counter to the mode detector by a low potential vertical synchronizing signal. The battery pack of claim 2, wherein the positive count unit comprises: a positive count unit; A second counter enabled by the low potential vertical synchronizing signal to count the number of clocks of the horizontal synchronizing signal; And And a second register configured to store and output the output signal of the second counter to the mode detector by a high potential vertical synchronization signal.

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