KR100261963B1 - Manufacturing method of triple well of semiconductor device - Google Patents
Manufacturing method of triple well of semiconductor device Download PDFInfo
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- KR100261963B1 KR100261963B1 KR1019970077378A KR19970077378A KR100261963B1 KR 100261963 B1 KR100261963 B1 KR 100261963B1 KR 1019970077378 A KR1019970077378 A KR 1019970077378A KR 19970077378 A KR19970077378 A KR 19970077378A KR 100261963 B1 KR100261963 B1 KR 100261963B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000007943 implant Substances 0.000 claims description 75
- 238000005468 ion implantation Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 28
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 18
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 229910015900 BF3 Inorganic materials 0.000 claims description 10
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 4
- 238000002955 isolation Methods 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 102000004310 Ion Channels Human genes 0.000 description 1
- 108090000862 Ion Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0191—Manufacturing their doped wells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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Abstract
본 발명은 반도체소자의 3중웰 형성방법에 관한 것으로, 피형 반도체기판에 소자분리 영역을 형성한 다음 베리드(buried) n-well을 형성하고, n-well, p-well, 및 p-well-2를 각각의 마스크를 사용하여 형성함으로써 웰 바이어스(bias)를 다르게 사용할 수 있는 두 가지의 엔모스(NMOS)를 형성할 수 있고, 각각의 마스크를 사용하여 웰을 형성함으로써 각 소자의 특성에 맞는 도핑농도를 갖는 3중웰을 형성하여 각 소자의 문턱전압 및 펀치쓰루(punch through) 특성 조절을 용이하게 하고, 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming triple wells of semiconductor devices, wherein device isolation regions are formed on a semiconductor substrate, and buried n-wells are formed, and n-well, p-well, and p-well- Two masks can be formed using each mask to form two NMOSs that can use different well biases. The wells can be formed using the respective masks to match the characteristics of each device. By forming a triple well having a doping concentration, it is easy to adjust the threshold voltage and punch through characteristics of each device, and thereby improve the characteristics and reliability of the semiconductor device.
Description
본 발명은 반도체소자의 3중웰 형성방법에 관한 것으로, 특히 원하는 도핑 농도를 갖고 독립적으로 동작하는 3가지의 웰을 형성하여 각 소자들의 문턱전압(Vt) 조절이나 펀치쓰루 특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a triple well forming method of a semiconductor device, and more particularly to a technique for improving threshold voltage (Vt) control or punch-through characteristics of each device by forming three wells independently having a desired doping concentration. will be.
일반적으로 DRAM 에서 주변회로는 CMOS가 널리 사용되며, 이러한 CMOS 는 3중웰이 구비된 반도체기판에 형성되는데 3중웰은 종래의 2중웰 구조의 n-well 영역에 또 다른 p-well 영역이 형성된다.In general, CMOS is widely used as a peripheral circuit in a DRAM. Such a CMOS is formed on a semiconductor substrate provided with triple wells, and another p-well region is formed in an n-well region of a conventional double well structure.
도시되어 있지는 않지만 종래기술에 따른 반도체소자의 3중 웰 형성방법을 설명하면 다음과 같다.Although not shown, a triple well forming method of a semiconductor device according to the prior art will be described.
먼저, 반도체기판 상부에 패드산화막, 질화막 및 제1감광막을 순차적으로 형성하고, 소자분리 마스크를 이용한 식각공정으로 소자분리 산화막을 형성한다.First, a pad oxide film, a nitride film, and a first photoresist film are sequentially formed on the semiconductor substrate, and a device isolation oxide film is formed by an etching process using an device isolation mask.
그 다음, n-well 마스크를 사용한 n-well 임플란트 공정과, 피-채널 스톱 임플란트를 실시한다.Next, an n-well implant process using an n-well mask and a P-channel stop implant are performed.
그 다음, p-well 마스크를 사용하여 p-well 임플란트 공정과, 엔-채널 스톱 임플란트와 엔-채널 Vt 임플란트를 연속적으로 실시하여 반도체소자의 3중 웰을 형성한다. 여기서, 상기 p-well 임플란트 공정시 상기 n-well 내부에 또 하나의 p-well이 형성되는데, 이를 p-well-2라 한다.Then, a p-well implant process and an n-channel stop implant and an n-channel Vt implant are successively performed using a p-well mask to form a triple well of a semiconductor device. Here, another p-well is formed inside the n-well during the p-well implant process, which is called p-well-2.
상기와 같이 종래기술에 따른 반도체소자의 3중웰 형성방법은, 반도체기판에 n-well을 형성한 다음에, p-well과 n-well 내부의 p-well-2를 동시에 형성하는데, 상기와 같은 형성방법은 p-well-2의 도핑농도를 원하는 데로 형성하기 어렵고, 또한 소자가 작아짐에 따라 취약해지는 펀치쓰루 특성을 보완하기 위하여 웰의 농도를 높여야 하는데 n-well의 농도를 높이는 동시에 상기 n-well 내부에 있는 p-well-2의 농도까지 높이기 어렵기 때문에 p-well-2의 펀치쓰루 특성이 약해지며, 문턱전압을 조절하기 위한 엔-채널 Vt 임플란트와 블랭켓 Vt 임플란트로 세가지 타입 소자의 문턱전압을 조절하기가 어려운 문제점이 있다.As described above, the triple well forming method of a semiconductor device according to the related art forms an n-well on a semiconductor substrate and then simultaneously forms a p-well and p-well-2 inside the n-well. Forming method is difficult to form the doping concentration of p-well-2, and also to increase the concentration of the well to compensate for the punch-through characteristics that become weak as the device becomes smaller, while increasing the concentration of the n-well and the n- Because it is difficult to increase the concentration of p-well-2 in the well, the punch-through characteristic of p-well-2 is weakened, and the N-channel Vt implant and the blanket Vt implant for adjusting the threshold voltage are used to There is a problem that it is difficult to adjust the threshold voltage.
본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, 피형 반도체기판을 사용하여 소자를 형성하는 경우에 엔형의 불순물을 높은 에너지로 이온주입하여 베리드 n-well을 형성하고, n-well 마스크, p-well 마스크 및 p-well-2 마스크를 사용하여 각 웰의 도핑농도를 원하는 대로 조절하면서 형성함으로써 각 소자의 문턱전압 조절이나 펀치쓰루 특성을 향상시키는 반도체소자의 3중웰 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the related art, the present invention provides a buried n-well by implanting impurities of high-energy with high energy when forming a device using a semiconductor substrate, and forming an n-well mask, By using a p-well mask and a p-well-2 mask to control the doping concentration of each well as desired to provide a triple well forming method of a semiconductor device to improve the threshold voltage and punch-through characteristics of each device. There is a purpose.
도 1a 내지 도 1e 는 본 발명의 제1실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method of forming a triple well of a semiconductor device according to a first embodiment of the present invention.
도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of forming a triple well of a semiconductor device according to a second embodiment of the present invention.
◈ 도면의 주요부분에 대한 부호의 설명 ◈◈ Explanation of Codes for Main Parts of Drawing
11, 12 : 실리콘기판 13, 14 : 필드산화막11, 12:
15, 16 : 베리드 n-well 17, 18 : 제2감광막15, 16: buried n-well 17, 18: the second photosensitive film
19, 20 : n-well 임플란트 영역 21, 22 : 인터 n-well 임플란트 영역19, 20: n-well implant region 21, 22: inter n-well implant region
23, 24 : 피-채널 스톱 임플란트 영역23, 24: P-channel stop implant area
25, 26 : 피-채널 Vt 임플란트 영역25, 26: P-channel Vt implant region
27, 50 : 제3감광막 28, 37 : 제4감광막27, 50: third
29, 30 : p-well 임플란트 영역 31, 32 : 인터 p-well 임플란트 영역29, 30: p-well implant region 31, 32: inter p-well implant region
33, 34 : 엔-채널 스톱 임플란트 영역 35, 36 : 엔-채널 Vt 임플란트 영역33, 34: N-channel stop implant area 35, 36: N-channel Vt implant area
38 : 제5감광막 39, 40 : p-well-2 임플란트 영역38: fifth
41, 42 : 인터 p-well-2 임플란트 영역41, 42: inter p-well-2 implant area
43, 44 : 엔-채널-2 스톱 임플란트 영역43, 44: N-channel-2 stop implant area
45, 46 : 엔-채널-2 Vt 임플란트 영역45, 46: N-channel-2 Vt implant region
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 3중웰 형성방법은,The triple well forming method of a semiconductor device according to the present invention for achieving the above object,
필드 산화막이 형성되어 있는 피형 반도체기판에 n-well 로 정의된 부분보다 좁고, p-well-2로 정의된 부분보다는 넓게 형성하되, n-well 을 연결시켜주고 p-well 과 p-well-2가 서로 분리되도록 하는 베리드 n-well을 형성하는 공정과,On the semiconductor substrate where the field oxide film is formed, it is narrower than the part defined as n-well and wider than the part defined as p-well-2, and the n-well is connected and p-well and p-well-2 are formed. Forming buried n-wells to separate the
상기 구조 상부에 n-well을 형성하는 공정과,Forming an n-well on the structure;
상기 구조 상부에 p-well을 형성하는 공정과,Forming a p-well on the structure;
상기 구조 상부에 p-well-2를 형성하는 공정을 포함하는 것을 특징으로 한다.And forming p-well-2 on the structure.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e 는 본 발명의 제1실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a triple well forming method of a semiconductor device according to a first embodiment of the present invention.
먼저, 피형 반도체기판(11) 상부에 패드산화막(도시안됨), 질화막(도시안됨)제1감광막(도시안됨)을 순서대로 형성한 다음에, 소자분리 마스크를 이용하여 소자분리 영역으로 예정된 부분에 필드산화막(13)을 형성하고, 상기 질화막 및 패드산화막을 제거한다.First, a pad oxide film (not shown) and a nitride film (not shown) and a first photoresist film (not shown) are formed in this order on an upper portion of the
이어서, 블랭켓 방법으로 엔형 불순물을 상기 반도체기판(11)에 높은 에너지로 이온주입하여 베리드 n-well(15)을 형성한다. 여기서, 상기 베리드 n-well(15)은 도즈량 1.0 ∼ 3.0E13/㎠ 을 이온주입 에너지 0.5 ∼ 3MeV 로 5가의 불순물 인 또는 비소를 이온주입하여 형성한다.Subsequently, the buried n-well 15 is formed by ion implanting the N-type impurity into the
그런 후에, n-well마스크(17)를 사용하여 n-well 영역으로 예정된 부분에 3 ∼ 5회에 걸쳐서 높은 에너지를 사용한 임플란트 공정을 실시한다.Thereafter, an n-
먼저, 도즈량 5.0E12/㎠ ∼ 5.0E13/㎠ 을 이온주입 에너지 500KeV ∼ 1MeV 로 5가의 불순물인 인을 이온주입하여 n-well 임플란트 영역(19)을 형성한다.First, an n-well implant region 19 is formed by ion implanting phosphorus, which is a pentavalent impurity, at a dose of 5.0E12 /
다음, 도즈량 1.0E12/㎠ ∼ 1..0E13/㎠ 을 이온주입 에너지 100KeV ∼ 700KeV 로 5가의 불순물인 인을 이온주입하여 인터 n-well 임플란트 영역(21)을 형성한다.Next, the inter n-well implant region 21 is formed by ion implanting phosphorus, which is a pentavalent impurity, with a dose amount of 1.0E12 /
다음, 도즈량 1.0E12/㎠ ∼ 1..0E13/㎠ 을 이온주입 에너지 50KeV ∼ 100KeV 로 5가의 불순물인 인 또는 비소를 이온주입하여 피-채널 스톱 임플란트 영역(23)을 형성한다.Next, phosphorus or arsenic which is a pentavalent impurity is ion-implanted at a dose amount of 1.0E12 /
그 다음, 도즈량 1.0E11/㎠ ∼ 5..0E12/㎠ 을 이온주입 에너지 10KeV ∼ 50KeV 로 3가의 불순물인 붕소 또는 불화붕소를 이온주입하여 피-채널 Vt 임플란트 영역(25)을 형성한다.Subsequently, boron or boron fluoride, which is a trivalent impurity, is ion-implanted at a dose amount of 1.0E11 /
그 후, p-well마스크(27)를 사용하여 3 ∼ 5회에 걸쳐서 높은 에너지로 임플란트 공정으로 실시한다.Thereafter, the p-
먼저, 도즈량 1.0 ∼ 5.0E13/㎠ 을 이온주입 에너지 300KeV ∼ 700KeV 로 3가의 불순물인 붕소를 이온주입하여 p-well 임플란트 영역(29)을 형성한다.First, a p-well implant region 29 is formed by ion implanting boron, which is a trivalent impurity, with a dose amount of 1.0 to 5.0E13 /
다음, 도즈량 0.5E13/㎠ ∼ 2..0E13/㎠ 을 이온주입 에너지 100KeV ∼ 400KeV 로 3가의 불순물인 붕소를 이온주입하여 인터 p-well 임플란트 영역(31)을 형성한다.Next, the inter p-well implant region 31 is formed by ion implanting boron, which is a trivalent impurity, at a dose of 0.5E13 /
그 다음, 도즈량 1.0E12/㎠ ∼ 1..0E13/㎠ 을 이온주입 에너지 50KeV ∼ 100KeV 로 3가의 불순물인 붕소 또는 불화붕소를 이온주입하여 엔-채널 스톱 임플란트 영역(33)을 형성한다.Subsequently, boron or boron fluoride, which is a trivalent impurity, is ion-implanted at a dose of 1.0E12 /
그리고, 도즈량 1.0E11/㎠ ∼ 5..0E12/㎠ 을 이온주입 에너지 10KeV ∼ 50KeV 로 3가의 불순물인 붕소 또는 불화붕소를 이온주입하여 엔-채널 Vt 임플란트 영역(35)을 형성한다.Then, the ion-channel Vt implant region 35 is formed by ion implanting boron or boron fluoride, which is a trivalent impurity, at a dose of 1.0E11 /
다음, p-well-2 마스크(37)를 사용하여 p-well-2를 형성한다. 이때, 상기 p-well-2 마스크(37)는 상기 n-well영역 내의 일부분만 노출시키는 형태를 갖는다.Next, p-well-2 is formed using a p-well-2
여기서, 상기 p-well-2 형성공정은 3 ∼ 5회에 걸쳐서 높은 에너지를 사용한 임플란트 공정으로 실시한다.Here, the p-well-2 forming step is performed by an implant step using high energy over three to five times.
먼저, 도즈량 1.0 ∼ 5.0E13/㎠ 을 이온주입 에너지 300KeV ∼ 700KeV 로 3가의 불순물인 붕소를 이온주입하여 p-well-2 임플란트 영역(39)을 형성한다.First, the p-well-2
다음, 도즈량 0.5E13/㎠ ∼ 2..0E13/㎠ 을 이온주입 에너지 100KeV ∼ 400KeV 로 3가의 불순물인 붕소를 이온주입하여 인터 p-well-2 임플란트 영역(41)을 형성한다.Next, the inter p-well-2
그 다음, 도즈량 1.0E12/㎠ ∼ 1..0E13/㎠ 을 이온주입 에너지 50KeV ∼ 100KeV 로 3가의 불순물인 붕소 또는 불화붕소를 이온주입하여 엔-채널-2 스톱 임플란트 영역(43)을 형성한다.Subsequently, boron or boron fluoride, which is a trivalent impurity, is ion-implanted at a dose amount of 1.0E12 /
그리고, 도즈량 1.0E11/㎠ ∼ 5..0E12/㎠ 을 이온주입 에너지 10KeV ∼ 50KeV 로 3가의 불순물인 붕소 또는 불화붕소를 이온주입하여 엔-채널-2 Vt 임플란트 영역(45)을 형성한다.Then, the ion-channel-2
본 발명에 따른 제2실시예를 살펴보면 다음과 같다.Looking at the second embodiment according to the present invention.
도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 3중웰 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a triple well forming method of a semiconductor device according to a second exemplary embodiment of the present invention.
먼저, 소자분리 산화막을 형성하는 단계까지의 공정을 순차적으로 진행한 후, p-well과 p-well-2영역을 분리시키는 베리드 n-well 마스크를 사용하여 엔형 불순물을 상기 반도체기판에 높은 에너지로 이온주입하여 베리드 n-well을 형성하고, 후속 공정으로 n-well, p-well, p-well-2를 형성하여 3중웰을 완성한다.First, the process up to the step of forming a device isolation oxide film is sequentially performed, and high energy is then applied to the semiconductor substrate by using a buried n-well mask that separates p-well and p-well-2 regions. After implantation, the buried n-well is formed, and in the subsequent process, n-well, p-well, and p-well-2 are formed to complete the triple well.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 3중웰 형성방법은, 피형 반도체기판에 소자분리 영역을 형성한 다음 베리드 n-well을 형성하고, n-well, p-well 및 p-well-2를 각각의 마스크를 사용하여 형성함으로써 웰 바이어스(bias)를 다르게 사용할 수 있는 두 가지의 엔모스(NMOS)를 형성할 수 있고, 각각의 마스크를 사용하여 웰을 형성함으로써 각 소자의 특성에 맞는 도핑농도를 갖는 3중웰을 형성하여 각 소자의 문턱전압 및 펀치쓰루(punch through) 특성 조절을 용이하게 하고, 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of forming a triple well of a semiconductor device according to the present invention, a device isolation region is formed on a to-be-shaped semiconductor substrate, and then a buried n-well is formed, and n-well, p-well and p-well- Two masks can be formed using each mask to form two NMOSs that can use different well biases. The wells can be formed using the respective masks to match the characteristics of each device. By forming a triple well having a doping concentration, it is easy to adjust the threshold voltage and punch through characteristics of each device, and thus, there is an advantage of improving the characteristics and reliability of the semiconductor device.
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