KR100258933B1 - Memory Management Device and Method - Google Patents

Abstract

The present invention relates to a memory management apparatus and method, comprising: a memory unit for linking a plurality of memory blocks with each other and assigning a predetermined number to each of the memory blocks; A first register storing a number of one memory block to be indexed among the memory blocks; A second register for storing a number of the last linked memory block of the memory blocks; A third register in which a plurality of pieces of data are processed in parallel and one status bit indicating whether each memory block is in use or not; And a memory block to read and store contents stored in the first and second registers, and determine whether a memory block to be indexed is available by reading the status bits for the memory block in the third register. And a control unit for accessing the memory.

According to the present invention, the number of memory accesses can be reduced by using a vector register having information of status bits containing information of whether a corresponding memory block is available or not.

Description

Memory Management Device and Method

The present invention relates to a memory management apparatus and a method thereof, and more particularly, to a memory management apparatus and method for managing a plurality of equally low-capacity memory blocks using a vector register composed of a plurality of memory elements.

Conventionally, as shown in the memory block diagram of FIG. 1, a status bit is placed in each memory block for a plurality of equally low-capacity memory blocks to determine whether the corresponding memory block is available, unavailable or in use. It was made. This is implemented by reading the contents after accessing the registers with the status bits of each memory block when using a memory block by placing a register not shown in the figure.

In the above-described memory block management, every time a memory block is used, memory access must be performed to check status bits and then traverse other memory blocks, thereby reducing overall system performance including speed problems in the related system. The problem arises.

An object of the present invention is to provide an apparatus and method for managing a memory block which does not require frequent memory access by storing a status bit indicating a usable state of a memory block in a vector register.

1 illustrates a configuration of a conventional memory unit.

2 is a block diagram of a memory management apparatus according to the present invention.

3 is a flowchart of a memory management method according to the present invention.

The memory management apparatus for the above problem comprises: a memory unit for linking a plurality of memory blocks with each other and assigning a predetermined number to each of the memory blocks; A first register storing a number of one memory block to be indexed among the memory blocks; A second register for storing a number of the last linked memory block of the memory blocks; A third register in which a plurality of pieces of data are processed in parallel and one status bit indicating whether each memory block is in use or not; And a memory block to read and store contents stored in the first and second registers, and determine whether a memory block to be indexed is available by reading the status bits for the memory block in the third register. And a control unit for accessing the memory.

For the another object, a first register for storing a memory block number to be indexed among the memory unit to which the plurality of memory blocks are linked to each other, the block number for distinguishing the memory blocks, the number of the last memory block in the memory block A second register for storing, a third register having a plurality of registers, in which a status bit indicating a usage state of the memory block is written for each register, and a control unit for reading the first, second, and third registers, and accessing the memory unit. A memory management method of a system comprising: a first step of initializing the first register and the third register and storing the number of the last memory block of the memory unit in the second register; Reading a status bit of the third register with respect to the memory block number written in the first register if the content of the first register in the first step is less than or equal to the last memory block number of the second register;

A third step of initializing contents of the first register when the contents of the first register in the first stage are larger than the memory block number stored in the second register; A fourth step of determining whether a corresponding memory block is enabled by reading the status bits of the third register of the second step; Calculating a start address of a memory block to be used as a memory block number to be indexed in the first register when the corresponding memory block is enabled in the fourth step; In the fourth step, when the corresponding memory block is in a disabled state or when the use of the memory block ends, the number of the next memory block linked to the memory block is written to the first register, and the third memory block is used for the used memory block. Disabling a status bit of the memory block in a register; And a seventh step of performing the second step again to use another memory block.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a memory management apparatus according to the present invention, and includes a control unit 200, a memory unit 210, a first register 220, a second register 230, and a vector register 240. The controller 200 is a subject that operates and manages a memory, and includes a predetermined algorithm for memory management. The memory unit 210 includes a plurality of memory blocks of the same low capacity, and each of the memory blocks has the same size and is sequentially assigned a memory block number. The first register 220 is a register having a conventional structure, and stores / stores the number of the memory block to be indexed soon among the memory blocks of the memory unit 210. The second register 230 is a conventional data storage register having the same structure as the first register 220 and always stores the number of the last memory block of the memory unit 210. Unlike the general register, the vector register 240 is a register in which a predetermined number of data can be input / output and stored in parallel together, and a register is not permitted to move data between the registers. Unlike the state bits included in the present invention, the vector register 240 includes a state bit indicating whether the memory blocks are in use or not. Therefore, unlike the conventional case in which the control unit 200 directly accesses the memory unit and knows whether to use the memory blocks, the control unit 200 reads only the vector register 240 to know it.

3 is a flowchart illustrating a memory management method according to the present invention. First, in order to use the memory unit 210, the contents of the first register 220 and the vector register 240 are initially initialized to predetermined contents (step 300). In this case, the initialization of the first register 220 and the vector register 240 writes the number of the linked block to the first register to be accessed first among the memory blocks, and writes the vector register to all the registers. The status bit is set to indicate that the memory block is in an enabled state, that is, 'usable'. Thereafter, the second register 230 stores / stores the number of the last memory block of the memory unit 210 (step 310). The size of the contents of the first register 220 and the second register 230 is compared (step 320) to index the first register 220 written in the first register 220 rather than the number of the last memory block recorded in the second register 230. If the number of the memory block is the same or smaller, the vector register 240 including the status bits of the memory block corresponding to the memory block number recorded in the first register 220 is read (step 330). If the memory block number stored in the second register 230 is smaller than the memory block number stored in the first register 220, the contents of the first register 220 are initialized back to the contents of step 300 described above (340). step). If the status bit is enabled, the status bit of the memory block corresponding to the number is read in the vector register 240, and the memory block is determined to be usable, and if it is disabled, it is determined to be unavailable (step 350). If available, the start address of the memory block to be used is calculated using Equation 1 below using the memory block number to be indexed in the first register 220 (step 360).

If it is determined that the corresponding memory block is not available by reading the above-described status bit or when the above-mentioned memory block is finished, the memory block number to be indexed written in the first register 220 is changed to the number of the memory block having the next linked order. In operation 380, the status bit of the memory block that has just been used in the vector register 240 is disabled to indicate that the memory block is in an 'unavailable' state (operation 380). Comparing the size of the contents of the first register 220 and the second register 230 to use another memory block when the use of one memory block is finished or the state of the memory block to be used is disabled (step 320). To do it again.

For example, the operation of the present invention will be described below. When the memory unit 210 is to be used, first, the control unit 200 initializes the first register 220 and the vector register 240 (step 300). The first register 220 includes the memory unit 210. The first memory block number is written and the state registers indicating whether all memory blocks are used or not are set in the vector register 240 to include a predetermined content meaning 'usable'. In this case, for example, '1' is set as the initial value in the first register 220 and stored. In addition, the second register 230 stores the number of the last memory block constituting the memory unit 210 (step 310). For example, if the last memory block number is '8', '8' is stored in the second register 230. In order to index the memory block to be used, the controller 200 compares the sizes of the contents of the first register 220 and the second register 230 (step 320). Since it is smaller than the contents of the register 230, the status bit of the register corresponding to the memory block number to be indexed written in the first register 220, that is, the memory block number '1' in the vector register 240 is set. Read (step 330). If the status bit is written to mean 'usable', the start address of the memory block to be used is calculated by using the number of the memory block in the first register 220 as shown in Equation 1 above, and the corresponding memory block is '1'. The memory is used by accessing from the start address of the 'memory' block (step 360). The controller 200 increases the memory block number to be indexed recorded in the first register 220 (step 370). The increased value becomes the number of the next memory block linked to the memory block just used. Disable the status bit of the just-used memory block in the vector register 240 (step 380) to prevent anyone from accessing this memory block. In order to access the next memory block again, comparing the sizes of the contents of the first register 220 and the second register 230 described above (step 320), the process is repeated sequentially.

According to the present invention, the number of memory accesses can be reduced by using a vector register having information of status bits containing information of whether a corresponding memory block is available or not.

Claims (6)

A memory unit for linking a plurality of memory blocks with each other and assigning a predetermined number to each of the memory blocks; A first register storing a number of one memory block to be indexed among the memory blocks; A second register for storing a number of the last linked memory block of the memory blocks; A third register in which a plurality of pieces of data are processed in parallel and one status bit indicating whether each memory block is in use or not; And The memory block to read the contents stored in the first register and the second register is determined to determine the memory block, and by reading the status bits for the memory block in the third register to determine whether the memory block to be indexed is available, the memory accordingly And a control unit for accessing the memory management apparatus. The method of claim 1, wherein the memory unit And a plurality of memory blocks of the same low capacity. The method of claim 1, wherein the third register, And a vector register comprising a plurality of registers, data is inputted and outputted in parallel for each register, and data movement between the registers is not permitted. A memory register in which a plurality of memory blocks are linked to each other, a first register storing a memory block number to be indexed among block numbers for distinguishing the memory blocks, a second register storing a number of a last memory block among the memory blocks; A control unit for accessing the memory unit by reading the first register, the first register, the second register, and the third register, each of which is composed of a plurality of registers, in which a state bit indicating whether the memory block is in use or disabled is written. In the memory management method of the system comprising: A first step of initializing the first register and the vector register and storing the number of the last memory block of the memory unit in the second register; Reading a status bit of the vector register with respect to the memory block number written in the first register if the content of the first register in the first step is less than or equal to the last memory block number of the second register; A third step of initializing contents of the first register when the contents of the first register in the first stage are larger than the memory block number stored in the second register; A fourth step of determining whether a corresponding memory block is enabled by reading the status bits of the third register of the second step; Calculating a start address of a memory block to be used as a memory block number to be indexed in the first register when the corresponding memory block is enabled in the fourth step; In the fourth step, when the corresponding memory block is in a disabled state or when the use of the memory block ends, the number of the next memory block linked to the memory block is written to the first register, and the third memory block is used for the used memory block. Disabling a status bit of the memory block in a register; And And a seventh step of performing again from the second step to use another memory block in the sixth step. The method of claim 4, wherein the initialization of the first register and the third register, And writing the number of the linked block to be accessed first among the memory blocks in the first register, and setting the memory block in the vector register to enable in all registers. The method of claim 4, wherein the calculating of the start address of the memory block to be used comprises: A start address = start address of the first memory block + (index), wherein the start address of the first memory block of the memory unit is added by multiplying the capacity of one memory block by a value obtained by subtracting 1 from the memory block number stored in the first register. A memory management method characterized by the number of memory blocks to be minus 1) * capacity of one memory block in bytes.

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