KR100258876B1 - Method for fabricating test package of semiconductor - Google Patents
Method for fabricating test package of semiconductor Download PDFInfo
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- KR100258876B1 KR100258876B1 KR1019980001547A KR19980001547A KR100258876B1 KR 100258876 B1 KR100258876 B1 KR 100258876B1 KR 1019980001547 A KR1019980001547 A KR 1019980001547A KR 19980001547 A KR19980001547 A KR 19980001547A KR 100258876 B1 KR100258876 B1 KR 100258876B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 시험용 패키지의 제조방법에 관한 것으로, 종래 기술은 세라믹 패키지를 제작하기 위한 고가의 금형 제작을 해야 하고, 상기 세라믹 패키지에 반도체 칩의 실장시 별도의 보트가 필요하게 되며, 세라믹 패키지의 전용 다이본딩머신 및 웨지본딩머신이 필요하게 되므로 공정비용의 상승이 불가피한 바, 이에 본 발명은 범용 리드프레임의 캐비티 외측에 방사상으로 다수개 형성된 인너리드의 일단부에만 고상의 에폭시수지를 몰딩하여 경게막을 형성하는 단계와, 상기 캐비티의 상면에 반도체 칩을 부착하는 다이본딩 단계와, 상기 반도체 칩과 인너리드의 노출된 부분을 와이어로 연결하여 전기적 신호의 연결작업을 하는 와이어본딩 단계와, 상기 반도체 칩 및 와이어를 보호하기 위해 캐비티 전체에 액상의 에폭시수지를 도포하는 포팅 단계와, 상기 반도체 칩의 전기적 신호를 외부로 전달할 수 있도록 리드를 형성하는 트리밍/포밍 단계로 이루어진 것을 특징으로 하는 반도체 시험용 패키지의 제조방법을 제공함으로써, 별도의 금형 제작이 불필요하므로 시험용 패키지의 제조 및 특성 검사를 용이하고 신속하게 진행할 수 있으며, 아울러 공정비용 절감의 효과가 있다.The present invention relates to a method for manufacturing a semiconductor test package, and the prior art has to produce an expensive mold for manufacturing a ceramic package, a separate boat is required when the semiconductor chip is mounted on the ceramic package, Since an exclusive die bonding machine and a wedge bonding machine are required, an increase in process cost is inevitable. Accordingly, the present invention is to mold and solidify the epoxy resin only at one end of the inner lead formed radially outside the cavity of the general-purpose lead frame. Forming a film, attaching a semiconductor chip to an upper surface of the cavity, connecting a semiconductor chip and an exposed portion of the inner lead with a wire, and connecting a signal to each other to connect an electrical signal; Fabric that applies liquid epoxy resin throughout the cavity to protect chips and wires And a trimming / forming step of forming a lead to transfer an electrical signal of the semiconductor chip to the outside, thereby providing a manufacturing method of a semiconductor test package, and thus, a separate mold is not required. Manufacturing and property inspection can be done easily and quickly, and process cost can be reduced.
Description
본 발명은 반도체 시험용 패키지의 제조방법에 관한 것으로, 특히 반도체 칩의 특성을 신속하게 검증하며, 제조비용을 절감하기 위한 반도체 시험용 패키지의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor test package, and more particularly, to a method for manufacturing a semiconductor test package for quickly verifying characteristics of a semiconductor chip and reducing manufacturing costs.
일반적으로 일정한 사양으로 다수개의 반도체 칩을 제조하면, 우선 그 반도체 칩의 전기적 특성 등을 검증하여 이상이 없으면 인쇄회로기판에 실장하기 위한 패키지를 제조하고, 이상이 있으면 이상이 발생한 부분을 보완하여 재생산하게 되는데, 이와 같이 미리 반도체 칩의 특성을 검증하기 위한 패키지를 시험용 패키지라 부른다.In general, when a plurality of semiconductor chips are manufactured to a certain specification, first, the electrical characteristics of the semiconductor chips are verified, and if there is no abnormality, a package for mounting on the printed circuit board is manufactured. In this way, the package for verifying the characteristics of the semiconductor chip in advance is called a test package.
이와 같은 반도체 시험용 패키지는 반도체 패키지를 양산하기에 앞서 칩이 설계된 대로 정확하게 동작하는지를 검증하기 위하여 사용되는 간이 패키지로서 매우 고가이며 빈번하게 사용되게 된다.Such a semiconductor test package is a very expensive and frequently used package that is used to verify that the chip operates exactly as designed prior to mass production of the semiconductor package.
종래에는 시험용 패키지로 세라믹 재질로 이루어진 패키지(이하, "세라믹 패키지"로 통칭함)를 사용하게 되는데, 이 세라믹 패키지는 도 1에 도시된 바와 같이 소정 형상의 세라믹으로 이루어진 몸체(1)와, 그 몸체(1)의 상면 중앙에 형성되어 검사하고자 하는 반도체 칩(미도시)을 안착시키기 위한 캐비티(2)와, 그 캐비티(2)의 양측에 다수개 설치되어 반도체 칩의 아웃리드와 접촉하여 외부와의 전기적 단자 역할을 하는 리드(3)로 구성되어 있다.Conventionally, a package made of a ceramic material (hereinafter, referred to as a “ceramic package”) is used as a test package. The ceramic package includes a body 1 made of ceramic having a predetermined shape as shown in FIG. Cavities 2 are formed in the center of the upper surface of the body 1 for mounting a semiconductor chip (not shown) to be inspected, and a plurality of cavities 2 are provided at both sides of the cavity 2 so as to be in contact with the outlead of the semiconductor chip. It consists of a lead 3 serving as an electrical terminal with the.
이와 같은 세라믹 패키지는 반도체 칩의 사양, 즉 반도체 칩의 크기, 모양, 본딩 패드의 위치, 와이어의 수 등을 고려하여 설계한 후, 제조를 진행한다.Such a ceramic package is designed in consideration of the specifications of the semiconductor chip, that is, the size, shape of the semiconductor chip, the position of the bonding pad, the number of wires, and the like, and then proceeds to manufacture.
이와 같이 제조된 세라믹 패키지는 개별로 움직일 수 없으므로 도 2와 같은 패키지 안착부(4a)가 형성된 별도의 보트(4)에 안착 이동되는 상태에서 다이본딩머신(미도시)으로 반도체 칩을 상기 세라믹 패키지에 실장하는 다이본딩작업을 진행하게 되며, 그후 별도의 웨지본딩머신(미도시)을 이용하여 반도체 칩의 아웃리드와 상기 세라믹 패키지의 리드(3)를 와이어로 연결하여 전기적 연결을 이루는 웨지본딩작업을 한다.Since the ceramic package manufactured as described above cannot be moved separately, the semiconductor chip is transferred to the ceramic package by a die bonding machine (not shown) while being seated and moved in a separate boat 4 having the package seating portion 4a as shown in FIG. 2. The die-bonding operation is carried out, and then, a separate wedge-bonding machine (not shown) is used to connect the outlead of the semiconductor chip and the lead 3 of the ceramic package with a wire to form an electrical connection. Do it.
그후, 상기 와이어에 가해지는 손상을 방지하기 위해 상기 캐비티(2) 부분을 액상의 에폭시 수지를 이용하여 밀봉하고, 테스트하기에 적합하도록 상기 리드를 절단하는 트리밍공정을 실시함으로써 세라믹 패키지의 제조가 완성된다.Thereafter, the cavity 2 is sealed using a liquid epoxy resin to prevent damage to the wire, and a trimming process of cutting the lead to perform a test is completed to complete the manufacture of the ceramic package. do.
그러나, 상기와 같은 종래 기술은 세라믹 패키지를 제작하기 위한 고가의 금형 제작을 해야 하고, 상기 세라믹 패키지에 반도체 칩의 실장시 별도의 보트(4)가 필요하게 되며, 세라믹 패키지의 전용 다이본딩머신 및 웨지본딩머신이 필요하게 되므로 공정비용의 상승이 불가피한 문제점이 있었다.However, the prior art as described above is required to manufacture an expensive mold for manufacturing a ceramic package, and when the semiconductor chip is mounted on the ceramic package, a separate boat 4 is required, and a dedicated die bonding machine for the ceramic package and Since the wedge bonding machine is required, there is an inevitable problem of an increase in process cost.
따라서, 본 발명은 상술한 종래의 문제점을 해결하기 위하여 안출된 것으로, 일반적으로 사용되는 리드프레임상에 반도체 칩을 실장하여 시험용 패키지를 제조함으로써, 신속하고 저렴한 비용으로 시험용 패키지를 제조하기 위한 반도체 시험용 패키지의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and by manufacturing a test package by mounting a semiconductor chip on a lead frame generally used, a semiconductor test for manufacturing a test package at a quick and low cost The purpose is to provide a method for manufacturing a package.
도 1은 종래 기술에 의한 세라믹 패키지의 구조를 보인 정면도,1 is a front view showing the structure of a ceramic package according to the prior art,
도 2는 종래 기술에 의한 패키지를 이동시키기 위한 보트를 보인 평면도,2 is a plan view showing a boat for moving a package according to the prior art,
도 3은 종래 기술에 의한 패키지가 보트에 안착된 상태를 보인 평면도,3 is a plan view showing a state in which the package according to the prior art seated on the boat,
도 4는 본 발명에 적용되는 범용 리드프레임을 보인 평면도,4 is a plan view showing a general-purpose leadframe applied to the present invention,
도 5 내지 도 8은 본 발명에 의한 시험용 패키지의 제조방법을 순차적으로 보인 평면도로서,5 to 8 is a plan view sequentially showing a method of manufacturing a test package according to the present invention,
도 5는 몰딩공정을 보인 평면도,5 is a plan view showing a molding process,
도 6은 다이본딩공정을 보인 평면도,6 is a plan view showing a die bonding process,
도 7은 와이어본딩공정을 보인 평면도,7 is a plan view showing a wire bonding process,
도 8은 밀봉공정을 보인 평면도.8 is a plan view showing a sealing process.
** 도면의 주요부분에 대한 부호의 설명 **** Explanation of symbols for main parts of drawings **
10 ; 리드프레임 11 ; 캐비티10; Leadframe 11; Cavity
12 ; 인너리드 13 ; 아웃리드12; Inner lead 13; Outlead
14 ; 고상 에폭시수지 20 ; 반도체 칩14; Solid epoxy resin 20; Semiconductor chip
21 ; 와이어 30 ; 액상 에폭시수지21; Wire 30; Liquid epoxy resin
상기와 같은 본 발명의 목적을 달성하기 위하여, 범용 리드프레임의 캐비티 외측에 방사상으로 다수개 형성된 인너리드의 일단부에만 고상의 에폭시수지를 몰딩하여 경게막을 형성하는 단계와, 상기 캐비티의 상면에 반도체 칩을 부착하는 다이본딩 단계와, 상기 반도체 칩과 인너리드의 노출된 부분을 와이어로 연결하여 전기적 신호의 연결작업을 하는 와이어본딩 단계와, 상기 반도체 칩 및 와이어를 보호하기 위해 캐비티 전체에 액상의 에폭시수지를 도포하는 포팅 단계와, 상기 반도체 칩의 전기적 신호를 외부로 전달할 수 있도록 리드를 형성하는 트리밍/포밍 단계로 이루어진 것을 특징으로 하는 반도체 시험용 패키지의 제조방법이 제공된다.In order to achieve the object of the present invention as described above, forming a hard film by molding a solid epoxy resin only at one end of the inner lead is formed radially outside the cavity of the general-purpose lead frame, and a semiconductor on the upper surface of the cavity A die bonding step of attaching a chip, a wire bonding step of connecting an exposed portion of the semiconductor chip and an inner lead with wires, and a wire bonding step of connecting electrical signals, and a liquid phase in the entire cavity to protect the semiconductor chip and the wire. A potting step of applying an epoxy resin and a trimming / forming step of forming a lead to transmit an electrical signal of the semiconductor chip to the outside are provided.
이하, 본 발명에 의한 반도체 시험용 패키지의 제조방법에 대한 실시예를 첨부된 도면을 참고하여 설명하면 다음과 같다.Hereinafter, an embodiment of a method for manufacturing a semiconductor test package according to the present invention will be described with reference to the accompanying drawings.
도 4는 일반적으로 사용되는 리드프레임을 보인 평면도로서, 이에 도시된 바와 같이, 본 발명에 사용되는 리드프레임은 플라스틱으로 이루어진 범용 리드프레임(10)으로서, 중앙에 반도체 칩(도 6,7에 도시)을 탑재하여 본딩하기 위한 장방형의 캐비티(11)를 형성하고, 그 캐비티(11)의 외측에는 인너리드(12)를 방사상으로 형성하여 상기 반도체 칩의 패드(미도시)에 부착된 골드와이어(도 7에 도시)와 연결하며, 상기 각각의 인너리드(12)에는 아웃리드(13)를 일체로 연장 형성하여 외부와의 전기적 단자 역할을 한다.4 is a plan view showing a lead frame generally used. As shown in the drawing, the lead frame used in the present invention is a general-purpose lead frame 10 made of plastic, and a semiconductor chip (shown in FIGS. ) And a rectangular cavity 11 for mounting and bonding, and an inner lead 12 is radially formed outside the cavity 11 to be attached to a pad (not shown) of the semiconductor chip. 7, and each of the inner leads 12 has an outlead 13 integrally formed to serve as an electrical terminal with the outside.
이와 같은 리드프레임에서 도 5에 도시된 바와 같이, 고상의 에폭시수지(14)를 소정 형상의 금형을 이용하여 이후에 기술할 포팅공정시 가이드바 역할을 하도록 캐비티(11)는 노출된 상태로 인너리드(12)의 일단부에만 밀봉하고, 도 6에서와 같이 상기 캐비티(11)에 반도체 칩(20)을 부착하는 다이본딩을 진행하고, 도 7과 같이 상기 반도체 칩(20)의 패드(미도시)와 인너리드(12)의 밀봉되지 않은 부분을 금선 등의 와이어(21)를 이용하여 연결하는 와이어본딩을 실시하며, 도 8과 같이 상기 캐비티(11) 전체에 액상의 에폭시수지(30)를 밀봉하는 포팅작업을 진행하여 상기 인너리드(12) 및 와이어(21)를 보호함으로써 시험용 패키지의 제조를 완성한다.In such a lead frame, as shown in FIG. 5, the cavity 11 is exposed in the exposed state so that the solid epoxy resin 14 serves as a guide bar in a potting process to be described later using a mold having a predetermined shape. It seals only at one end of the lid 12, die-bonding attaching the semiconductor chip 20 to the cavity 11 as shown in FIG. 6, and pad (not shown) of the semiconductor chip 20 as shown in FIG. C) and an unsealed portion of the inner lead 12 are wire-bonded to each other using a wire 21 such as a gold wire. The liquid epoxy resin 30 is formed in the entire cavity 11 as shown in FIG. Porting work to seal the to protect the inner lead 12 and the wire 21 to complete the manufacture of the test package.
그후, 일반적인 트리밍(TRIMING)/포밍(FORMING)공정을 통해 반도체 칩(20)의 전기적 신호가 외부로 전달되도록 리드를 형성한다.Thereafter, a lead is formed so that an electrical signal of the semiconductor chip 20 is transmitted to the outside through a general trimming / forming process.
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 시험용 패키지의 제조방법은 범용 리드프레임에 기존에 사용되는 다이본딩머신 및 와이어본딩머신을 이용하여 시험용 패키지의 제조작업을 진행함으로써, 별도의 금형 제작이 불필요하므로 시험용 패키지의 제조 및 특성 검사를 용이하고 신속하게 진행할 수 있으며, 아울러 공정비용 절감의 효과가 있다.As described above, the method for manufacturing a semiconductor test package according to the present invention does not require the production of a separate mold by performing a manufacturing operation of the test package using a die bonding machine and a wire bonding machine, which are conventionally used for a general-purpose lead frame. Therefore, manufacturing and testing of the test package can be performed easily and quickly, and the process cost can be reduced.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980001547A KR100258876B1 (en) | 1998-01-20 | 1998-01-20 | Method for fabricating test package of semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980001547A KR100258876B1 (en) | 1998-01-20 | 1998-01-20 | Method for fabricating test package of semiconductor |
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| KR19990065973A KR19990065973A (en) | 1999-08-16 |
| KR100258876B1 true KR100258876B1 (en) | 2000-06-15 |
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| KR1019980001547A Expired - Fee Related KR100258876B1 (en) | 1998-01-20 | 1998-01-20 | Method for fabricating test package of semiconductor |
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