KR100255520B1 - A cache memory device having excess data ram - Google Patents

Abstract

The present invention provides an extra data RAM to replace a cell area of a defective data RAM by using the extra memory even when a specific cell of the data RAM is defective, thereby increasing the reliability and service life of the microprocessor. In order to provide a cache memory device capable of performing the above, the present invention provides decoding means for decoding an index address input from the outside; A tag RAM for storing an address and outputting an address stored in a corresponding cell of the address in response to an address input from the decoding means; A data RAM for storing data and outputting data stored in a corresponding cell of the address or storing data in the corresponding cell in response to an address input from the decoding means; First comparing means for comparing a physical address input from an external device and an address input from the tag RAM; Redundant data RAM for storing corresponding data to be stored in the defective memory cell when a defect occurs in a specific memory cell of the data RAM; Controlling the read and write operations of the redundant data RAM in response to the index address, the address of a defective cell among the plurality of cells of the data RAM from the fuse box, and a read / write control signal input from the outside; Control means for controlling an input / output terminal of the redundant data RAM; And selecting means for selecting one of a plurality of output data inputted from the data RAM and the redundant data RAM in response to a signal output from the first comparing means, and outputting the selected one to a data bus. Second comparing means for receiving the index address and the address of the cell where the defect occurred and comparing the two addresses with each other; Matching signal generating means for generating a matching signal for controlling the three-state buffering means in response to a comparison result signal output from the second comparing means and a test control signal input from the outside; And read / write control means for controlling read and write operations of the redundant data RAM in response to the coincidence signal and the read / write control signal.

Description

A cache memory device having excess data RAM

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a cache memory device having an extra data RAM, in which a specific cell of the data RAM is replaced with an extra data RAM. .

As the integration technology of semiconductors develops, the number of transistors integrated in a single chip tends to increase, and the function of the chip also tends to be complicated. According to this tendency, a relatively large cache memory is embedded in order to improve the performance of a semiconductor chip.

In general, some frequently used data or instructions stored in main memory (DRAM) are stored in a data cache or instruction cache memory in a microprocessor. When the microprocessor finds the data to use in the execution of the instruction unit, it first retrieves the desired data from the internal cache memory and retrieves it for use. The structure of the data or instruction cache memory basically includes a tag RAM, a data RAM, and an index address from an external source to enable word lines of the tag RAM and the data RAM. Decoders to compare the output of the tag RAM and the physical address input from the Translation Look a side Buffer (TLB) and output a selection control signal, and the data according to the output of the comparator. It has a column selector for selecting one of a plurality of outputs of the RAM.

In this case, the tag RAM and the data RAM are generally implemented as static random access memory (SRAM).

Since the conventional microprocessor does not have a separate spare memory, if a specific cell of the data RAM fails, a serious failure of the function of the microprocessor may occur.

That is, even when the control logic in the microprocessor is fully operated in the memory of the microprocessor, the conventional microprocessor has a problem that cannot be used even if only one bit fails as a result of the memory test in the chip.

Accordingly, the present invention devised to solve the above-described problems of the prior art is provided with an extra data RAM, so that a defect occurs in any specific cell of the data RAM by using the redundant memory. It is an object of the present invention to provide a cache memory device capable of increasing the reliability and service life of a microprocessor by replacing the cell area.

1 is a schematic block diagram of a microprocessor having a spare cache memory according to an embodiment of the present invention;

2 is a detailed configuration diagram of a control unit according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: Tag RAM

12: Pre-Decoder

13: X-decoder

14: data RAM

15: comparator

16: Column Selection

17: control unit

18: extra data RAM

The present invention for achieving the above object, decoding means for decoding the index address input from the outside; A tag RAM for storing an address and outputting an address stored in a corresponding cell of the address in response to an address input from the decoding means; A data RAM for storing data and outputting data stored in a corresponding cell of the address or storing data in the corresponding cell in response to an address input from the decoding means; First comparing means for comparing a physical address input from an external device and an address input from the tag RAM; Redundant data RAM for storing corresponding data to be stored in the defective memory cell when a defect occurs in a specific memory cell of the data RAM; Controlling the read and write operations of the redundant data RAM in response to the index address, the address of a defective cell among the plurality of cells of the data RAM from the fuse box, and a read / write control signal input from the outside; Control means for controlling an input / output terminal of the redundant data RAM; And selecting means for selecting one of a plurality of output data input from the data RAM and the redundant data RAM in response to a signal output from the first comparing means, and outputting the selected data to a data bus. A second comparing means for receiving the index address and the address of the cell where the defect occurs and comparing the two addresses with each other; Matching signal generating means for generating a matching signal for controlling the three-state buffering means in response to a comparison result signal output from the second comparing means and a test control signal input from the outside; And read / write control means for controlling read and write operations of the redundant data RAM in response to the coincidence signal and the read / write control signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

FIG. 1 is a schematic block diagram of a cache memory device having redundant data RAMs according to an embodiment of the present invention, in which “11” is a tag RAM and “12” is a pre-decoder ( Pre-Decoder, "13" is X-Decoder, "14" is Data RAM, "15" is Comparator, "16" is Column Selection, and "17" is The control unit " 18 " represents redundant data RAMs, respectively.

Referring to the drawings, the cache memory device of the present invention includes a pre-decoder 12 for precoding an index address input from an external device, and an X-decoder 13 for decoding the output of the pre-decoder 12. , A memory for storing an address, a tag RAM 11 for outputting an address stored in cells corresponding to an address input from the X-decoder 13, and a memory for storing data to be used, an X-decoder 13 The physical address and the tag RAM which are output from the data RAM 14 and the conversion index buffer (TLB, not shown in the drawing) which output data of the corresponding cell or store data in the corresponding cell according to the address inputted from 11) a comparator 17 for outputting a selection control signal for selecting one of a plurality of output data outputted from the data RAM 14 by comparing an address inputted from the data RAM 14, and storing data to be used together with the data RAM 14; Me Therefore, a spare data RAM 18 for replacing a specific cell of the data RAM 14 in case of a failure, a cell having a failure among a plurality of cells of the data RAM 14 from an index address and a fuse box from the outside. A control unit 17 and a comparator for controlling the read and write operations of the redundant data RAM 18 and receiving input / output signals of the redundant data RAM 18 and controlling the input / output terminals of the data RAM 14 and the redundant data RAM 18 ( In response to the selection control signal from 15), one of a plurality of output data input from the data RAM 14 and the redundant data RAM 18 is selected and output to the data bus, or data input through the data bus is output. It consists of a column selector 16 for storing in the data RAM 14 or the redundant data RAM 18.

Referring to Figure 1, the configuration and operation of the present invention will be described in detail.

First, the pre-decoder 12 and the X-decoder 13 decode the index address inputted from the outside, so that 128 words of the tag RAM 11, the data RAM 14, and the redundant data RAM 18 are decoded. Performs the function of enabling the word line. Here, the index address input from the outside is firstly decoded by the pre-decoder 12, and this decoded signal is secondly decoded by the X-decoder 13 again. The signal decoded by the X-decoder 13 is input to the tag RAM 11, the data RAM 14, and the redundant data RAM 18, respectively, and the tag RAM 11, the data RAM 14, and the redundant data. The word line of the RAM 18 is selected.

The tag RAM is a memory for storing an address, and outputs an address stored in cells corresponding to an address input from the X-decoder 13.

The comparator 15 compares the physical address from the conversion index buffer with the address input from the tag RAM 11 and selects a selection control signal for selecting one of a plurality of output data output from the data RAM 14. Output to the column selector 16.

The data RAM 14 is a memory storing data to be used, and outputs 256 bits of a corresponding cell at a time according to an input signal of the X-decoder 13.

The column selector 16 includes a plurality of multiplexers and selects one of a plurality of output data inputs from the data RAM 14 and the redundant data RAM 18 according to a selection control signal output from the comparator 15. To provide a path for output to the data bus or for storing data input through the data bus in the data RAM 14 or the redundant data RAM 18.

The redundant data RAM 18 is a memory for storing data to be used together with the data RAM 14, except that the redundant data RAM 18 replaces a defect in a specific cell of the data RAM 14. In other words, the input / output terminal of the redundant data RAM 18 is connected to the data bus through the column selector 16.

The controller 17 receives the address of the defective cell among the plurality of cells of the data RAM 14 from the index address and the fuse box from the outside, and reads and writes the redundant data RAM 18 by receiving a read / write signal. It controls the operation and controls the input / output terminals of the data RAM 14 and the redundant data RAM 18.

The input / output terminals of the data RAM 14 and the redundant data RAM 18 are constituted by a tri-state buffer, and the tri-state buffer is operated under the control of the controller 17.

By the above configuration, the redundant data RAM 18 can replace some memory cells of the defective data RAM.

FIG. 2 is a detailed configuration diagram of a controller according to an embodiment of the present invention, and illustrates a coupling relationship between components of the controller, a data RAM, and a redundant data RAM.

The controller 17 receives the index address and the address of the defective data RAM from the fuse box from the outside and controls the comparator 21 for comparing the two input addresses with each other, and controls the input / output terminal of the data ram and the input / output terminal of the redundant data RAM. A redundant data RAM read / write controller configured to control a read / write of the redundant data RAM by receiving a matched signal generator 22 generating a signal to be outputted, an output signal of the matched signal generator 22, and an external read / write signal. (23, 24) is provided.

The interaction between the controller 17 having the above configuration, the data RAM 14 and the redundant data RAM 18 will be described in detail as follows.

The comparator 21 receives the address of the defective data RAM and the index address from the outside and compares them with each other. Here, the address of the defective data RAM can be input through a fuse box located in the cache memory. In other words, if an error occurs due to a defect in a memory cell during a test of a row of data RAM, the index address is written to the fuse box by the laser's ON / OFF operation. The comparator 21 can receive the recorded value.

The comparator 21 outputs a comparison result signal as "high" when the address of the defective data RAM and the index address [6: 0] are the same.

The first AND gate 22 combines the comparison result signal input from the comparator 21 and the test control signal input from the outside to output a coincidence signal, and according to the coincidence signal, three states of the data RAM and the redundant data RAM are output. The buffer is controlled.

Here, the test control signal is a control signal generated by the control logic (not shown) present in the microprocessor to test the function of the data RAM only. That is, the control logic in the microprocessor outputs a test control signal "low" during the test of the data RAM to prevent the redundant data RAM from affecting the test results. In the normal operation mode, not the test mode, the test control signal is output as "high".

Therefore, the first AND gate 22, which is the coincidence signal generator, outputs a coincidence signal as " low " in the test mode, and in such a case (when the coincidence signal is low), the tri-state buffer in the data RAM is turned on. The tri-state buffer in the redundant data RAM is turned off.

In the normal operation mode, the first AND gate 22 outputs a coincidence signal as "high" when the comparison result signal of the comparator 21 is "high". In this case, the three-state buffer in the data RAM is It is turned off and the tri-state buffer in the redundant data RAM is turned on.

On the other hand, the test of the redundant data RAM 18 may be performed by applying the same address as the initial recording value through the fuse box when the test control signal is "high".

The redundant data RAM read / write controller includes a second AND gate 23 and a third AND gate 24. The second AND gate 23 combines the output coincidence signal of the first AND gate 22 and an external read / write signal to output the write control signal to the redundant data RAM 18. Similarly, the third AND gate 24 combines the output coincidence signal of the first AND gate 22 and an external read / write signal to output the output control signal to the redundant data RAM 18.

Here, one of the second and third AND gates 23 and 24 may invert the read / write signal input from the outside to be input according to the implementation method of the system.

In conclusion, a brief description of the features of the present invention is that a test is performed on a memory cell in a data RAM in a test mode, whereby the address of a defective memory cell is written to the fuse box. In the normal operation mode, when the index address and the address of the defective data RAM recorded in the fuse box match, the input / output terminal of the data RAM is blocked, and the data to be stored in the data RAM is made through the redundant data RAM.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

According to the present invention, a spare cache memory is separately provided in a microprocessor having a cache memory to prevent a defect of some memory cells of the cache memory, thereby replacing the function of a defective memory cell of the cache memory. In order to increase the reliability of the microprocessor, it is possible to increase the manufacturing yield of the microprocessor, thereby providing economic benefits.

Claims (4)

Decoding means for decoding the index address input from the outside; A tag RAM for storing an address and outputting an address stored in a corresponding cell of the address in response to an address input from the decoding means; A data RAM for storing data and outputting data stored in a corresponding cell of the address or storing data in the corresponding cell in response to an address input from the decoding means; First comparing means for comparing a physical address input from an external device and an address input from the tag RAM; Redundant data RAM for storing corresponding data to be stored in the defective memory cell when a defect occurs in a specific memory cell of the data RAM; Controlling the read and write operations of the redundant data RAM in response to the index address, the address of a defective cell among the plurality of cells of the data RAM from the fuse box, and a read / write control signal input from the outside; Control means for controlling an input / output terminal of the redundant data RAM; And And selecting means for selecting one of a plurality of output data input from the data RAM and the redundant data RAM in response to a signal output from the first comparing means, and outputting the selected data to a data bus. The control means, Second comparing means for receiving the index address and the address of the cell where the defect occurred and comparing the two addresses with each other; Matching signal generating means for generating a matching signal for controlling the three-state buffering means in response to a comparison result signal output from the second comparing means and a test control signal input from the outside; And Read / write control means for controlling read and write operations of the redundant data RAM in response to the match signal and the read / write control signal Cache memory device comprising a. The data RAM and the redundant data RAM, respectively, 3-state buffering means controlled by the control means The cache memory device further comprises. The coincidence signal generating means according to claim 1, First AND product for receiving and comparing the comparison result signal and the test control signal Cache memory device comprising a. The method of claim 3, wherein the read / write control means, Second logical multiplication means for performing an AND operation on the output signal of the first AND product and the read / write control signal to output the write control signal of the redundant data RAM; And Third logical multiplication means for outputting the output signal of the first logical multiplication means and the read / write control signal and outputting the output control signal of the redundant data RAM; Cache memory device comprising a.

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