KR100253647B1 - 전력감소회로 - Google Patents
전력감소회로 Download PDFInfo
- Publication number
- KR100253647B1 KR100253647B1 KR1019970005455A KR19970005455A KR100253647B1 KR 100253647 B1 KR100253647 B1 KR 100253647B1 KR 1019970005455 A KR1019970005455 A KR 1019970005455A KR 19970005455 A KR19970005455 A KR 19970005455A KR 100253647 B1 KR100253647 B1 KR 100253647B1
- Authority
- KR
- South Korea
- Prior art keywords
- voltage
- circuit
- threshold voltage
- power reduction
- pmos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0021—Modifications of threshold
- H03K19/0027—Modifications of threshold in field effect transistor circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (3)
- 외부로부터 소정의 제 1 전원 전압(VDD1), 제 2 전원 전압(VDD2), 제 1 접지 전압(VSS1), 그리고 제 2 접지 전압(VSS2)을 인가 받고, 슬립 모드를 알리는 신호(SL) 에 응답해서 소정 N 웰전압(VNWELL)을 출력하는 대기 전력 감소 수단(100)과; 전원 전압(VDD)과 상기 대기 전력 감소 수단(100)으로부터 출력되는 N 웰 전압(VNWELL)을 인가 받고, 상기 시놓(SL)에 응답해서 제 문턱 전압 및 상기 제 1 문턱 전압과 다른 레벨의 문턱 전압을 갖는 제 2 문턱 전압 중 어느 하나의 문턱 전압 레벨로 동작하는 수단(200)을 포함하고, 상기 대기 전력 감소 수단(100)은, 상기 제 1 및 제 2 전원 전압들(VDD1, VDD2)과 상기 제 1 및 제 2 접지 전앙ㅂ들(VSS1, VSS2)을 받아들여서 이들 중 적어도 하나의 전압을 상기 수단(200)으로 출력하는 쉬프트 회로(40, 500 및, 상기 신호(SL)에 응답해서 상기 쉬프트 회로(40, 50)로부터 출력되는 상기 전압들(VDD1, VDD2, VSS1, VSS2)의 출력 경로들을 선택하는 스위칭 회로(30)를 포함하는 전력 감소 회로.
- 제 1 항에 있어서, 상기 대기 전력 감소 수단(100)은, 2V 내지 4V의 N 웰 영역 전압(VNWELL)을 출력하는 전력 감소 회로.
- 제 1 항에 있어서, 상기 다중 문턱 전압 수단(200)은, 소오스가 제 1 노드에 연결된 제 4 PMOS 트랜지스터(MP4)와 드레인이 상기 제 4 PMOS 트랜지스터(MP4)의 드레인에 연결되고 게이트가 상기 제 4 PMOS 트랜지스터(MP4)의 게이트에 연결되고 소오스가 접지 된 제 3 NMOS 트랜지스터(MN3)를 포함하는 CMOS 인버터(10)와; 소오스에 전원 전압(VDD)이 인가되고, 게이트에 소정 신호()가 인가되고 드레인이 제 1 노드에 연결되고 웰영역에 상기 대기 전력 감소 수단(100)의 N 웰 영역 전압(VNWELL)이 인가되는 제 1 PMOS 트랜지스터(MP1)를 구비한 스위칭 수단(20)을 포함하는 전력 감소 회로.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970005455A KR100253647B1 (ko) | 1997-02-22 | 1997-02-22 | 전력감소회로 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970005455A KR100253647B1 (ko) | 1997-02-22 | 1997-02-22 | 전력감소회로 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980068699A KR19980068699A (ko) | 1998-10-26 |
| KR100253647B1 true KR100253647B1 (ko) | 2000-04-15 |
Family
ID=19497709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970005455A Expired - Fee Related KR100253647B1 (ko) | 1997-02-22 | 1997-02-22 | 전력감소회로 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100253647B1 (ko) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6166985A (en) * | 1999-04-30 | 2000-12-26 | Intel Corporation | Integrated circuit low leakage power circuitry for use with an advanced CMOS process |
| CN1277211C (zh) | 2003-05-06 | 2006-09-27 | 联想(北京)有限公司 | 一种计算机操作系统的修复方法 |
| KR100699832B1 (ko) * | 2005-01-05 | 2007-03-27 | 삼성전자주식회사 | Ｍｔｃｍｏｓ 제어 회로 |
| KR100784893B1 (ko) * | 2005-12-27 | 2007-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 컬럼 어드레스 디코딩 회로 |
| CN116110938A (zh) * | 2022-12-21 | 2023-05-12 | 天狼芯半导体(成都)有限公司 | 一种低导通电阻的mosfet功率器件及其制备方法 |
-
1997
- 1997-02-22 KR KR1019970005455A patent/KR100253647B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980068699A (ko) | 1998-10-26 |
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