KR100251925B1 - Data Split Information Automatic Loading Circuit - Google Patents

Abstract

TECHNICAL FIELD This invention relates to a high capacity hard disk drive having a headerless format, and more particularly, to a circuit capable of automatically loading data split information.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit capable of hardware loading data split information for a data sector during data read / write in a hard disk drive having a headerless format.

SUMMARY OF THE INVENTION A data split information automatic loading circuit of a high capacity hard disk drive having a headerless format, wherein split information of a data sector is counted from a data address mark by using a byte counter, and the servo sector has data. If present, a split interrupt is generated to temporarily store the counted data byte value in the storage means.If data is re-entered after the servo sector, in the write mode, the count value is written after the data address mark while in the read mode. At the time of writing, a predetermined counting value is read and written to the buffer memory.

Important use of the invention: Can be used in circuits that can provide data split information in hardware.

Description

Data Split Information Automatic Loading Circuit

1 is a block diagram of a hard disk drive according to the present invention.

2 is a timing diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to loading data split information of a high capacity hard disk drive having a headerless format, and more particularly to a circuit capable of automatically loading data split information. .

In a conventional high speed, high capacity hard disk drive having a headless format, the data split information is stored in the buffer memory, and when the zone is changed, the data split information is transferred from the main memory (ROM) to the buffer memory again. Downloaded In this case, when a DDC (Disk Data Controller) is applied to a sector pulse (hereinafter referred to as an SP), the DDC takes split information of every data sector from a buffer memory and uses the split data of the next data sector. It was. The data split value has the split value in the data read / write because the servo sector exists in the data. If the counter in the data area is the same as the split value already loaded, the read or write function is stopped. After receiving the interrupt at the end of the servo sector, read or write gate (RG) and write gate (WG) are enabled again to read or write data. Therefore, in the conventional hard disk drive having a headerless format, since N times split information has to be loaded for N data sectors, there is a problem that excessive overload occurs.

Accordingly, an object of the present invention is to provide a circuit capable of hardware loading data split information in a high speed, high capacity hard disk drive having a headerless format.

In order to achieve the above object, the present invention provides a disk in which a data sector and a servo sector are alternately positioned, and writes data received from an external device such as a host computer on the disk in magnetic form and reads already written data. A data split information automatic loading circuit of a hard disk drive having a headerless format having a head and control means for performing overall control operations for data read and write operations between the external device and the disk,

Counting means for counting and outputting the read reference clock RRCLK at the lead gate or write gate enable point;

Comparison means for generating and outputting a signal for disabling the read gate or the write gate when the output counting value of the counting means and the data original sector length are the same;

Latch means which is enabled when the split interrupt signal is input and latches the output value of the counting means;

A disk data controller which sequentially writes data synchronization, data address marks, and output values of the latching means by enabling the write gate again by the servo gate input after inputting the split interrupt signal in the data write mode;

Data address mark detection means for detecting a data address mark in the data read mode and generating and outputting a counting enable signal for enabling the counting means;

And a data count value detecting means for counting the read reference clock in data read mode to detect a data counter value and output the count value to the disk data controller.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, numerous specific details such as number of bytes, number of sectors, gating elements and the like are shown to provide a more general understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And detailed descriptions of well-known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

1 is a block diagram of a hard disk drive for automatic split loading according to the present invention. In FIG. 1, a head disk assembly (HDA) 10 includes a disk used as a recording medium and a head for recording and reading data received from a host computer on the disk in a magnetic form, and a servo driver (not shown). Drive by). In addition, in the following description, it is assumed that the HDA 10 includes an actuator for horizontally moving the head in the circumferential direction on the disk. The preamplifier 11 connected between the HDA 10 and the read / write channel circuit 12 pre-amplifies the signal picked up by the head in the data read mode and drives the head in the data write mode to drive the read / write channel circuit. The coded recording data applied from (12) is written onto the disc. The read / write channel circuit 12 generates and outputs a digitized servo sector pulse (also referred to as encoded read data ERD) from a signal input from the preamplifier 11. The servo synchronization circuit 14 outputs the servo sector pulses input from the read / write channel circuit 12 in synchronization with the system clock. Meanwhile, the index generator 16, the SP (sector pulse) generator 18, the SG (servo gate) generator 20, and the split interrupt (SI) generator 22 are servo sector pulses input from the servo synchronization circuit 14. The index pulse IP, the sector pulse SP, the subgate SG, and the split interrupt SI are respectively generated from and output to the DDC 24. The DDC 24 is controlled by the CPU 32 and transmits / receives read / write data with the host computer and simultaneously interfaces communication between the host computer and the CPU 32. In addition, the DDC 24 generates an RG or WG selection signal for read / write mode selection under the control of the CPU 32 when the SP is input from the SP generator 18 and outputs it to the read / write channel circuit 12. The data address mark detector 26 outputs a Byte Counter Enable (BCE) signal using 8-bit NRZ data and RRCLK (Read Reference Clock) input from the read / write channel circuit 12. The data count value detector 28 is connected between the read / write channel circuit 12 and the DDC 24 and uses the RRCLK input from the read / write channel circuit 12 to count the NRZ data. P ″ is output to the DDC 24. The buffer memory 30 is connected to the DDC 24 to temporarily store data transmitted and received between the host computer and the disk. On the other hand, the CPU 32 performs the overall control operation of the hard disk drive and generates and outputs an RG or WG selection signal in response to receiving a data read or write command from the host computer. The one sector length register 34 connected to the CPU 32 temporarily stores the one sector length value under the control of the CPU 32 and loads it into the comparator 36. On the other hand, the RG / WG selection signal set from the CPU 32 is inverted through the inverter INV1 and then gated at the lead gate RG and the AND gate A1 output from the DDC 24, and then input to the oragate 01. On the other hand, the RG / WG selection signal set from the CPU 32 is inputted to the oragate 01 after being gated at the write gate WG and the AND gate A2 output from the DDC 24. OA gate 02 RG / WG selection signal output from the CPU 32 and BCE output from the data address mark detector 26 are output to the AND gate A3, and the AND gate A3 is connected to the OA gates 01 and 02. The signals output from the RRCLK terminal of the output terminal and the read / write channel circuit 12 are AND-gated and output to the clock CK terminal of the byte counter 40. The byte counter 40 outputs a value counting a signal input through the clock CK terminal to the input terminal D of the register 38, and the register 38 outputs the RG / WG selection signal and the servo at the AND gate A6. Enabled by the logic level of the signal engaged by interrupt SI. The comparator 36 compares the value input from the output terminal Q of the byte counter 40 and the one sector length register 34 through the X and Y terminals, and if the values are the same, the logic signal of the "high" state is output. Output through the output terminal (Q). At this time, the logic signal output from the comparator 36 is commonly input to the disable terminal DIS of the inverters IN2 and DDC24. The AND gate A4 resets the signal generated by the AND gate output signal of the comparator 36 and the PORB (Power On Reset Bar) signal inverted through the inverter IN2. Output to terminal Hereinafter, the automatic split value loading process in the read or write mode in the hard disk drive having the above-described configuration will be described.

First, an automatic loading process of data split information in the data write mode will be described. Upon receiving a data write command from the host computer, the CPU 32 performs search and follow control for moving the actuator to the target track. When the head is located on-track, the servo sector signal read from the head is transmitted to the read / write channel circuit 12 through the preamplifier 11. The servo sector signal is output from the read / write channel circuit 12 as a digitalized servo sector signal (ie, ERD) and applied to the servo synchronization circuit 14. The digitalized servo sector signal is output from the servo synchronizer 14 to the index generator 16, the SP generator 18, the SG generator 20, and the SI generator 22 in synchronization with the system clock SCLK. Thereafter, the index generator 16, the SP generator 18, the SG generator 20, and the SI generator 22 generate index pulses IP, SP, SG, and SI, respectively, and output the index pulses to the DDC 24. The SG generated in 20 is also input to the read / write channel circuit 12. The DDC 24 generates and outputs a WG for writing data information stored in the buffer memory 30 transmitted from the host computer when the first SP is input after the IP input from the index generator 16. At this time, the WG generated and output from the DDC 24 is simultaneously input to the AND gate A2 and the read / write channel circuit 12. On the other hand, when the CPU 32 receives the data write command from the host computer, the CPU 32 sets and outputs the RG / WG selection signal to the "high" state so that the AND gate A2 outputs the logic signal of the "high" state to the oragate 01. do. Thus, the OR gates 01 and 02 output the logic signal in the "high" state. Therefore, the AND gate A3 outputs the RRCLK input from the read / write channel circuit 12 to the clock stage CK of the byte counter 40 when the WG is enabled. The byte counter 40 then outputs a value counting RRCLK inputted to the clock terminal CK through the Q terminal, and the comparator 36 controls the value loaded from the original sector length register 34 under the control of the CPU 32. When the output values of the byte counter 40 are compared and the values are the same, the disable signal of the "high" state for disabling the WG is output through the Q terminal. As a result, the DDC 24 disables the WG. If the SI is generated and output from the SI generator 22 due to the presence of the servo sector during counting, the SI is input to the AND gate A6 and end gated with the RG / WG selection signal set to the "high" state. 38) will be enabled. As a result, the register 38 momentarily latches the output counting value " P " of the byte counter 40 and transmits it to the CPU 32 and the DDC 24. On the other hand, the DDC 24 waits for the servo sector to pass after the SI input, and when the WG is enabled again by the SG input, the data synchronization and data address marks are written, and the " P " input from the register 38 is loaded into the NRZ data. Write and the rest of the data. In the above-described method, the ECC polynominal of each data sector in a specific zone at the time of data writing differs in all data sectors by the "P" value. That is, if there is no SI input from the SI generator 22, the DDC 24 generates the polynominal of the ECC based on the data, and if the SI is generated and the "P" value is input, the ECC polynomial including the "P" value This is created and written to disk. Hereinafter, the automatic split loading process in the data read mode will be described.

In response to the data read command received from the host computer, the CPU 32 sets and outputs the RG / WG selection signal as a logic signal in the "low" state. When the RG is enabled in the DDC 24, the read / write channel is output. The circuit 12 synchronizes the data synchronization read from the disk by using the PLL circuit and transmits the NRZ data and RRCLK accordingly to the DDC 24 and the byte counter 40. The data address mark detector 26 generates a BCE for enabling the byte counter 40 when the data address mark is detected from the 8-bit NRZ data input from the read / write channel circuit 12 to the oragate 02. Output On the other hand, if the RG / WG selection signal is "low" and RG is enabled, the AND gate A1 is "high" and the byte counter 40 starts counting when the data address mark is detected. If there is no split information of the data, when the counting value is equal to the original sector length value, a signal for disabling the RG is transmitted to the DDC 24 to disable the RG. If a split occurs in the data, the register 38 is disabled and read by the data count value detector 28 to read the " P " value. At this time, the data can be written to the buffer memory 30 from 0 to K, and the remaining data from K + 1 to N bytes can be written by the value "P".

2 shows a detailed timing diagram according to the present invention, and (a) shows a sector format according to the present invention. In FIG. 2, the index pulse IP should always be generated at the end of the servo sector, and by the index pulse IP, the sector pulse SP is constantly generated by calculating the length of one data sector. The servo gate SG is generated to protect the servo sector area with respect to the servo sector. The split interrupt SI is always generated in front of the servo area to inform the data sector information of the data sector. In the data write mode, the DDC 24 receives the sector pulse SP to enable the WG, receives the data from the host computer, and writes the data synchronization and data address marks among the data sectors in the buffer memory 30 to the disk. At the time of data writing, the byte counter 40 is operated and counted with the RRCLK inputted from the read / write channel circuit 12 at the same time. For example, count 512 bytes of data + 22 bytes of ECC + PAD. Normally, if it does not meet the servo sector, the byte counter 40 counts up to N bytes, which is the length of one data sector, and stops when the WG is disabled. If there is a servo sector inside the data sector and the data split information is needed, if the counter starts from the data and the SI is generated and input, the byte counter 40 specifies the data byte count value "P" until after the SI is input. Transfer to register 38. The register 38 then latches and holds the counting value " P " and the WG is disabled. In addition, until the SI is input from the buffer memory 30, the data is read from the buffer memory 30 up to "K" and stopped when the SI is input. When the servo sector passes and WG is enabled again, the DDC 24 again writes data synchronization, data address marks, writes "P" which is the value when the data is split, and reads the buffer memory 30 after "K". Read up to N bytes and additionally read the PAD.

In the data read mode, the DDC 24 receives the sector pulse, enables RG, and enters the read / write channel circuit 12. Then, the data synchronization is phase locked using the PLL circuit inside the read / write channel circuit 12. After (Phase Lock) the data is read as soon as the data address mark is detected. At this time, the byte counter 40 also starts counting based on RRCLK. If there is a servo sector in the data and a data split occurs, the data is first read and SI is transmitted. The current data is transferred to the buffer memory 30 and the RG is disabled. When the split ends and RG is enabled again, data synchronization is synchronized again and a data address mark is detected to read the next two bytes of data counting value "P". This reads the value " P " as the number of bytes of data counted when transferring the data before the data split to the buffer memory 30 to indicate how much more data to read in the future. Further, the data before the split of the buffer memory 30 is additionally written and transmitted to the host computer.

As described above, the present invention has an advantage of reducing software overload by loading data split information in hardware in a hard disk drive having a headerless format.

Claims (3)

A disk in which a data sector and a servo sector are alternately positioned, a head which reads data received from an external device such as a host computer in a magnetic form on the disk and reads already written data, between the external device and the disk. A data split information autoloading circuit of a hard disk drive having a headerless format having control means for performing overall control operations for data read and write operations of Counting means for counting and outputting the read reference clock RRCLK at the lead gate or write gate enable point; Comparison means for generating and outputting a signal for disabling the read gate or the write gate when the output counting value of the counting means and the data original sector length are the same; Latch means which is enabled when the split interrupt signal is input and latches the output value of the counting means; A disk data controller which sequentially writes data synchronization, data address marks, and output values of the latching means by enabling the write gate again by the servo gate input after inputting the split interrupt signal in the data write mode; Data address mark detection means for detecting a data address mark in the data read mode and generating and outputting a counting enable signal for enabling the counting means; And data count value detecting means for counting said read reference clock in data read mode to detect a data counter value and output it to said disk data controller. 2. The automatic data split information according to claim 1, wherein the rape means is enabled according to a logic level of a signal generated by AND gating a read / write selection signal and a split interrupt signal set by the control means. Loading circuit. 3. The split interrupt signal of claim 2, wherein the disk data controller stores a counting value input from the data count value detecting means when the split interrupt signal is enabled in the data read mode, and disables the read gate. The data split information automatic loading circuit is characterized in that the read gate is re-enabled to input and store a data counting value when the signal is disabled.