KR100251103B1 - Circuit for separating vertical synchronous signal from composite synchronous signal - Google Patents

Abstract

A vertical sync separation circuit is disclosed in which only a vertical sync signal is separated from a complex sync signal in which a horizontal sync signal and a vertical sync signal are included in a television signal input to a television or a monitor. An input unit for providing a control current by receiving a composite synchronizing signal including a horizontal synchronizing signal, a vertical synchronizing signal, and an equalization pulse from an input terminal, a constant current unit for providing a constant difference current of the current mirror by receiving the control current, and the current A comparator for receiving a constant difference current and a comparison reference voltage of a mirror to provide a constant difference current and a compared current of the current mirror, and providing a voltage charged and discharged in a capacitor by receiving a constant difference current of the current mirror And a condenser unit for outputting a vertical synchronization signal separated from the comparison reference voltage and the composite synchronization signal by receiving the compared current. Can be configured. Therefore, an improved vertical synchronous separation circuit which receives the complex synchronous signal including the horizontal synchronous signal and the vertical synchronous signal and integrates only the vertical synchronous signal more stably since the integrated circuit is possible than the conventional RC discrete element. Can be implemented.

Description

Vertical Sync Separation Circuit from Vertical Sync Signal Separated from Composite Sync Signal

TECHNICAL FIELD The present invention relates to a vertical sync separation circuit, and more particularly, to an improved vertical sync circuit for outputting a vertical sync signal from a composite sync signal including an interlaced vertical sync signal and a horizontal sync signal in a television.

The television signal includes a video signal, a horizontal synchronizing signal and a vertical synchronizing signal, and the composite synchronizing signal includes a horizontal synchronizing signal and a vertical synchronizing signal.

The television screen consists of 30 frames per second, one frame consists of 1st and 2nd films interlaced on the TV, and the 1st and 2nd films are 0.5H (H: 63.5μs in horizontal scanning period). ) Pulse difference.

The field scanned by the television is a complex synchronization signal consisting of a horizontal synchronization signal of 1H period, an equalizing pulse of 3H size in 0.5H period, a vertical synchronization signal of 3H size in 0.5H period, and an equalization pulse of 3H size in 0.5H period. It is composed.

A horizontal sync pulse is necessary to shift the scan point back to the left end by this pulse when the scan point shifts from the left end of the screen to the right when interlaced on the television screen.

The vertical sync pulse is used to shift the scan point back to the top left corner of the screen in order to scan two feeds again since the scan point moves to the bottom end of the screen when one feed ends. The vertical synchronizing signal has a width of 3H, and 6 pulses are inserted in the period. In addition, before and after the vertical synchronization signal, equalization pulses are contained in the pulse group of the vertical blanking signal.

As shown in Fig. 1, equalizing pulses are pulses of six pulses at intervals of 0.5H at the front and rear ends of the vertical synchronization pulses having the magnitude of 3H in the composite synchronization signal. It is composed of and is a signal necessary to complete interlaced injection.

The horizontal synchronizing signal is transmitted for each horizontal line to keep the horizontal scanning synchronized, and the vertical synchronizing signal is transmitted for each feed. The vertical synchronizing signal, the equalization pulse, and the vertical synchronizing signal can be seen as a periodic waveform with the same amplitude but different pulse width as shown in FIG. Each vertical sync pulse is wider than a horizontal pulse because it exists over a period of six horizontal lines, or three complete horizontal lines. This is to change the shape of the vertical and horizontal pulses so that they can be completely separated, so that one side gives only horizontal synchronization and the other gives only vertical synchronization. In addition, a vertical pulse is inserted into the vertical pulse every half of the horizontal line, which divides the wide vertical pulse into six narrow intervals, each of which is used as a horizontal synchronizing pulse, so that the horizontal synchronism is kept stable even during the vertical synchronizing period. To do that. That is, the horizontal synchronization must be maintained even in the vertical retrace period, but if the horizontal synchronization signal is lost in the vertical retrace period, the interlaced scan is not performed, and the synchronization is not restored until the horizontal scanning effective for reproduction starts.

간격(0.5H)으로 되어 있어 하나의 컬러 수평 동기 펄스의 역할을 한다. 이 경우 수평 동기 펄스로서의 역할을 하는 동화 펄스는 각 피일드에 따라 결정되며 짝수번째와 홀수번째의 피일드에서는 서로 교대한다. 즉, 짝수번째와 홀수번째의 피일드에서 수직 동기 신호에서 생기는 차이를 등화시키기 위해서 삽입된다. 이와 같이 짝수번째와 홀수번째의 피일드에서 서로 다른 수직 동기 신호를 같은 모양으로 만들어 완전한 비월주사가 이루어지도록 한다.Equalization pulse of the horizon

Interval (0.5H) serves as one color horizontal sync pulse. In this case, the moving picture pulse serving as the horizontal synchronizing pulse is determined according to each of the feeds, and the even and odd feeds alternate with each other. In other words, it is inserted to equalize the difference occurring in the vertical synchronization signal in the even and odd periods. As such, different vertical sync signals are formed in the same shape in the even-numbered and odd-numbered periods so that complete interlacing is achieved.

In addition, the synchronization signal scanned to the television is transmitted in a form superimposed on the video signal to completely match the speed and time of the scan line of one line between the transmitting side and the receiving side, and the frequency of the horizontal and vertical deflection oscillation circuit of the television receiver is adjusted. Used to control

1 is a simple vertical sync separation circuit using a conventional RC low pass filter.

The conventional vertical synchronous separation circuit is a vertical synchronous separation circuit that performs a low pass filter function as an RC integrator, as shown in FIG. The composite sync signal is input from the sync clipper, that is, one field is a horizontal sync signal of 1H cycle, an equalizing pulse of 3H size in 0.5H cycle, a vertical sync pulse of 3H size in 0.5H cycle, and a 0.5H cycle. A composite synchronization signal consisting of a 3H-sized equalization pulse and a 1H period horizontal synchronization signal is input to a low pass filter (LPF), an RC integrator, to extract a vertical synchronization signal, and output a vertical synchronization signal to a vertical oscillator. Indicates. In addition, the vertical sync signal has a higher pulse width than the equalized pulse or the horizontal sync signal, and has a high pulse width of 27.3 μs and a low pulse width of 4.44 μs. The field period of) is represented by 16,666.6 μs.

Therefore, in the conventional simple vertical sync separation circuit described above, there is a problem in that an accurate output waveform of the vertical sync signal cannot be obtained with a simple circuit configuration.

The present invention has been made to solve the problems of the prior art in view of the above, the object of the present invention is to configure the RC low pass filter to configure the active element to be suitable for IC without separating the vertical synchronization signal It is to provide a circuit for separating the vertical synchronization signal of the television signal.

1 is a conventional simple vertical sync separation circuit.

2 is a circuit diagram illustrating a vertical sync separation circuit according to an embodiment of the present invention.

Fig. 3 is a waveform diagram showing a composite synchronization signal of a field to be scanned on a television.

4 illustrates an output waveform of a voltage and a vertical synchronization signal that are charged and discharged in a capacitor in the horizontal synchronization signal section of FIG. 3.

FIG. 5 illustrates output waveforms of a voltage and a vertical synchronization signal that are charged and discharged in a capacitor in the equalizing pulse section of FIG. 3.

6 is a waveform diagram of receiving a composite synchronization signal from a vertical synchronization separation circuit and outputting a vertical synchronization signal.

FIG. 7 is a circuit diagram for explaining the basic function of the current mirror in the vertical synchronous separation circuit of FIG.

<Description of the symbols for the main parts of the drawings>

V _B : Comparative reference voltage of the comparator applied to the base of the tenth transistor

V _C1 : Voltage applied to the base of the ninth transistor by charging and discharging the capacitor

D1: diode C1: capacitor

R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12: Resistance

Q4: The base and collector are connected to perform the current mirror function.

pnp BJT transistor

Q6, Q7: base and collector are connected to perform the current mirror function

npn type BJT transistor

Q1, Q5, Q8, Q9, Q10, Q12: npn type BJT transistor

Q2, Q3, Q11: pnp type BJT transistor

In order to realize the above object of the present invention, the present invention, an input unit for receiving a complex synchronization signal including a horizontal synchronization signal, a vertical synchronization signal and an equalization pulse from the input terminal to provide a control current; A constant current unit configured to receive the control current and provide a constant difference current of the current mirror; A comparator configured to receive a constant difference current and a comparison reference voltage of the current mirror to provide a constant difference current and a compared current of the current mirror; A condenser unit for receiving a constant difference current of the current mirror to provide a voltage charged and discharged from the capacitor; And an output unit configured to receive the compared current and output a vertical synchronization signal separated from the comparison reference voltage and the composite synchronization signal to an output terminal, wherein the vertical synchronization separation circuit separates the vertical synchronization signal from the composite synchronization signal. to provide.

According to the present invention, the composite image signal is separated from only the synchronization signal in the synchronization separation circuit and inputs a composite synchronization signal including a vertical synchronization signal and a horizontal synchronization signal from an input terminal of the vertical synchronization separation circuit to include a first resistor and a first transistor. Including an input unit, second, third, fourth, fifth, and sixth resistors and fourth and sixth transistors connected to a collector and a base performing a current mirror function, and mirrored second, third, and fifth transistors. A capacitor unit including a constant current unit providing a constant current, a capacitor for charging and discharging a current of a current difference between the collector current of the second transistor and the collector current of the fifth transistor, the seventh, eighth, ninth resistors, diodes, A tenth and a tenth transistor including a seventh transistor, an eighth transistor, and a comparator, to which a base and a collector, which perform a current mirror function, are connected; Comparator, tenth, eleventh, twelfth, thirteenth resistor, eleventh transistor, and inverter function which are compared by the capacitor voltage input to the base of the ninth transistor by the reference voltage of the comparator applied to the base of the transistor. A vertical synchronization signal separated from the composite synchronization signal is output through an output unit including a twelfth transistor that performs the operation.

Therefore, it is possible to separate the vertical synchronizing signal of the television signal by receiving the composite synchronizing signal including the horizontal synchronizing signal and the vertical synchronizing signal interlaced into the television and configuring the active element to be suitable for IC.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a circuit diagram illustrating a vertical synchronous separation circuit according to an embodiment of the present invention.

The vertical synchronous separation circuit includes an input unit 100, a constant current unit 200, a comparison unit 300, a condenser unit 400, and an output unit 500.

The input unit 100 includes a first resistor R1 and a first transistor Q1.

The first resistor R1 receives the composite synchronization signal 110 from the input terminal 103.

The first transistor Q1 is an npn type BJT transistor, a base connected to the first resistor R1, an emitter grounded, and providing a control current 123 to a collector.

The constant current unit 200 includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second transistor Q2, and a second resistor R2. It consists of three transistors Q3, a fourth transistor Q4, a fifth transistor Q5 and a sixth transistor Q6.

The second resistor R2 is connected to the emitter of the second transistor Q2 with a resistance of 15k to receive the constant voltage of 9v.

The third resistor R3 is connected to the emitter of the third transistor Q3 with a resistance of 15k and is provided with a constant voltage of 9v.

The fourth resistor (R4) is a 15k resistor, one side is connected to the second resistor (R2) and the third resistor (R3) and the other side is connected to the emitter of the fourth transistor (Q4) to provide a constant voltage of 9v Receive.

The fifth resistor R5 is connected to the emitter of the fifth transistor Q5 with a resistance of 7.5k and one side is grounded.

The sixth resistor R6 receives a emitter current of the sixth transistor Q6 that is grounded on one side and has a current mirroring of a predetermined magnitude with a resistance of 15k.

The second transistor Q2 is a pnp type BJT transistor, and an emitter is connected to the second resistor R2 and a collector is connected to the comparator 300 and the condenser 400, and thus a current mirrored collector having a predetermined size. Provide current.

The third transistor Q3 is a pnp type BJT transistor and the emitter is connected to the third resistor R3 and provides a current mirrored collector current of a predetermined magnitude from the collector.

The fourth transistor Q4 is a pnp type BJT transistor, and an emitter is connected to the fourth resistor R4, and a base is connected to the base of the third transistor Q3 and the base of the fourth transistor Q4, and is a collector. The base and collector are connected to the ground from the connection point to provide a constant amount of constant current and base current to perform a current mirror function.

The fifth transistor Q5 is an npn type BJT transistor, in which a control current 123 is applied to a base to be connected to the condenser 400, and when a charged voltage is discharged, a constant current 210 is input from a collector. Provides twice the current mirrored emitter current 203 in a given magnitude.

The sixth transistor Q6 is an npn type BJT transistor that performs a current mirror function, receives the control current 123 from a base, _{induces a} voltage V _BE to a base, and has a predetermined magnitude of the third transistor Q3. The base and the collector are inputted at the connection point of the current mirrored collector current, and the base and the collector are connected to provide a base current at turn-on to provide a current mirrored emitter current of a predetermined magnitude.

The comparator 300 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, and a fifth resistor R7. It consists of 10 transistors Q10 and diode D1.

The seventh resistor R7 is a 30k resistor, and a constant voltage of 9v is applied to one side thereof.

The seventh transistor Q7 is an npn type transistor that performs a current mirror function, and the other side of the seventh resistor R7 is connected to the collector, and the base and the collector are connected by providing a base current and an emitter current.

As the diode D1, a positive terminal of the seventh transistor Q7 is connected in the forward direction and a negative terminal of the seventh transistor Q7 is connected to ground to receive the rectifier current of the seventh transistor Q7. It works.

The eighth resistor R8 is 7k resistor and one side of the eighth resistor R8 is grounded.

The ninth resistor R9 receives the constant voltage of 9v with a resistance of 12k.

The eighth transistor Q8 is a current mirrored npn type BJT transistor in which the emitter is connected to the other side of the eighth resistor R8 and the base is connected to the base of the seventh transistor Q7 so that the collector provides a comparison function. The emitter common current of the differential amplifier is provided and the base receives the mirrored base current of the seventh transistor Q7 to provide the current mirrored emitter current from the emitter to the eighth resistor R8. .

The ninth transistor Q9 is an npn type BJT transistor serving as a comparator. The collector is connected to one side of the ninth resistor R9, and the emitter is connected to the collector of the eighth transistor Q8. The voltage V _C1 charged and discharged from the capacitor 400 is compared with the comparison reference voltage V _B , and the voltage V _C1 charged and discharged from the capacitor 400 applied to the base is compared. When the value is less than the comparison reference voltage V _{B, the} signal is turned off and is turned on to provide the compared current 310 to the ninth resistor R9 at turn-on.

The tenth transistor Q10 is an npn type BJT transistor serving as a comparator, and a collector is applied with the constant voltage and the comparison reference voltage V _B is input to a base, and an emitter is a collector of the eighth transistor Q8. And a voltage V _C1 connected to an emitter of the ninth transistor Q9 and charged and discharged by the capacitor 400 applied to the base of the ninth transistor Q9 is the comparison reference voltage V _B. If less than), it is off, and if it is big, it provides emitter current to the emitter at turn-on.

The condenser unit 400 includes a capacitor C1.

The capacitor C1 receives a constant difference current 210 of the current mirror through a 30PF capacitor and provides a voltage V _{C1 that} is charged and discharged and charged and discharged.

The output unit 500 includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, an eleventh transistor Q11, and a twelfth transistor Q12. do.

The constant voltage of 9v is applied to one side of the tenth resistor R10 20k and the other side thereof is connected to the comparator 300.

9v = 6v의 비교기의 상기 비교 기준 전압(V_B)을 제10 트랜지스터(Q10)의 베이스로 제공한다.As the resistance of the eleventh resistor R11 40k, one side is connected to the other side of the tenth resistor R10 and the comparator 300, and the other side is grounded, thereby distributing the voltage with the tenth resistor R10.

The comparison reference voltage V _B of the comparator of 9v = 6v is provided to the base of the tenth transistor Q10.

One side of the twelfth resistor R12 40k is connected to the collector of the eleventh transistor Q11.

As a resistance of the thirteenth resistor R13 10k, one side is connected to the other side of the twelfth resistor R12 and the other side is grounded.

The eleventh transistor Q11 is a pnp type BJT transistor whose base is connected to the comparator 300 to receive the compared current 310, and the emitter is supplied with the constant voltage of 9v and provides a collector current to the collector. do.

The twelfth transistor Q12 is an npn type BJT transistor, the base of which is connected to the connection point of the twelfth resistor R12 and the thirteenth resistor R13 and the emitter is grounded, and receives a base current at turn-on to serve as an inverter. To output the vertical synchronization signal 511 to the collector.

Fig. 3 is a waveform diagram showing a composite synchronization signal of a field to be scanned on a television.

As described above, the television screen is composed of 30 frames per second, one frame is composed of the first feed and the second feed which are interlaced to the TV, and the first feed and the second feed have a pulse difference of 0.5H. And constitute the same pulse. The field to be scanned on the television is a horizontal synchronization signal at intervals of 1H (H: 63.5μs) in a horizontal scan period, a 3H-sized equalizing pulse with 6 pulses at 0.5H cycles, and 6 pulses at 0.5H cycles. It consists of a 3H-sized vertical sync signal, a 3H-sized equalization pulse with 6 pulses at 0.5H cycle, and a composite sync signal consisting of a horizontal sync pulse with a high pulse width of 4.7μs with 1H cycle.

The vertical sync separation circuit as shown in FIG. 2 is a vertical sync separation circuit that separates only the vertical sync signal from the composite sync signal including the vertical sync signal and the pull sync signal of the television or monitor. The composite synchronization signal input through the first resistor R ₁ is inputted with a waveform as shown in FIG. 3, and the operation of the vertical synchronization separation circuit is as follows.

x 9v = 6 v가 되며, 한편 8.6μA의 정전류원이 제공되어 전류 미러링의 기준 트랜지스터인 베이스와 컬렉터가 연결된 제4 트랜지스터(Q4)에 의해 미러링되는 트랜지스터인 제2 및 제3 트랜지스터(Q2, Q3)로 정전류원과 같은 컬럭터 전류가 미러링되며, 또한, 상기 미러링된 컬렉터 전류를 입력받아 베이스와 컬렉터가 연결된 제6 트랜지스터(Q6)의 에미터로 I만큼의 전류가 미러링되고, 제6 트랜지스터(Q6)에 의해 미러링되는 제5 트랜지스터(Q5)의 컬렉터로 제6 저항(R6)과 제5 저항(R5)의 저항비가 2 : 1 이므로 제5 트랜지스터(Q5)의 에미터로 2I만큼의 전류가 미러링된다.The reference voltage of the comparator composed of the ninth transistor Q9 and the tenth transistor Q10 by receiving the constant voltage of 9v is V _{B (Q10)} = by voltage distribution.

x 9v = 6 v, while the second and third transistors Q2 and Q3, which are transistors mirrored by a fourth transistor Q4 connected with a base and a collector, which is a reference transistor for current mirroring, are provided with a constant current source of 8.6 μA. Collector current, such as a constant current source, is mirrored, and as much as I is mirrored by the emitter of the sixth transistor Q6 to which the base and the collector are connected by receiving the mirrored collector current, and the sixth transistor ( Since the resistance ratio of the sixth resistor R6 and the fifth resistor R5 is 2: 1 as the collector of the fifth transistor Q5 mirrored by Q6), the current of 2I is increased by the emitter of the fifth transistor Q5. Mirrored.

I _C (Q2) = I _C (Q3) = I _C (Q4) = I = 8.6 μA

I _C (Q6) = I _C (Q3) = I = 8.6 μA

_{I C (Q5) = 2I C} (Q6) = 17.2 μA

On the other hand, in order to grasp the general basic function of the current mirroring in the vertical synchronous separation circuit will be described as shown in FIG. 7 is an N-output BJT current mirror circuit, in which a reference transistor (Q _REF ) of current mirroring connects a base and a collector, and inputs a constant current source I _REF at the top of the collector to the base and the collector. It is first, that each current mirror has the same V _bE 2 ... N transistors are connected with the base of (Q1, Q2 ... Q _N) mirrored to the collector of the transistor mirroring the respective output current _{I 1, I 2, I 3} ... And outputting the I _N when the following relationship.

I_E I _REF =

I _E

When there is only one transistor mirrored with the reference transistor Q _REF of current mirroring, the output current I ₁ inputted to the collector of the first transistor Q1 by inputting the constant current source I _REF to the base and the collector is as follows. .

I_E) =

I_E=

I_REF=

I ₁ = βI _B = β (

I _E ) =

I _E =

I _REF =

In general, when there are N transistors mirrored with the reference transistor Q _REF of current mirroring, the output current I ₁ , I ₂ , I ₃ . I _N is represented as follows.

I_REF≒ I_REF( ∵ β ≫ 1)I ₁ = I ₂ = I ₃ =… = I _N =

I _REF ≒ I _REF (∵ β ≫ 1)

Therefore, the reference transistor Q _REF of the current mirroring connecting the base and the collector outputs the mirrored current of approximately the same magnitude to the collector of the transistor mirrored by the constant current source I _REF inputted at the connection point of the base and the collector, respectively. do.

I) In the horizontal synchronizing signal period, since the first transistor Q1 is saturated, the fifth transistor Q5 and the sixth transistor Q6 are turned off, and the second transistor Q2 and the third transistor ( Q3) and the fourth transistor Q4 are turned on and the collector current I _C (Q2) = I of the second transistor Q2 is charged through the capacitor C1.

However, since the pulse width of the horizontal synchronizing signal is 4.7 μs, the voltage charged in the capacitor C1 is V _C1 = It / C = (8.6 uA x 4.7 μs) / 30 pf = 1.35 v, so that the ninth transistor Q9 of the comparator is used. Is off, and the tenth transistor Q10 is turned on. Accordingly, the eleventh transistor Q11 is turned off, the twelfth transistor Q12 serving as an inverter is turned off, and the vertical synchronous output is made high.

II) In the period other than the horizontal synchronization signal, since the first transistor Q1 is turned off, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, and the sixth transistor ( Q6) is on. Therefore, the current difference I between I _C (Q2) and I _C (Q5) flows from the capacitor voltage V _C1 and the capacitor C1 discharges. Therefore, the ninth transistor Q9 serving as a comparator is turned off, the tenth transistor Q10 is turned on, the eleventh transistor Q11 is turned off, the twelfth transistor Q12 is turned off, and the vertical synchronous output is high. Becomes The result of the horizontal synchronizing signal period and the period other than the horizontal synchronizing signal is shown graphically to represent a waveform as shown in FIG.

4 illustrates output voltages of a voltage and a vertical synchronization signal that are charged and discharged in a capacitor in the horizontal synchronization signal section of FIG. 3.

= 0.7 v 까지 충전되며, 등화 펄스 이외의 기간은 I_C(Q2)과 I_C(Q5)의 전류차 I만큼 커패시터(C1)를 통해 방전되므로 비교기의 제9 트랜지스터(Q9)는 오프, 제10 트랜지스터(Q10)는 온, 제11 트랜지스터(Q11)는 오프, 제12 트랜지스터(Q12)도 오프가 되어 수직 동기 출력은 항상 하이 상태가 된다. 이 상태를 그림으로 도시하면 도 5와 같이 등화 펄스 구간에 커패시터의 충전 및 방전되는 전압 및 수직 동기 신호의 출력 파형이 표시되게 된다.III) The equalizing pulse period is similar to the horizontal synchronizing signal period, and the pulse period is charged through capacitor C1 with I _C (Q2) = 8.6 μA, where the equalizing pulse width is 25 μs, so Vc =

= 0.7 v, and the period other than the equalizing pulse is discharged through the capacitor C1 by the current difference I between I _C (Q2) and I _C (Q5), so that the ninth transistor Q9 of the comparator is turned off, the tenth. The transistor Q10 is turned on, the eleventh transistor Q11 is turned off, and the twelfth transistor Q12 is also turned off so that the vertical synchronous output is always in a high state. If this state is shown as a picture, as shown in FIG. 5, the output waveforms of the voltage and the vertical synchronization signal that are charged and discharged in the capacitor are displayed in the equalizing pulse section.

IV) The vertical signal synchronization period is because the charging time for the capacitor C1 is greater than the discharge time, when V _C1 is greater than the comparison reference voltage 6v of the comparator, the tenth transistor Q10 is turned off, and the ninth transistor Q9 ) Is turned on and the eleventh transistor Q11 is turned on and the twelfth transistor Q12 serving as an inverter becomes saturation so that the output of the vertical synchronization signal is low. The output waveform of the vertical synchronizing signal through the vertical synchronizing separation circuit is input as shown in FIG. 3 by combining the above-described results of I), II), III), and IV). As described above, the waveform of the vertical synchronization signal separated from the composite synchronization signal can be obtained.

As a result, a fourth transistor connected to the base and the collector, which is a reference for current mirroring, is applied with a constant voltage of 9v inside by receiving a complex sync signal including a horizontal sync signal, an equalization pulse, and a vertical sync signal from an input terminal. Current mirrored from Q6 and the sixth transistor Q6 to mirror the collector currents 273 and 283 equal to I through the second and third transistors Q2 and Q3, respectively, and 2I to the fifth transistor Q5. The collector current 201 is mirrored so that the current difference by I between the collector current 273 of the second transistor Q2 and the collector current 201 of the fifth transistor Q5 is converted into the capacitor C1 by the capacitor C1. The voltage V _C1 charged to the capacitor and supplied to the capacitor is input to the base of the ninth transistor Q9 serving as a comparator. The time for charging and discharging the capacitor (V _C1 ) to 6v, the reference voltage (V _B ) of the comparator, is t = (C x V) / 8.6 uA = 21 μs and V _C1 is 9v-V _{CEsat (Q7 )} ≒ 8.8 v the second charge from, the capacitor (C1) as to greater than the reference voltage (V _B) of the comparator 6v a ninth transistor (Q9) is is turned on discharges the current difference as long as the I station to And a fifth transistor.

x 9v = 6 v가 되어, 제10 트랜지스터(Q10)의 비교되는 6v의 기준 전압(V_B)과 제9 트랜지스터(Q9)의 커패시터에 충전되는 전압(V_C1)가 비교되어, V_B> V_C1면 제10 트랜지스터(Q10)가 온되고 제9 트랜지스터(Q9)는 오프되어 제11 트랜지스터(Q11)는 오프, 인버터 역할을 수행하는 제12 트랜지스터(Q12)는 오프되어 출력은 하이 값이 되고, V_B< V_C1면 제10 트랜지스터(Q10)가 오프되고 제9 트랜지스터(Q9)는 온되어 제11 트랜지스터(Q11)는 온, 인버터 역할을 수행하는 제12 트랜지스터(Q12)는 온되어 로우 값이 되어 복합 동기 신호로부터 수직 동기 신호를 분리할 수 있게 된다.The reference comparison voltage V _B of the comparator applied to the base of the tenth transistor Q10 is inputted with the voltage of 9v to V _{B (Q10)} by voltage distribution.

x 9v = 6 v, and the reference voltage V _B of 6v compared to the tenth transistor Q10 and the voltage V _C1 charged to the capacitor of the ninth transistor Q9 are compared, and V _B > V _C1 if the tenth transistor (Q10) is turned on and the ninth transistor (Q9) is turned off the eleventh transistor (Q11) is a twelfth transistor (Q12) to perform the off-inverter role is turned off the output is at a high value, When V _B <V _C1 , the tenth transistor Q10 is turned off, the ninth transistor Q9 is turned on, the eleventh transistor Q11 is turned on, and the twelfth transistor Q12 serving as an inverter is turned on to have a low value. The vertical synchronization signal can be separated from the composite synchronization signal.

Therefore, according to the above configuration, the composite synchronization signal including the horizontal synchronization signal, the equalizing pulse, and the vertical synchronization signal of the feed scanned by the television is input and passes through the vertical synchronization separation circuit to output the vertical synchronization signal separated from the composite synchronization signal. can do.

As described above, according to the vertical synchronizing separation circuit according to the present invention, a composite synchronizing signal including a horizontal synchronizing signal and a vertical synchronizing signal in a signal scanned to a television or a monitor is input, rather than using a conventional RC discrete element, Because of the integrated circuit, it is possible to implement an improved vertical synchronous separation circuit in which only vertical synchronous signals are separated more stably.

Although this invention was demonstrated concretely by the said Example, this invention is not restrict | limited by this, A deformation | transformation and improvement are possible within the normal knowledge of a person skilled in the art.

Claims (6)

An input unit 100 for receiving a complex synchronization signal 110 including a horizontal synchronization signal, a vertical synchronization signal, and an equalization pulse from the input terminal 103 to provide a control current 123; A constant current unit 200 for receiving the control current 123 to provide a constant difference current 210 of the current mirror; A comparator 300 configured to receive a constant difference current 210 and a comparison reference voltage V _{B of} the current mirror to provide a constant difference current 210 and a compared current 310 of the current mirror; A condenser unit 400 for receiving a constant difference current 210 of the current mirror to provide a voltage V _C1 charged and discharged from a capacitor _C1 ; And And an output unit 500 for receiving the compared current 310 and outputting the vertical reference signal 511 separated from the comparison reference voltage V _B and the composite synchronization signal to the output terminal 603. Vertical sync separation circuit that separates the vertical sync signal from the composite sync signal. The method of claim 1, wherein the input unit 100, A first resistor (R1) for receiving the composite synchronization signal (110) from the input terminal (103); And A vertical synchronizing signal in the composite synchronizing signal, characterized in that the base is connected to the first resistor (R1), the emitter is grounded and the npn type BJT first transistor (Q1) for providing the control current 123 to a collector. Vertical synchronous separation circuit. The method of claim 1, wherein the constant current unit 200, A second resistor R2 receiving a constant voltage; A third resistor R3 receiving the constant voltage; A fourth resistor R4 provided with the constant voltage; An emitter is connected to the second resistor R2 and a collector is connected to the comparator 300 and the condenser 400 to provide a pnp type BJT second transistor Q2 for providing a current mirrored collector current of a predetermined magnitude. ); The emitter includes: a pnp type BJT third transistor Q3 connected to the third resistor R3 for providing a current mirrored collector current of a predetermined magnitude from the collector; The emitter is connected to the fourth resistor R4 and the base is connected to the base of the third transistor Q3 and the base of the fourth transistor Q4, and the collector has a predetermined size by connecting the base and the collector to the ground from the connection point. A pnp-type BJT fourth transistor Q4 that provides a constant current and a base current to perform a current mirror function; The control current 123 is applied to the base and is connected to the condenser 400, and when the charged voltage is discharged, the constant current 210 is inputted from the collector to the current mirrored emitter current twice the predetermined magnitude ( A current mirrored npn type BJT fifth transistor Q5 for providing 203; When the control current 123 is input from the base, the voltage V _BE is induced to the base, and the base and the collector receive the current mirrored collector current of a predetermined magnitude of the third transistor Q3 at the connection point and turn on. An npn type BJT sixth transistor Q6 providing a base current to the base mirror to provide a current mirrored emitter current of a predetermined size, and to perform a current mirror function connected to the collector; One side includes a fifth resistor (R5) for receiving the emitter current of the fifth transistor (Q5) of twice the size of the constant current source is grounded and current mirrored; And The vertical sync separation of the vertical sync signal separated from the vertical sync signal, characterized in that the one side is composed of a sixth resistor (R6) for receiving the emitter current of the sixth transistor (Q6) is grounded and a current mirror of a certain magnitude. Circuit. The method of claim 1, wherein the comparison unit 300, A seventh resistor (R7) to which the constant voltage is applied to one side; An npn-type seventh transistor Q7 connected to the other side of the seventh resistor R7 and providing a base current and an emitter current to perform a current mirror function connected to the base and the collector; The diode D1 receives the emitter current of the seventh transistor Q7 and rectifies by connecting the positive terminal side of the seventh transistor Q7 to the positive terminal in the forward direction and the negative side to ground. ); One side of the eighth resistor R8 grounded; A ninth resistor R9 provided with the constant voltage; The emitter is connected to the other side of the eighth resistor R8 and the base is connected to the base of the seventh transistor Q7 so that the collector is provided with the emitter common current of the differential amplifier functioning and the base A current mirrored npn type BJT eighth transistor Q8 for receiving a mirrored base current of a seventh transistor Q7 to provide a current mirrored emitter current from the emitter to the eighth resistor R8; The collector is connected to one side of the ninth resistor R9, the emitter connects the collector of the eighth transistor Q8, and inputs a voltage V _C1 charged and discharged to the capacitor 400 from a base. Is compared with the comparison reference voltage V _B , and when the voltage V _C1 charged and discharged in the capacitor unit 400 applied to the base is smaller than the comparison reference voltage V _B , it is turned off, and when it is large, it is turned on. An npn type BJT ninth transistor Q9 serving as a comparator for providing the compared current 310 to the ninth resistor R9 at turn-on; And The collector is applied with the constant voltage and the comparison reference voltage V _B is input to the base, and the emitter is connected to the collector of the eighth transistor Q8 and the emitter of the ninth transistor Q9, so that the ninth When the voltage V _C1 charged and discharged in the capacitor 400 applied to the base of the transistor Q9 is smaller than the comparison reference voltage V _B , the voltage is turned off when the voltage V _C1 is smaller than the comparison reference voltage V _B , and the emitter is turned on when the emitter is turned on A vertical sync separation circuit comprising a vertical sync signal separated from a complex sync signal, comprising a npn type BJT tenth transistor (Q10) serving as a comparator for providing a current. The method of claim 1, wherein the condenser 400, Vertical sync separation circuit that separates the vertical sync signal from the composite sync signal, characterized in that it consists of a capacitor (C1) for providing a voltage (V _C1 ) is charged and discharged by receiving a constant difference current 210 of the current mirror . The method of claim 1, wherein the output unit 500, A tenth resistor (R10) connected at one side to the constant voltage and at the other side to the comparator 300; One side is connected to the other side of the tenth resistor R10 and the comparator 300, and the other side is grounded to provide the comparison reference voltage V _B by voltage distribution with the tenth resistor R10. Resistor R11; A base is connected to the comparator 300 to receive the compared current 310, and the emitter is a pnp type BJT eleventh transistor Q11 for applying the constant voltage and providing a collector current to a collector; One side includes a twelfth resistor R12 connected to the collector of the eleventh transistor Q11; A thirteenth resistor R13 connected to the other side of the twelfth resistor R12 and grounded on the other side thereof; And The base is connected to the connection point of the twelfth resistor (R12) and the thirteenth resistor (R13) and the emitter is grounded, and receives a base current at turn-on to serve as an inverter to output a vertical synchronization signal 511 to a collector. A vertical sync separation circuit comprising a vertical sync signal separated from a complex sync signal comprising an npn type BJT twelfth transistor (Q12).

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