KR100242388B1 - Internal Clock Signal Generation Circuit - Google Patents
Internal Clock Signal Generation Circuit Download PDFInfo
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- KR100242388B1 KR100242388B1 KR1019970036114A KR19970036114A KR100242388B1 KR 100242388 B1 KR100242388 B1 KR 100242388B1 KR 1019970036114 A KR1019970036114 A KR 1019970036114A KR 19970036114 A KR19970036114 A KR 19970036114A KR 100242388 B1 KR100242388 B1 KR 100242388B1
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Abstract
외부에서 입력되는 넓은 범위의 클럭신호를 효과적으로 모델링하여 내부 클럭신호를 출력시킬 수 있는 내부 클럭신호 발생회로는 입력되는 외부 클럭신호(CLOCK_IN)의 주기가 변하여 로킹(LOCKING)범위가 넓어져도 추가의 지연단이 필요없도록 하기 위하여 외부 클럭신호(CLOCK_IN)를 일정한 지연을 가지는 지연 클럭신호(CLOCK_IND)를 출력하는 지연 회로부를 추가하여 지연단(Delay Stage)을 추가하지 않고 로킹(LOCKING)범위를 넓게 만들 수 있으므로 레이아웃 면적과 메모리칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time) 및 전류소비를 줄일 수 있다.The internal clock signal generation circuit that can effectively model a wide range of clock signals input from the outside and output the internal clock signal has an additional delay even when the locking range is widened due to the change in the period of the external clock signal CLOCK_IN. In order to eliminate the need for a stage, a delay circuit that outputs a delayed clock signal CLOCK_IND with a constant delay to the external clock signal CLOCK_IN can be added to make the locking range wider without adding a delay stage. Therefore, the clock access time and current consumption until outputting the layout area and the data of the memory chip can be reduced.
Description
본 발명은 내부 클럭신호 발생회로에 관한 것으로서, 특히 외부에서 입력되는 넓은 범위의 클럭신호를 효과적으로 모델링하여 내부 클럭신호를 출력시킬 수 있는 내부 클럭신호 발생회로에 관한 것이다.The present invention relates to an internal clock signal generation circuit, and more particularly, to an internal clock signal generation circuit capable of outputting an internal clock signal by effectively modeling a wide range of clock signals input from the outside.
메모리 소자의 기술이 점차 발전함에 따라 메모리칩의 동작속도가 점점 고속화 되어가고 있다.As the technology of the memory device is gradually developed, the operating speed of the memory chip is getting faster.
그러나 외부의 클럭신호를 입력받아 메모리칩을 동작시키기에 적당한 내부 클럭신호를 발생시키기까지는 일정한 지연시간을 가지므로 외부의 클럭신호로부터 메모리칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time)을 줄이는 데는 한계가 있다.However, since it has a certain delay time to receive an external clock signal and generate an internal clock signal suitable for operating the memory chip, the clock access time from the external clock signal to outputting the data of the memory chip. There is a limit to the reduction.
이러한 한계를 개선하기 위하여 PLL(Phase Locked Loop) 또는 DLL(Delay Locked Loop)를 이용하여 외부 클럭신호와 내부 클럭신호의 지연시간을 줄이거나 내부 클럭신호를 외부 클럭신호보다 좀더 빠르게 하여 매우 빠른 클럭 억세스 타임(clock access time)을 얻을 수 있다.To solve this limitation, PLL (Phase Locked Loop) or DLL (Delay Locked Loop) is used to reduce the delay time of external clock signal and internal clock signal or to make the internal clock signal faster than external clock signal for very fast clock access. You can get the clock access time.
제1도는 종래의 내부 클럭신호 발생회로도이고, 제2도는 제1도의 클럭신호 발생회로의 타이밍도이다.FIG. 1 is a conventional internal clock signal generation circuit diagram, and FIG. 2 is a timing diagram of the clock signal generation circuit of FIG.
입력되는 외부 클럭신호(CLOCK_IN)는 직렬로 연결된 제1~제n 지연단(Delay Stage 1~Delay Stage n)중 제1 지연단(Delay Stage 1)의 입력과 각각의 플립플릅(FF1~FFn)의 클럭신호(CLK) 그리고 제1 N형 트랜지스미션 스위치(TG1)의 입력에 인가되고, 제1 N형 트랜스미션 스위치(TG1)와 제1 P형 트랜스미션 스위치(/TG1)는 게이트가 접지되고 출력단이 공동으로 내부 클럭신호(CLOCK_OUT)를 출력한다.The input external clock signal CLOCK_IN is input from the first delay stage (Delay Stage 1) of the first to n th delay stages (Delay Stage 1) connected in series with each flip-flop (FF1 to FFn). Is applied to the clock signal CLK and the input of the first N-type transmission switch TG1. The first N-type transmission switch TG1 and the first P-type transmission switch / TG1 have a gate grounded and an output terminal. This joint outputs the internal clock signal CLOCK_OUT.
각각의 제1~제n 지연단(Delay Stage 1~Delay Stage n) 사이 사이의 출력인 클럭_데이타(CLOCK_Di)는 각각 제1~제n 플립플롭(FF1~FFn)의 데이터(D)와 제2~제n+1 N형 트랜스미션 스위치(TG2~TGn+1)의 입력에 인가된다. 상기 제1~제n 플립플롭(FF1~FFn)의 출력(Q1~Qn)은 각각 제1~제n 인버터(INV1~INVn)를 거쳐 반전되어 각각의 제1~제n 노어게이트(NOR1~NORn)에 입력되고 제2~제n+1 플립플롭(FF1~FFn+1)의 출력(Q2~Qn+1)은 바로 각각의 제1~제n 노어게이트(NOR1~NORn)에 입력된다. 상기 제1~제n 노어게이트(NOR1~NORn)의 출력은 제2~제n+1 N형 트랜스미션 스위치(TG2~TGn+1)와 제2~제n+1 P형 트랜스미션 스위치(TG2~TGn+1)의 게이트 신호로 각각 입력된다. 상기 제2~제n+1 N형 트랜스미션 스위치(TG2~TGn+1)와 제2~제n+1 P형 트랜스미션 스위치(/TG2~/TGn+1)의 출력은 제1~제n P형 트랜스미션 스위치의 입력으로 인가된다.The clock_data CLOCK_Di, which is an output between the first to nth delay stages (Delay Stage 1 to Delay Stage n), is the data D and the first to nth flip-flops FF1 to FFn, respectively. It is applied to the inputs of the 2nd to n + 1N type transmission switches (TG2 to TGn + 1). The outputs Q1 to Qn of the first to nth flip-flops FF1 to FFn are inverted through the first to nth inverters INV1 to INVn, respectively, to respectively the first to nth NOR gates NOR1 to NORn. ) And the outputs Q2 to Qn + 1 of the second to n + 1 flip-flops FF1 to FFn + 1 are directly input to the respective first to n-th NOR gates NOR1 to NORn. Outputs of the first to n-th NOR gates NOR1 to NORn include second to n + 1N-type transmission switches TG2 to TGn + 1 and second to n + 1 P-type transmission switches TG2 to TGn. It is input to the gate signal of +1), respectively. The outputs of the second to n + 1 N-type transmission switches (TG2 to TGn + 1) and the second to n + 1 P-type transmission switches (/ TG2 to / TGn + 1) are first to n-th P-type. It is applied to the input of the transmission switch.
제2도의 타이밍도에 나타낸 클럭_데이타(CLOCK_Di)는 입력되는 외부 클럭신호(CLOCK_IN)를 제1~제n 지연단(Delay Stage 1~Delay Stage n)에서 지연시킨 신호이다. 이 클럭_데이타(CLOCK_Di)가 외부 클럭신호(CLOCK_IN)에 클럭킹(clocking)되어 플립플롭의 출력인 Qi가 발생된다.The clock_data CLOCK_Di shown in the timing diagram of FIG. 2 is a signal obtained by delaying the input external clock signal CLOCK_IN in the first to nth delay stages (Delay Stage 1 to Delay Stage n). The clock data CLOCK_Di is clocked to the external clock signal CLOCK_IN to generate Qi, which is an output of the flip-flop.
제2도를 참조하면, 시간 TO에서 제1 플립플롭(FF1)과 제2 플립플롭(FF2)의 출력인 Q1과 Q2는 “LOW”, 제3 플립플롭(FF3)과 제4 플립플롭(FF4)의 출력인 Q3과 Q4는 “HIGH”, 제5 플립플롭(FF5)과 제6 플립플롭(FF6) 및 제7 플립플롭(FF7)의 출력인 Q5와 Q6 및 Q7은 “LOW”로 세팅된다. 따라서 비교로직(comparision logic)에 의해 제4 클럭_데이타(CLOCK_D4)에 연결된 제5 N형 트랜스미션 스위치(TG5)가 턴 온 되고 제5 P형 트랜스미션 스위치(/TG 5)에 제4 클럭_데이타(CLOCK_D4)가 인가된 후, 제5 P형 트랜스미션 스위치(/TG 5)가 턴 온 될 때 내부 클럭신호(CLOCK_OUT)로서 제4 클럭_데이타(CLOCK_D4)를 출력한다.Referring to FIG. 2, Q1 and Q2, which are outputs of the first flip-flop FF1 and the second flip-flop FF2 at time TO, are “LOW”, the third flip-flop FF3, and the fourth flip-flop FF4. Q3 and Q4, which are the outputs of the Q1, Q5 and Q6 and Q7, which are the outputs of “HIGH”, the fifth flip-flop FF5 and the sixth flip-flop FF6, and the seventh flip-flop FF7, are set to “LOW”. . Accordingly, the fifth N-type transmission switch TG5 connected to the fourth clock data CLOCK_D4 is turned on by comparison logic, and the fourth clock_data (5) is connected to the fifth P-type transmission switch / TG 5. After the CLOCK_D4 is applied, the fourth clock_data CLOCK_D4 is output as the internal clock signal CLOCK_OUT when the fifth P-type transmission switch / TG 5 is turned on.
즉, 외부 클럭신호(CLOCK_IN)가 상승(rising)할 때 클럭_데이타(CLOCK_Di) 신호가 “LOW”가 되면 플립플롭의 출력신호 Qi가 “LOW”가 되므로 Qi-1이 “HIGH”이고 Qi가 “LOW”인 스테이지의 클럭_데이타(CLOCK_Di)가 외부 클럭신호(CLOCK_IN)와 거의 같은 타이밍이 된다. 따라서 Qi-1이 제n-1 인버터(INVn-1)에 의해 반전된 신호 “LOW”와 Qi신호 “LOW”가 제n-1 노어게이트(NOR1)에 입력되어 “HIGH”신호를 출력하여 제n N형 트랜스미션 스위치(TG n)를 턴 온 시키면 외부 클럭신호(CLOCK_IN)가 임의의 시간만큼 지연된 클럭_데이타(CLOCK_Di) 신호 즉, 제4 클럭_데이타(CLOCK_D4) 신호를 외부 클럭신호(CLOCK_IN)보다 빠른 내부 클럭신호(CLOCK_OUT)로 출력시킬 수 있다. 상기에서 n=i이다.That is, when the clock_data signal CLOCK_Di becomes "LOW" when the external clock signal CLOCK_IN rises, the output signal Qi of the flip-flop becomes "LOW", so Qi-1 is "HIGH" and Qi is The clock_data (CLOCK_Di) of the stage which is "LOW" is at the same timing as the external clock signal (CLOCK_IN). Accordingly, the signal “LOW” and Qi signal “LOW” in which Qi-1 is inverted by the n-1 inverter INVn-1 are inputted to the n-1 NOR gate NOR1 to output a “HIGH” signal. When the n-type transmission switch (TG n) is turned on, the clock_data (CLOCK_Di) signal, in which the external clock signal (CLOCK_IN) is delayed by a predetermined time, that is, the fourth clock_data (CLOCK_D4) signal is converted into the external clock signal (CLOCK_IN). Can be output as a faster internal clock signal (CLOCK_OUT). Where n = i.
상기 종래의 회로가 로킹(LOCKING)할 수 있는 범위는 7개의 지연단에 의하여 결정되므로 좀더 넓은 로킹(LOCKING) 범위를 가지려면 지연단(Delay Stage)과 이에 따르는 플립플롭(FF)과 인버터(INV)와 트랜스미션 스위치(TG, /TG)와 노어게이트(NOR)를 추가하여야 한다.Since the range in which the conventional circuit can be locked is determined by seven delay stages, a delay stage, a flip-flop (FF), and an inverter (INV) may be used to have a wider locking range. ), Transmission switches (TG, / TG) and NOR gates (NOR) should be added.
그러나 이러한 방법은 외부 클럭신호(CLOCK_IN)와 내부 클럭신호(CLOCK_OUT)를 로킹(LOCKING)시키기까지 많은 수의 클럭 사이클이 필요하므로 외부의 클럭신호로 부터 메모리칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time)이 길어지고, 잠시동안 외부 클럭신호(CLOCK_IN)가 없는 대기상태에서도 회로를 “온”시켜야 하기 때문에 전류소비가 많다는 문제점을 갖는다.However, this method requires a large number of clock cycles to lock the external clock signal CLOCK_IN and the internal clock signal CLOCK_OUT, so the clock access time from the external clock signal to outputting the data of the memory chip. (clock access time) is long, the current consumption is high because the circuit has to be "on" even in the standby state without the external clock signal (CLOCK_IN) for a while.
따라서 본 발명의 목적은 외부 클럭신호가 로킹 범위가 넓어도 효과적으로 모델링하여 외부의 클럭신호로부터 메모리칩의 데이터를 출력하기까지의 클럭 억세스타임(clock access time)이 길어지지 않으며, 잠시동안 외부 클럭신호(CLOCK_IN)가 없는 대기상태에서도 회로를 “오프”시켜 전류소비를 줄일 수 있는 내부 클럭신호 발생회로를 제공하는 데 있다.Accordingly, an object of the present invention is that even if the external clock signal has a wide locking range, the clock access time from the external clock signal to the data output from the memory chip is not long, and the external clock signal is short for a while. The present invention provides an internal clock signal generation circuit that can reduce current consumption by “off” the circuit even in a standby state without (CLOCK_IN).
상기 목적을 달성하기 위한 본 발명에 따른 내부 클럭신호 발생회로는 지연단(Delay Stage)과 플립플롭과 노어게이트와 삼상태 버퍼와 삼상태 인버터 및 외부클럭신호(CLOCK_IN)의 주기가 변하여 로킹(LOCKING)범위가 넓어도 추가의 지연단을 설치 할 필요가 없는 지연 회로부를 포함한다.In order to achieve the above object, the internal clock signal generation circuit according to the present invention has a delay stage, a flip-flop, a NOR gate, a tristate buffer, a tristate inverter, and an external clock signal CLOCK_IN. It also includes a delay circuit section that, even with a wide range, does not require the installation of additional delay stages.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 종래의 내부 클럭신호 발생회로도.1 is a conventional internal clock signal generation circuit diagram.
제2도는 종래의 내부 클럭신호 발생회로의 타이밍도.2 is a timing diagram of a conventional internal clock signal generation circuit.
제3도는 본 발명에 따른 내부 클럭신호 발생회로도.3 is an internal clock signal generation circuit diagram according to the present invention.
제4도는 본 발명에 따른 내부 클럭신호 발생회로의 타이밍도.4 is a timing diagram of an internal clock signal generation circuit according to the present invention.
제4(a)도는 CLOCK-IN이 지연단에 의한 로킹(locking)범위 내에 있을 때.4 (a) is when CLOCK-IN is within the locking range by the delay stage.
제4(b)도는 CLOCK-IN이 지연단에 의한 로킹(locking)범위 내에 없을 때.4 (b) is when CLOCK-IN is not within the locking range by the delay stage.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
100 : 지연 회로부100: delay circuit
제3도는 본 발명에 따른 내부 클럭신호 발생회로도이고 제4도는 본 발명에 따른 내부 클럭신호 발생회로의 타이밍도이다.3 is an internal clock signal generation circuit diagram according to the present invention, and FIG. 4 is a timing diagram of an internal clock signal generation circuit according to the present invention.
본 발명에 따른 내부 클럭신호 발생회로는 외부 클럭신호(CLOCK_IN)를 입력받는 지연회로(100) 및 상기 지연회로(100)에 직렬로 연결된 제1~제7 지연단(Delay Stage 1~delay Stage 7)과 외부 클럭신호(CLOCK_IN)를 클럭신호(CLK)로 하여 제1~제7지연단(Delay Stage 1~Delay Stage 7)의 출력을 클럭_데이타(CLOCK_Di)로 입력받는 각각의 제1~제6 플립플롭(FF1~FF6)과, 상기 제1~제6 플립플롭(FF1~FF6)중 홀수 번째 플립플롭(FF2n-1)의 출력(Q2n-1)은 각각의 제1~제5 인버터(INV1~INV5)중 홀수 번째 인버터(INV2n-1)에 입력되고 짝수 번째 플립플롭(FF2)의 출력(Q2n)은 짝수 번째 인버터(INV2n)에 입력되며, 홀수 번째 지연단(Delay Stage 2n-1)의 출력은 각각의 제1~제3 삼상태 인버터(TSI1~TSI3)에 입력되고 짝수 번째 지연단(Delay Stage 2n)은 출력은 각각의 제1~제4 삼상태 버퍼(TSB1~TSB4)에 인가되며, 상기 제1~제5 인버터(INV1~INV5)의 출력과 제2~제6의 플립플롭(FF2~FF6)의 출력은 각각 제1~제5 노어게이트(NOR1~NOR5)에 입력되고, 상기 제1~제5 노어게이트(NOR1~NOR5)의 출력은 제1~제5/선택스위치(/G1~G5) 및 제2~제6 선택스위치(G2~G6)에 인가되고 제1 선택스위치(G1)는 접지된다.The internal clock signal generation circuit according to the present invention includes a
제1~제7 /선택스위치(/G1~/G7)와 제1~제7 선택스위치(G1~G7)는 각각 쌍을 이루어 제1~제4 삼상태 버퍼(TSB1~TSB4)와 제1~제3 삼상태 인버터(TSI1~TSI3)에 번갈아 동작신호를 인가하고 제1~제4 삼상태 버퍼(TSB1~TSB4)와 제1~제4 삼상태 인버터(TSI1~TSI3)의 출력이 공동으로 내부 클럭신호(CLOCK_OUT)를 출력한다.The first to seventh / selection switches / G1 to / G7 and the first to seventh selection switches G1 to G7 are paired, respectively, to the first to fourth tri-state buffers TSB1 to TSB4 and the first to seventh. The operation signal is alternately applied to the third tri-state inverters TSI1 to TSI3, and the outputs of the first to fourth tri-state buffers TSB1 to TSB4 and the first to fourth tri-state inverters TSI1 to TSI3 are jointly internal. Output the clock signal CLOCK_OUT.
상기 각각의 지연단(Delay Stage)은 하나인 인버터로 구성된다.Each of the delay stages includes one inverter.
본 발명의 내부 클럭신호 발생회로의 동작을 두 가지로 나누어 설명한다.The operation of the internal clock signal generation circuit of the present invention will be described in two ways.
먼저, 제4(a)도는 CLOCK_IN이 지연단에 의한 로킹(locking)범위 내에 있는 경우에 대한 타이민도이다.First, FIG. 4 (a) is a timing diagram for a case where CLOCK_IN is within a locking range by a delay stage.
제4(a)도에서와 같이, 외부 클럭신호(CLOCK_IN)의 주기가 지연단(Delay Stage) 전체의 지연주기보다 작은 경우에는 외부 클럭신호(CLOCK_IN)가 지연회로(100)에서 미리 일정한 지연주기를 가져 시간 T1~T2 사이에서 지연 클럭신호(CLOCK_IND)를 출력한다.As shown in FIG. 4 (a), when the period of the external clock signal CLOCK_IN is smaller than the delay period of the entire delay stage, the external clock signal CLOCK_IN is delayed in advance in the
시간 T2에서 제1 플립플롭(FF1)과 제2 플립플롭(FF2)의 출력인 Q1과 Q2는 “LOW”, 제3 플립플롭(FF3)과 제4 플립플롭(FF4)의 출력인 Q3과 Q4는 “HIGH”, 제5 플립플롭(FF5)의 출력인 Q5는 “LOW”가 된다.Q1 and Q2, which are the outputs of the first flip-flop FF1 and the second flip-flop FF2, are "LOW" at time T2, and Q3 and Q4, which are the outputs of the third flip-flop FF3 and the fourth flip-flop FF4. Is "HIGH", Q5 which is the output of the fifth flip-flop FF5 is "LOW".
시간 T2에서 제4 클럭_데이타(CLOCK_D4)가 클럭_데이타(CLOCK_Di)의 지연시간에 의하여 순차적으로 제1~제4 삼상태 버퍼(TSB1~TSB4)와 제1~제3 삼상태 인버터(TSI1~TSI3)를 번갈아 동작시켜 내부 클럭신호(CLOCK_OUT)로 출력된다.At time T2, the fourth clock data CLOCK_D4 sequentially rotates the first through fourth tri-state buffers TSB1 through TSB4 and the first through third tri-state inverters TSI1 through the delay time of the clock data CLOCK_Di. TSI3) are alternately operated and output as the internal clock signal CLOCK_OUT.
즉, 외부 클럭신호(CLOCK_IN)가 시간 T1에 로킹(LOCKING)되지 않고 시간 T2에서 로킹(LOCKING)되어 제4 클럭_데이타(CLOCK_D4)를 내부 클럭신호(CLOCK_OUT)로서 출력하게 된다.That is, the external clock signal CLOCK_IN is not locked at time T1 but is locked at time T2 to output the fourth clock data CLOCK_D4 as the internal clock signal CLOCK_OUT.
제4(b)도는 CLOCK_IN이 지연단에 의한 로킹(locking) 범위 내에 없을 때의 타이밍도이다.4 (b) is a timing diagram when CLOCK_IN is not within the locking range by the delay stage.
제4(b)도에 도시된 바와 같이, 외부 클럭신호(CLOCK_IN)의 주기가 지연단(Delay Stage) 전체의 지연주기보다 큰 경우에는 외부 클럭신호(CLOCK_IN)가 지연회로(100)를 통하여 일정한 지연주기를 가지는 지연 클럭신호(CLOCK_IND)를 출력하더라도 내부 클럭신호(CLOCK_OUT)가 시간 T1에서 로킹되어 제4 클럭_데이타(CLOCK_D4)를 출력하게 된다.As shown in FIG. 4 (b), when the period of the external clock signal CLOCK_IN is greater than the delay period of the entire delay stage, the external clock signal CLOCK_IN is fixed through the
따라서 본 발명은 외부 클럭신호(CLOCK_IN)를 일정한 지연을 가지는 지연 클럭신호(CLOCK_IND)를 만들어 지연단(Delay Stage)을 추가하지 않고 로킹(LOCKING) 범위를 넓게 만들 수 있으므로 레이아웃 면적과 메모리칩의 데이터를 출력하기까지의 클럭 억세스 타임(clock access time) 및 전류소비를 줄일 수 있다.Therefore, the present invention can make the external clock signal CLOCK_IN delay clock signal CLOCK_IND having a constant delay, thereby making it possible to widen the locking range without adding a delay stage. The clock access time and current consumption until the output can be reduced.
Claims (2)
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| KR1019970036114A KR100242388B1 (en) | 1997-07-30 | 1997-07-30 | Internal Clock Signal Generation Circuit |
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| KR1019970036114A KR100242388B1 (en) | 1997-07-30 | 1997-07-30 | Internal Clock Signal Generation Circuit |
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