[go: up one dir, main page]

KR100242381B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
KR100242381B1
KR100242381B1 KR1019960075720A KR19960075720A KR100242381B1 KR 100242381 B1 KR100242381 B1 KR 100242381B1 KR 1019960075720 A KR1019960075720 A KR 1019960075720A KR 19960075720 A KR19960075720 A KR 19960075720A KR 100242381 B1 KR100242381 B1 KR 100242381B1
Authority
KR
South Korea
Prior art keywords
npn
conductive type
forming
region
pnp transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019960075720A
Other languages
Korean (ko)
Other versions
KR19980056450A (en
Inventor
주재일
Original Assignee
김영환
현대반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체주식회사 filed Critical 김영환
Priority to KR1019960075720A priority Critical patent/KR100242381B1/en
Publication of KR19980056450A publication Critical patent/KR19980056450A/en
Application granted granted Critical
Publication of KR100242381B1 publication Critical patent/KR100242381B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137Collector regions of BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177Base regions of bipolar transistors, e.g. BJTs or IGBTs

Landscapes

  • Bipolar Transistors (AREA)

Abstract

본 발명은 바이폴라 트랜지스터의 제조방법에 관한 것으로서 절연기판상의 단위 소자 영역 상에 각각 분리되어 형성된 단결정실리콘층을 형성하는 공정과, 상기 단결정실리콘층을 제1도전형 및 제2도전형의 불순물을 고농도로 주입하여 NPN 및 PNP 트랜지스터의 콜렉터영역을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터의 콜렉터영역에 제2도전형 및 제1도전형의 각각의 베이스영역을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터 각각의 베이스영역 상에 불순물이 도핑되지 않은 다결정실리콘층을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터의 각각의 베이스영역 상에 형성된 다결정실리콘층의 각각에 제1 및 제2도전형의 불순물을 선택적으로 이온 주입하여 각각의 에미터영역을 형성하는 공정을 구비한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor, comprising: forming a single crystal silicon layer formed separately on a unit device region on an insulating substrate; and forming impurities of the first conductive type and the second conductive type in the single crystal silicon layer. Forming a collector region of the NPN and PNP transistors by implanting the same, forming a base region of each of the second conductive type and the first conductive type in the collector region of the NPN and PNP transistors; Forming a non-doped polysilicon layer on each base region, and selectively selecting first and second conductive impurities on each of the polysilicon layers formed on each base region of the NPN and PNP transistors. Ion implantation to form respective emitter regions.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

제1도는 종래 기술에 따른 바이폴라 트랜지스터의 단면도.1 is a cross-sectional view of a bipolar transistor according to the prior art.

제2(a)도 내지 제2(l)도는 본 발명에 따른 바이폴라 트랜지스터의 제조 공정도.2 (a) to 2 (l) are manufacturing process diagrams of a bipolar transistor according to the present invention.

본 발명은 바이폴라 소자 제조공정에서 절연체의 다결정 실리콘 성장기법(SILICON-ON-INSULATOR: 이하 SOI라 칭함)을 이용한 초고주파용 소자 제조에 관한 것으로 특히, 초고속 초고집적 초고신뢰성 소자제조에 적합하도록한 SOI 폴리 에미터구조와 그에 따른 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of ultra-high frequency devices using polycrystalline silicon growth techniques of insulators (SILICON-ON-INSULATOR: SOI) in the bipolar device manufacturing process. It relates to an emitter structure and a manufacturing method accordingly.

일반적으로, 바이폴라 트랜지스터의 단면 구조는 첨부한 제1도에 도시되어 있는 바와 같이, P형 또는 N형의 실리콘기판 상에 구현되는데, 소자간의 격리를 위한 LOCOS 방식을 이용한 필드산화막이 형성되어야 하며, 베이스영역과 에미터영역을 형성하기 위해 다수의 포토레지스트 공정과 다수의 확산 공정을 수행하여야 한다.In general, the cross-sectional structure of a bipolar transistor is implemented on a P-type or N-type silicon substrate, as shown in FIG. 1, and a field oxide film using a LOCOS method for isolation between devices should be formed. A plurality of photoresist processes and a plurality of diffusion processes must be performed to form the base region and the emitter region.

그러므로, 종래의 바이폴라 트랜지스터는 제조 공정이 복잡하며 소자의 집적도를 향상시키기 어려운 문제점이 있었다. 또한, 소자간 완전 격리가 어려움으로 인해 래치업특성과 소자간 누설전류에 관한 문제가 발생되었다.Therefore, the conventional bipolar transistor has a problem in that the manufacturing process is complicated and it is difficult to improve the integration of the device. In addition, due to the difficulty of complete isolation between devices, problems related to latch-up characteristics and leakage current between devices have occurred.

따라서, 본 발명의 목적은 제조 공정이 간단하고 소자의 집적도를 향상시킬 수 있는 바이폴라 트랜지스터의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a bipolar transistor, in which the manufacturing process is simple and the degree of integration of the device can be improved.

본 발명의 다른 목적은 소자들을 완전격리하여 래치업 특성과 소자간 누설전류를 방지할 수 있는 바이폴라 트랜지스터의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a bipolar transistor that can completely isolate the devices to prevent the latch-up characteristics and leakage current between the devices.

상기 목적들을 달성하기 위한 본 발명에 따른 바이폴라 트랜지스터의 제조방법의 제조방법은 절연기판 상의 단위 소자 영역 상에 각각 분리되어 형성된 단결정실리콘층을 형성하는 공정과, 상기 단결정실리콘층을 제1도전형 및 제2도전형의 불순물을 고농도로 주입하여 NPN 및 PNP 트랜지스터의 콜렉터영역을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터의 콜렉터영역에 제2도전형 및 제1도전형의 각각의 베이스영역을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터 각각의 베이스영역 상에 불순물이 도핑되지 않은 다결정실리콘층을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터의 각각의 베이스영역 상에 형성된 다결정실리콘층의 각각에 제1 및 제2도전형의 불순물을 선택적으로 이온 주입하여 각각의 에미터영역을 형성하는 공정을 구비한다.A method of manufacturing a bipolar transistor according to the present invention for achieving the above objects is a step of forming a single crystal silicon layer formed separately on the unit element region on the insulating substrate, the single crystal silicon layer is first conductive type and Implanting impurities of the second conductive type at a high concentration to form collector regions of the NPN and PNP transistors, and forming base regions of the second conductive type and the first conductive type in the collector regions of the NPN and PNP transistors; Forming a non-doped polysilicon layer on each base region of the NPN and PNP transistors, and forming a first polysilicon layer on each base region of the NPN and PNP transistors. And selectively ion implanting impurities of the second conductivity type to form respective emitter regions.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2(a)도 내지 제2(l)도는 본 발명에 따른 바이폴라 트랜지스터의 제조 공정도이다.2 (a) to 2 (l) are manufacturing process diagrams of a bipolar transistor according to the present invention.

제2(a)도에 의하면 사파이어(α-Al2O3)로 이루어진 절연기판(1) 상에 단결정 에피택셜 성장방법으로 〈100〉방향을 갖는 N형의 단결정실리콘층(2)을 형성한다.Referring to FIG. 2 (a), an N-type single crystal silicon layer 2 having a <100> direction is formed on the insulating substrate 1 made of sapphire (α-Al 2 O 3 ) by a single crystal epitaxial growth method. .

제2(b)도를 참조하면, 단결정실리콘층(2) 상에 CVD 방법으로 산화막(3)을 증착하고, 이 산화막(3) 상에 감광막(4)을 도포한다. 그리고, 감광막(4)을 소정 패턴으로 노광 및 현상하여 산화막(3)을 노출시킨다. 그 다음, 감광막(4)을 마스크로 사용하여 산화막(3)의 노출된 부분을 식각하여 단결정실리콘층(2)을 노출시킨다.Referring to FIG. 2 (b), the oxide film 3 is deposited on the single crystal silicon layer 2 by the CVD method, and the photosensitive film 4 is coated on the oxide film 3. Then, the photosensitive film 4 is exposed and developed in a predetermined pattern to expose the oxide film 3. Then, the exposed portion of the oxide film 3 is etched using the photosensitive film 4 as a mask to expose the single crystal silicon layer 2.

제2(c)도를 참조하면, 감광막(4) 및 산화막(3)을 마스크로 사용하여 단결정실리콘층(2)을 패터닝하여 소자격리영역을 한정한다. 그리고, 감광막(4) 및 산화막(3)을 순차적으로 제거한다.Referring to FIG. 2 (c), the device isolation region is defined by patterning the single crystal silicon layer 2 using the photosensitive film 4 and the oxide film 3 as a mask. Then, the photosensitive film 4 and the oxide film 3 are sequentially removed.

제2(d)도 및 제2(e)도를 참조하면, 잔류하는 단결정실리콘층(2)을 P형 및 N형의 불순물을 고농도로 이온주입하여 콜렉터영역(7)(8)을 형성한다. 상기에서, 잔류하는 단결정실리콘층(2) 중 일부를 감광막(5)으로 덮은 상태에서 덮지 않아 노출된 것을 붕소 등의 P형 불순물을 고농도로 이온주입하여 PNP 트랜지스터의 콜렉터영역(7)을 형성한다. 그리고, 감광막(5)을 제거한 후 다시 PNP 트랜지스터의 콜렉터영역(7)을 감광막(5A)로 덮은 상태에서 노출된 단결정실리콘층(2)에 인(P) 등의 N형의 불순물을 고농도로 이온주입하여 NPN 트랜지스터의 콜렉터영역(8)을 형성한다.Referring to FIGS. 2 (d) and 2 (e), the remaining single crystal silicon layer 2 is ion-implanted with P-type and N-type impurities at high concentration to form collector regions 7 and 8. . In the above, a portion of the remaining single crystal silicon layer 2 is not covered while being covered with the photosensitive film 5, and ion-implanted P-type impurities such as boron at a high concentration to form the collector region 7 of the PNP transistor. . After the photosensitive film 5 is removed, an N-type impurity such as phosphorus (P) is ionized at a high concentration in the single crystal silicon layer 2 exposed while the collector region 7 of the PNP transistor is covered with the photosensitive film 5A. Injection is performed to form the collector region 8 of the NPN transistor.

제2(f)도를 참조하면, 상기 감광막(5A)를 제거한다. 그리고, 콜렉터영역(7)(8)을 포함하는 절연기판(1) 상에 CVD 방법으로 산화막(6)을 증착한다.Referring to FIG. 2 (f), the photosensitive film 5A is removed. Then, an oxide film 6 is deposited on the insulating substrate 1 including the collector regions 7 and 8 by the CVD method.

제2(g)도를 참조하면, 상기 산화막(6)을 포토리쏘그래피 방법으로 선택적으로 NPN 트랜지스터의 콜렉터영역(8)을 노출시킨다. 그리고, 산화막(6)을 마스크로 사용하여 콜렉터영역(8) 상에 에피택셜 성장하여 P형의 베이스영역(9)을 형성한다.Referring to FIG. 2 (g), the oxide film 6 is selectively exposed to the collector region 8 of the NPN transistor by a photolithography method. Then, by using the oxide film 6 as a mask, epitaxial growth is performed on the collector region 8 to form a P-type base region 9.

제2(h)도 및 제2(i)도를 참조하면, 전술한 구조의 전표면에 다시 CVD 방법으로 산화막(6A)을 증착한다. 그리고, 상기 산화막(6A)을 포토리쏘그래피 방법으로 선택적으로 PNP 트랜지스터의 콜렉터영역(7)을 노출시킨다. 그리고, 산화막(6A)을 마스크로 사용하여 콜렉터영역(7) 상에 에피택셜 성장하여 N형의 베이스영역(10)을 형성한다.Referring to FIGS. 2 (h) and 2 (i), the oxide film 6A is again deposited on the entire surface of the structure described above by the CVD method. Then, the oxide film 6A is selectively exposed to the collector region 7 of the PNP transistor by a photolithography method. Then, the oxide film 6A is used as a mask to epitaxially grow on the collector region 7 to form an N-type base region 10.

제2(j)도를 참조하면, 상기 산화막(6A)을 제거하여 NPN 트랜지스터의 베이스영역(9)을 노출시킨다. 그리고, NPN 트랜지스터 및 PNP 트랜지스터의 베이스영역(9)(10) 상의 각각에 불순물이 도핑되지 않은 다결정실리콘층(11)을 형성한다. 상기 다결정실리콘층(11)은 CVD 방법으로 베이스영역(9)(10) 뿐만 아니라 산화막(6A)을 덮도록 증착한 후 산화막(6A)가 노출되도록 에치 백하므로써 형성된다.Referring to FIG. 2 (j), the oxide film 6A is removed to expose the base region 9 of the NPN transistor. Then, the polysilicon layer 11 which is not doped with impurities is formed in each of the base regions 9 and 10 of the NPN transistor and the PNP transistor. The polysilicon layer 11 is formed by depositing to cover not only the base regions 9 and 10 but also the oxide film 6A by CVD, and then etching back to expose the oxide film 6A.

제2(k)도를 참조하면, 베이스영역(10) 상의 다결정실리콘층(11)에 보론 등의 불순물을 이온 주입하여 PNP 트랜지스터의 에미터영역(13)을 형성한다. 상기에서 에미터영역(13)은 NPN 트랜지스터 영역 상에 감광막(12)을 형성한 후 이온주입하여 형성한다. 이 때, PNP 트랜지스터가 완성된다.Referring to FIG. 2 (k), the emitter region 13 of the PNP transistor is formed by ion implanting impurities such as boron into the polysilicon layer 11 on the base region 10. The emitter region 13 is formed by ion implantation after forming the photosensitive film 12 on the NPN transistor region. At this time, the PNP transistor is completed.

제2(l)도를 참조하면, 상기 감광막(12)을 제거한다. 그리고, NPN 트랜지스터 영역을 제외한 PNP 트랜지스터 상에 감광막(12A)을 형성한다. 그리고, 감광막(12A)을 마스크로 사용하여 다결정실리콘(11)에 인(P) 등의 N형 불순물을 고농도로 이온 주입하여 NPN 트랜지스터의 에미터영역(14)을 형성한다. 이 때, NPN 트랜지스터가 완성된다.Referring to FIG. 2 (l), the photosensitive film 12 is removed. Then, the photosensitive film 12A is formed on the PNP transistor except the NPN transistor region. Then, by using the photosensitive film 12A as a mask, the polysilicon 11 is ion-implanted with N-type impurities such as phosphorus (P) at a high concentration to form the emitter region 14 of the NPN transistor. At this time, the NPN transistor is completed.

기존의 실리콘기판을 통한 POLY 에미터구조에 대해 본 발명의 SOI 다결정실리콘 에미터구조는 수직형 NPN 트랜지스터와 수직형 PNP 트랜지스터를 동일한 절연기판 상에 형성시킬 수 있으며, 선택적 에피택셜 증착공정으로 자기정합적(SELF-ALIGNED)구조로써 제조공정이 단순해지며, 또한 다결정 실리콘위 이온 주입을 통한 에미터 형성으로 얕은 접합(shallow junction)이 가능하여 구주파 특성을 갖는 소자 구현에 적합하다. 또한, 소자간 격리영역이 완전절연체인 사파이어로 구성됨으로써 초고집적, 초고신뢰성소자 구성이 가능하며, 래치업문제가 전혀 없음으로 초고신뢰성의 소자 구현이 가능하다.About the POLY Emitter Structure Through the Existing Silicon Substrate The SOI polysilicon emitter structure of the present invention can form a vertical NPN transistor and a vertical PNP transistor on the same insulating substrate, and is self-aligned by a selective epitaxial deposition process. The SELF-ALIGNED structure simplifies the manufacturing process and allows shallow junctions by emitter formation through ion implantation on polycrystalline silicon, making it suitable for devices with sequential wave characteristics. In addition, since the isolation region between devices is made of sapphire, which is a full insulator, ultra-high integration and ultra-reliability devices can be configured, and there is no latch-up problem, thereby realizing ultra-high reliability devices.

Claims (3)

절연기판상의 단위 소자 영역 상에 각각 분리되어 형성된 단결정실리콘층을 형성하는 공정과, 상기 단결정실리콘층을 제1도전형 및 제2도전형의 불순물을 고농도로 주입하여 NPN 및 PNP 트랜지스터의 콜렉터영역을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터의 콜렉터영역에 제2도전형 및 제1도전형의 각각의 베이스영역을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터 각각의 베이스영역 상에 불순물이 도핑되지 않은 다결정실리콘층을 형성하는 공정과, 상기 NPN 및 PNP 트랜지스터의 각각의 베이스영역 상에 형성된 다결정실리콘층의 각각에 제1 및 제2도전형의 불순물을 선택적으로 이온 주입하여 각각의 에미터영역을 형성하는 공정을 구비하는 반도체 소자 제조방법.Forming a single crystal silicon layer separately formed on the unit element region on the insulating substrate; and injecting the single crystal silicon layer at high concentration into impurities of the first conductive type and the second conductive type to collect the collector regions of the NPN and PNP transistors. A step of forming a base region of each of the second conductive type and the first conductive type in the collector regions of the NPN and PNP transistors, and an impurity doped on the base regions of the NPN and PNP transistors, respectively. Forming a polysilicon layer and selectively ion implanting impurities of a first and a second conductive type into each of the polysilicon layers formed on each base region of the NPN and PNP transistors to form respective emitter regions A semiconductor device manufacturing method comprising the step of performing. 제1항에 있어서, 상기 절연기판을 사파이어(α-Al2O3)로 형성하는 반도체 소자 제조방법.The method of claim 1, wherein the insulating substrate is formed of sapphire (α-Al 2 O 3 ). 제1항에 있어서, 상기 NPN 및 PNP 트랜지스터의 콜렉터영역 및 베이스영역을 선택적 에피택셜 성장방법으로 형성하는 반도체 소자 제조방법.The method of claim 1, wherein the collector region and the base region of the NPN and PNP transistors are formed by a selective epitaxial growth method.
KR1019960075720A 1996-12-28 1996-12-28 Manufacturing method of semiconductor device Expired - Lifetime KR100242381B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960075720A KR100242381B1 (en) 1996-12-28 1996-12-28 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960075720A KR100242381B1 (en) 1996-12-28 1996-12-28 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR19980056450A KR19980056450A (en) 1998-09-25
KR100242381B1 true KR100242381B1 (en) 2000-02-01

Family

ID=19492000

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960075720A Expired - Lifetime KR100242381B1 (en) 1996-12-28 1996-12-28 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR100242381B1 (en)

Also Published As

Publication number Publication date
KR19980056450A (en) 1998-09-25

Similar Documents

Publication Publication Date Title
EP0552671A2 (en) Isolation technique for silicon germanium devices
US5846867A (en) Method of producing Si-Ge base heterojunction bipolar device
US4997775A (en) Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor
JPH0744232B2 (en) Bi-CMOS device manufacturing method
JP3258123B2 (en) Semiconductor device
US4978630A (en) Fabrication method of bipolar transistor
US6362025B1 (en) Method of manufacturing a vertical-channel MOSFET
JPH025432A (en) Manufacturing method of semiconductor device
EP0118102B1 (en) Method for manufacturing a semiconductor device
JPH065706B2 (en) Method for manufacturing BiCMOS device
EP0045848A1 (en) Planar semiconductor integrated circuits including improved bipolar transistor structures and method of fabricating such circuits
KR100242381B1 (en) Manufacturing method of semiconductor device
KR100745858B1 (en) Semiconductor device manufacturing method
KR0140444B1 (en) Bipolar Device Manufacturing Method
KR0137568B1 (en) Method of making a bipolar transistor
KR100223921B1 (en) Method of manufacturing semiconductor device
KR100209765B1 (en) Bimos manufacturing method
KR100221621B1 (en) Semiconductor device and manufacturing method thereof
KR100259586B1 (en) Method for manufacturing semiconductor device
JP3257523B2 (en) Method for manufacturing semiconductor device
JPH1140573A (en) Method for manufacturing semiconductor device
KR100216510B1 (en) Method of forming a collector of a bipolar transistor using a trench
KR100275539B1 (en) Self-aligned dipole transistor device and manufacturing method thereof
KR940001257B1 (en) Method of making semiconductor device
JP3120441B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19961228

A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19970108

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 19961228

Comment text: Patent Application

PG1501 Laying open of application
E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19991029

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19991110

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19991111

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20021018

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20031017

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20041108

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20051021

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20061024

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20071018

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20081017

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20091016

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20101019

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20111024

Start annual number: 13

End annual number: 13

PR1001 Payment of annual fee

Payment date: 20121022

Start annual number: 14

End annual number: 14

FPAY Annual fee payment

Payment date: 20131017

Year of fee payment: 15

PR1001 Payment of annual fee

Payment date: 20131017

Start annual number: 15

End annual number: 15

FPAY Annual fee payment

Payment date: 20141020

Year of fee payment: 16

PR1001 Payment of annual fee

Payment date: 20141020

Start annual number: 16

End annual number: 16

FPAY Annual fee payment

Payment date: 20151019

Year of fee payment: 17

PR1001 Payment of annual fee

Payment date: 20151019

Start annual number: 17

End annual number: 17

EXPY Expiration of term
PC1801 Expiration of term