KR100240684B1 - IC protective circuit of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electrostatic discharge (ESD) protection circuit of a semiconductor device, and in particular, by coupling a well voltage to a pad to speed up the operation of a bipolar transistor, thereby increasing discharge capacity and protecting the same. It provides a base coupled coupled protection circuit that improves latch-up by isolating the p well of the circuit from the internal circuitry.

To this end, the present invention provides a first conductive type semiconductor substrate, six field oxide films positioned on the substrate surface, and first to fifth active regions sequentially contacted with the surface of the substrate between the field oxide films and sequentially formed in the substrate in a horizontal direction. A first section and a second section formed by diffusion of high concentrations of second conductivity type impurities into the active region, the capacitor located above the first active region, the second active region, the third active region, and the fifth active region. And a first conductivity type well shallowly formed under the five field oxide films including the fourth section, the pad portion electrically connected to the capacitor and the first section, the first to fourth active regions, and the first conductivity type. It is composed of a second conductivity type well surrounding the well and including a fourth section and located deep inside the first conductivity type substrate under the six field oxide layers.

Description

IC protective circuit of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electrostatic discharge (ESD) protection circuit of a semiconductor device, and in particular, by coupling a well voltage to a pad to speed up the operation of a bipolar transistor, thereby increasing discharge capacity and protecting the same. The present invention relates to a base coupled coupled protection circuit that improves latch-up by isolating a p well of a circuit from an internal circuit.

As semiconductor devices are highly integrated, impurity regions and wiring widths used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that the resistance of the impurity region and the wiring increases, thereby lowering the operation speed.

Therefore, when wiring of elements in the semiconductor device is made of a low resistance material such as aluminum alloy and tungsten or made of polycrystalline silicon such as a gate electrode, a silicide layer may be formed to reduce the resistance. When the silicide layer is formed on the gate electrode formed of polycrystalline silicon, the silicide layer is formed on the surface of the impurity region to reduce the resistance.

However, the input / output terminals of the semiconductor device are susceptible to breakdown by electrostatic discharge due to a drop in breakdown voltage due to a transient voltage or a thin gate oxide film. That is, if the drain region has a low resistance silicide layer, the applied voltage is not evenly distributed and is concentrated in the LDD (Lightly Doped Drain) region to destroy the semiconductor device. Therefore, an ESD protection transistor is formed to prevent electrostatic discharge destruction by evenly spreading the applied voltage by increasing the resistance of the impurity region used as the source and drain regions and the gate electrode formed of polycrystalline silicon in the input / output terminals.

1 is a cross-sectional view of an ESD protection circuit of a semiconductor device according to the prior art.

The field oxide film 2 is formed in a predetermined portion on a portion where the P-type semiconductor substrate 1 or the P-type well 1 is formed by LOCOS (Local Oxidation of Silicon) method or the like to form the active region of the device, A region (not shown) where a normal transistor of the circuit is to be formed and an ESD protection transistor connected to the pad part are formed. This ESD protection circuit connects the ESD charge to the first n + section 5 (drain or collector) through an aluminum wiring (not shown) on one side of the pad 3 and the second n + section 6 connected to ground. , Source or emitter). In this case, in order to prevent a high electric field from being formed at the edge of the n + / p well, a space of about 3 to 10 μm is secured between the drain contact and the edge of the junction 5, that is, the field oxide film 2. The heavily doped p + third section 7 serves as a base, and the second section 6 and the third section 7 are connected to ground again by a conductor. The other side of the pad 3 is an internal circuit 8 Is electrically connected).

2 is a circuit diagram of an ESD protection circuit of a semiconductor device according to the prior art.

The circuit according to the prior art has an npn type bipolar transistor, which has a collector 25, an emitter 26, and a base 27 when the high voltage applied from the pad portion 23 has a positive charge. Base 27 meets and grounds emitter 26 through a p well resistance.

The operation of the ESD protection circuit is as follows.

First, when a negative isdy charge is applied to the pad 3, the n + / p well diode connected to the pad 3 is forward biased and a bias is applied to the p well. The condition is that the voltage at the pad n + (emitter) is V _ESD (V _ESD <0), the voltage at the p well (base) is the sum of V _ESD and 0.7 volts, and V _{SS at} n + (collector) 0 V is therefore (because npn bipolar base and the already voltage difference between the emitter of the transistors is 0.7 volts and the collector and because the same as already voltage difference between the emitter is V _ESD) bipolar transistor operates in an active mode and a yieseu di occupy V _SS stage To discharge.

In addition, when a positive YS charge is applied to the pad 24, the n + / p well diode connected to the pad 24 is reverse biased, and the reverse bias is increased to generate a breakdown voltage in the n + / p well diode. . This breakdown voltage causes a bias to be applied to the p well. The bias condition is that the voltage at the pad n + (collector) is V _ESD (V _ESD > 0), the voltage at the p well (base) is greater than 0.7 volts, and the voltage at the V _SS stage n + (emitter) is 0 volts. since the bipolar transistor (because the voltage difference between the base and emitter of npn bipolar transistor is greater than 0.7 volts collector and already voltage difference between the emitter is due to the same as the V _ESD) is a yieseu di charge while operating in the active mode or the saturation mode V _SS It discharges in stage.

As described above, in the ESD protection circuit of the conventional semiconductor device, if the ESD voltage of the positive voltage is applied, the ESD protection circuit starts the operation due to the breakdown voltage of the n + / p well function, and thus the destruction of the n + / p well function. If a phenomenon occurs easily and + /-surge voltage is applied to the input terminal after V _CC / V _SS is applied to each other, the sudden current caused by npn bipolar transistor operation raises / lowers the voltage of p well / n well and latches it. There is a problem that is easy to cause a catch-up phenomenon.

Accordingly, an object of the present invention relates to a method of manufacturing an electrostatic discharge (ESD) protection circuit of a semiconductor device, which increases the discharge capacity by coupling a well voltage to a pad to speed up the operation of the bipolar transistor. The present invention provides a method of manufacturing a base coupled coupled ESD protection circuit which improves a latch-up phenomenon by isolating a p well of a protection circuit from an internal circuit.

The DS protection circuit of the semiconductor device according to the present invention for achieving the above objects is in contact with the substrate surface between the first conductivity type semiconductor substrate, the six field oxide film located on the surface of the substrate, and the field oxide film and horizontally inside the substrate. A second conductivity type having a high concentration in the first to fifth active regions sequentially formed in the direction, a capacitor located above the first active region, the second active region, the third active region and the fifth active region Impurities diffused under the five field oxide films including a first section, a second section, and a fourth section, pad portions electrically connected to the capacitor and the first section, and first to fourth active regions. A shallowly formed first conductivity type well and a first conductivity type well surrounding the first conductivity type well and including a fourth section deep inside the first conductivity type substrate under the six field oxide films. Groping second conductivity type wells is made.

1 is a cross-sectional view of an ESD protection circuit of a semiconductor device according to the prior art.

2 is a circuit diagram of an ESD protection circuit of a semiconductor device according to the prior art.

3 is a cross-sectional view of an ESD protection circuit of a semiconductor device according to the present invention.

4 is a circuit diagram of an ESD protection circuit of a semiconductor device according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of an ESD protection circuit of a semiconductor device according to the present invention.

Six field oxide films 33 are formed on the surface of the first conductivity type silicon substrate 30 on which the plurality of field oxide films 33 are formed. Between the field oxide films 33, first to fifth active regions are sequentially formed. A capacitor 38 is formed on the first active region. In the second active region, the third active region, and the fifth active region, a high concentration of second conductive impurities are diffused to form a first section 34, a second section 35, and a fourth section 37, respectively. In the fourth active region, a third cushion 36 in which a high concentration of the first conductivity type impurity is diffused is positioned. In addition, the capacitor 38 and the first section 34 are electrically connected to each other, and the pad unit 300 is electrically connected to the first section 34, and the first section 34 is electrically connected to the internal circuit 301.

The first conductivity type well 32 is shallowly formed under the five field oxide films 33 including the first to fourth active regions under the capacitor 38, and then the first conductivity type well 32 is formed. ) And a second conductivity type well 31 including a fourth cushion 37 is deeply located inside the first conductivity type substrate 30 below the six field oxide layers 33.

In this case, the first conductivity type is a p-type impurity and the second conductivity type is an n-type impurity to form a bipolar transistor comprising a first section 34, a second section 35, and a third section 36 to form a pad. Discharges the applied ESD charge, and the fourth section and the second conductivity type well 31 make an ohmic contact to linearly convert the applied ESD charge. Again, the deeply formed second conductive well 31 isolates the shallowly formed first conductive well 32 from the bulk, reduces the parasitic capacitance in the first conductive well 32 and latch-down. Even during latch-up, it acts to trap electrons generated in the first section 34 connected to the pad to block the influence on the internal circuit.

In addition, the capacitor 38 temporarily increases the base voltage to speed up the operation of the transistor, and AC-couples the pad with the first conductivity type well 32.

4 is a circuit diagram of an ESD protection circuit of a semiconductor device according to the present invention.

This circuit has an npn type bipolar transistor, which has a collector 34, an emitter 35, and a base 36 when the high voltage applied from the pad portion 300 has a positive charge. One side of the base 27 is connected to the collector 34 via the capacitor 38 and the connection node is connected to the internal circuit 301 again, and the other side is connected to the emitter 35 through the p well resistance. Be grounded.

The operation of the ESD protection circuit completed as described above is the same as the conventional ESD protection circuit when the negative charge is applied to the pad. However, when the positive ESD charge is applied to the pad part, the capacitance between the pad and the p well depends on the capacitance. Since the bias of the p well rises and the n + / p well diode connected to the pad is reverse biased, the bipolar transistor operates in active or saturation mode and discharges its charge to the V _SS stage. The bias condition when applying the charge charge is the voltage of the emitter, which is the second n + region located at the V _SS stage when the voltage of the first n + section, that is, the collector voltage is V _ESD (> 0), and the voltage of the base p well is greater than 0.7 volts. Is zero because the voltage between the base and the emitter of the npn type transistor is greater than 0.7 volts and the voltage between the collector and the emitter is equal to the Isdye voltage.

Therefore, in the present invention, when the ESD charge is applied to the pad, the voltage of the p well rises and the npn transistor is operated, so that the operation speed of the ESD protection circuit is increased, so that the discharge capacity of the circuit is improved and the voltage change of the p well is ESD protected. By triggering the circuit operation, it is possible to prevent the performance degradation of the ESD protection circuit due to local operation of the protection circuit, which is likely to occur in the process of triggered by the breakdown voltage in the n + / p well, that is, rapid breakdown of the part of the section due to process failure. Can be.

Claims (3)

A first conductivity type semiconductor substrate, Six field oxide films positioned on the substrate surface; First to fifth active regions contacting the substrate surface between the field oxide layers and sequentially formed in the substrate in a horizontal direction; A capacitor positioned above the first active region; A first section, a second section, and a fourth section formed by diffusing a high concentration of a second conductivity type impurity in the second active region, the third active region, and the fifth active region; A pad part electrically connected to the capacitor and the first cushion; A first conductivity type well formed below the five field oxide layers including the first to fourth active regions; An ESD protection circuit of a semiconductor device including a second conductive well surrounding the first conductive well and simultaneously including the fourth section and deeply located inside the first conductive substrate under the six field oxide layers. The ESD protection circuit of claim 1, wherein the capacitor and the first section are electrically connected to each other so as to be electrically connected to the pad unit, and the first section is electrically connected to an internal circuit. The semiconductor device of claim 1, wherein the first conductivity type is formed of p-type impurity and the second conductivity type is formed of n-type impurity.

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