KR100236049B1 - Bipolar Transistors and Manufacturing Method Thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor suitable for simplifying a process and improving device characteristics, and a method for manufacturing the same, wherein ion implantation is performed to form a collector region in a substrate, followed by ion implantation for forming a first impurity region. Forming a first electrode having an insulating layer thereon on the first impurity region, forming a sidewall spacer on both sides of the first electrode, and contacting the first impurity region. And forming a second impurity region and a third impurity region by diffusing impurities from the first electrode and the second electrode through heat treatment, respectively, on the entire surface including the substrate.

Description

Bipolar Transistors and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and in particular, to bipolar transistors suitable for simplifying the process and improving the characteristics of the device and a method of manufacturing the same.

Hereinafter, a bipolar transistor according to the prior art will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional bipolar transistor.

First, as shown in FIG. 1A, a first insulating layer 13 for patterning a base region is formed on a substrate 11.

As shown in FIG. 1B, a photoresist (not shown) is coated on the first insulating layer 13, and then patterned by an exposure and development process, followed by an etching process using the patterned photoresist as a mask. The insulating layer 13 is selectively removed to define a base region.

Subsequently, after the impurity ion implantation is performed to form the base region, the base region 15 is formed by a diffusion process using heat treatment.

Next, as illustrated in FIG. 1C, a second insulating layer 17 is formed on the entire surface of the substrate 11 including the first insulating layer 13 to define an emitter region.

Thereafter, a predetermined portion of the second insulating layer 17 on the base region 15 is removed to form an emitter region in the base region 15.

At this time, the second insulating layer 17 is removed using a photo process.

Subsequently, impurity ion implantation is performed using the second insulating layer 17 as a mask, and a predetermined emitter region 19 is formed in the base region 15 through heat treatment.

Here, the base region 15 and the emitter region 19 are of the same conductivity type and opposite to the substrate 11.

Subsequently, as shown in FIG. 1D, a predetermined portion of the second insulating layer 17 on both sides of the emitter region 19 is removed to form a base contact, and after the polysilicon 21 is deposited on the entire surface, it is selectively removed. The bipolar transistor manufacturing process according to the prior art is completed.

However, the conventional bipolar transistor manufacturing method as described above has a problem in that the process becomes complicated because a large number of masks are required due to several photo processes.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a bipolar transistor and a method for manufacturing the same, which are simple to minimize the photo process, and to easily control the base region having an important influence on the characteristics of the device. The purpose is.

1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional bipolar transistor.

2 is a structural cross-sectional view of a bipolar transistor according to the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a bipolar transistor of the present invention.

Explanation of symbols for main parts of the drawings

11, 31: substrate 33: polysilicon layer

33a: first electrode 33b: second impurity region

35 insulation layer 37 sidewall spacer

39: second electrode 39a: third impurity region

41: first impurity region 43: collector region

A bipolar transistor of the present invention for achieving the above object comprises a substrate, a first impurity region formed in the surface of the substrate, a first electrode formed on the first impurity region having an insulating layer thereon, and the first A second impurity region formed in the substrate under the electrode, a second electrode formed in contact with the first impurity region in isolation from the first electrode, and a second impurity formed in a portion in contact with the second electrode in the first impurity region. The method for manufacturing a bipolar transistor according to an embodiment of the present invention includes a third impurity region, and includes a step of sequentially performing ion implantation to form a collector region in a substrate, followed by ion implantation to form a first impurity region; Forming a first electrode having an insulating layer over the impurity region, and forming sidewall spacers on both sides of the first electrode; Forming a second electrode on the entire surface including the substrate so as to be in contact with the first impurity region, and diffusing impurities from the first electrode and the second electrode through heat treatment, respectively; It includes a step of forming a region.

Hereinafter, a bipolar transistor and a method of manufacturing the same will be described with reference to the accompanying drawings.

2 is a cross-sectional view of a structure of a bipolar transistor according to the present invention, and FIGS. 3A to 3E are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to the present invention.

First, as shown in FIG. 2, the bipolar transistor of the present invention includes a substrate 31, a first impurity region 41 formed to a predetermined depth of the substrate 31, and an insulating layer 35 on the substrate. The first electrode 33a formed in a predetermined portion on the first impurity region 41, the second impurity region 33b formed in the substrate 31 under the first electrode 33a, and the first electrode 33a. The third impurity region 39a formed in the sidewall spacer 37 formed on both sides, the second electrode 39 formed on the front surface including the substrate 31, and the substrate 31 in contact with the second electrode 39. It is configured to include).

Here, the first impurity region 41 and the second impurity region 33b are of the same conductivity type, and the first and second impurity regions 41 and 33b and the third impurity region 39a are different from each other. to be.

The first electrode 33a is used as an emitter electrode, and the second electrode 39 is used as a base electrode.

The second impurity region 33b is used as an emitter region and the third impurity region 39a is used as a base region.

In the substrate 31 under the base region, the collector region 43 is formed by implanting impurity ions using high energy.

Referring to the bipolar transistor manufacturing method of the present invention configured as described above are as follows.

As shown in FIG. 3A, impurities of the same conductivity type as those of the substrate 31 are implanted with high energy so as to control the resistance and junction capacitance of the collector region in the substrate 31.

Subsequently, in order to form the first impurity region in the surface of the substrate 31, ion implantation impurities of the opposite conductivity type to the substrate 31 are implanted.

Subsequently, as illustrated in FIG. 3B, a polysilicon layer 33 doped with impurities is formed on the substrate 31.

Here, the impurities contained in the polysilicon layer 33 are later diffused into the substrate 31 through heat treatment to form a second impurity region (emitter region).

Next, an insulating layer 35 is formed on the polysilicon layer 33.

3C, the polysilicon layer 33 is selectively removed together with the insulating layer 35 to form the emitter electrode 33a.

In this case, the process of forming the emitter electrode 33a may be performed by applying a photoresist (not shown) on the insulating layer 35 and then patterning the photoresist in an exposure and development process. Using an etched photoresist as a mask to selectively remove the insulating layer 35 and the polysilicon layer 33 or patterning the photoresist on the insulating layer 35 Patterning the insulating layer 35 by an etching process using a patterned photoresist as a mask, and removing the polysilicon layer 33 by using the patterned insulating layer 35 as a mask may be used. .

As such, after forming the emitter electrode 33a having the insulating layer 35 on the upper side, the insulating layer is formed on the entire surface including the substrate 31 and then etched back to emitter electrode including the insulating layer 35 ( 33a) Sidewall spacers 37 are formed on both sides.

At this time, the sidewall spacer 37 serves to electrically isolate the emitter electrode 33a from the base electrode to be formed later.

Subsequently, as shown in FIG. 3D, the base electrode 39 is formed on the entire surface of the substrate 31 including the sidewall spacers 37.

At this time, the base electrode 39 has an opposite conductivity type to impurities contained in the polysilicon layer 33.

When the heat treatment process is performed as shown in FIG. 3E, impurities are diffused into the substrate 31 in contact with the emitter electrode 33a and the base electrode 39, respectively, so that the second impurity region 33b and the third impurity are respectively. Region 39a is formed.

In addition, impurities implanted into the surface of the substrate 31 to form the base region are also diffused to form the first impurity region 41.

In this case, the second impurity region 33b is an emitter region and the third impurity region 39a is a base region.

The second impurity region 33b and the third impurity region 39a exist in the first impurity region 41.

Here, reference numeral 43 is a collector region 43 formed by diffusion of impurities implanted in FIG. 3A through heat treatment.

As described above, the bipolar transistor of the present invention and the manufacturing method thereof have the following effects.

First, since the photo process for forming the base region is not necessary, the number of masks is reduced accordingly.

Second, since the profile forming the base region is determined by ion implantation rather than by diffusion, it is possible to easily control the base region which has an important influence on the characteristics of the device.

Claims (10)

Substrate, A first impurity region formed in the surface of the substrate, A first electrode having an insulating layer thereon and formed on the first impurity region; A second impurity region formed in the substrate under the first electrode; A second electrode which is isolated from the first electrode and formed to contact the first impurity region; And a third impurity region formed in a portion of the first impurity region in contact with the second electrode. The method of claim 1, And wherein the first electrode is an emitter electrode and the second electrode is a base electrode. The method of claim 1, And wherein the second impurity region is an emitter region and the third impurity region is a base region. The method of claim 1, And the second electrode is isolated from the first electrode by a sidewall spacer formed on a side of the first electrode. The method of claim 1, And a collector region in the substrate. Performing ion implantation to form a collector region in the substrate and then ion implantation to form a first impurity region; Forming a first electrode having an insulating layer thereon on the first impurity region; Forming sidewall spacers on both side surfaces of the first electrode; Forming a second electrode on the entire surface including the substrate to be in contact with the first impurity region; And forming a second impurity region and a third impurity region by diffusing impurities from the first electrode and the second electrode through heat treatment, respectively. The method of claim 6, And the first electrode and the second electrode are electrically isolated by the sidewall spacers. The method of claim 6, And wherein the third impurity region is of an opposite conductivity type to the first and second impurity regions. The method of claim 6, And wherein the second impurity region is an emitter region and the third impurity region is used as a base region. The method of claim 6, And the first electrode and the second electrode are made of polysilicon doped with impurities of different conductivity types, respectively.

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