KR100234697B1 - Mask ROM Manufacturing Method - Google Patents
Mask ROM Manufacturing Method Download PDFInfo
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- KR100234697B1 KR100234697B1 KR1019960052280A KR19960052280A KR100234697B1 KR 100234697 B1 KR100234697 B1 KR 100234697B1 KR 1019960052280 A KR1019960052280 A KR 1019960052280A KR 19960052280 A KR19960052280 A KR 19960052280A KR 100234697 B1 KR100234697 B1 KR 100234697B1
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- forming
- trench
- depositing
- bit line
- metal
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- Semiconductor Memories (AREA)
Abstract
본 발명은 마스크 롬 제조방법에 관한 것으로, 종래의 데이터 코딩은 게이트형성후에 이루어지는게 이는 TAT가 증가되고, 또한 TAT를 줄이기 위해 메탈 후에 데이터 코딩을 행하게 되면 비트라인 메탈이 액티브 영역을 침범하게 되고 이를 막기 위해서는 셀의 사이즈가 증가되는 문제가 있었다. 이에 본 발명은 기판에 안정화 산화막 침 질화막을 증착한 후 식각하여 기판 내에 트랜치를 형성하는 공정과, 상기 트랜치 내에필드 이온 주입을 하여 필드 확산 영역을 형성하고 공정과, 상기 트랜치 내에 살리사이드를 형성하는 공정과, 상기 질화막을 제거하고 셀 영역에 디플리션 이온주입 및 주변회로의 문턱전압 조절을 위한 이온주입을 하는 공정과, 상기 안정화 산화막을 제거하고 게이트 산화막을 증착한 다음 폴리실리콘 게이트를 형성하는 공정과, 소스 및 드레인을 형성하고 상기 폴리실리콘 게이트 위에 중간절 연막을 형성하는 공정과, 데이터 코딩을 실시하는 공정과, 컨택영역을 형성하고 메탈을 증착한 다음 패시베이션을 증착하고 패드를 형성하는 공정을 제공하는데, 이러한 본 발명은 트랜치 구조를 히용하여 비트라인 메탈을 형성함으로써 비트라인 메탈이 액티브 영역을 침범하여 발생하는 셀 사이즈 증가를 억제할 수 있고 이는 또한 셀간을 격리(isolation)할 수 있는 효과가 있다.The present invention relates to a method for manufacturing a mask ROM, in which conventional data coding is performed after gate formation, which increases TAT, and when data coding is performed after metal to reduce TAT, bit line metal invades the active region. There was a problem that the size of the cell is increased to prevent it. Accordingly, the present invention provides a process of depositing a stabilizing oxide nitriding film on a substrate and then etching to form a trench in the substrate, forming a field diffusion region by performing field ion implantation into the trench, and forming a salicide in the trench. And removing the nitride film and implanting ion into the cell region to control depletion ion and threshold voltage of the peripheral circuit; and removing the stabilized oxide film and depositing a gate oxide film to form a polysilicon gate. Forming a source and a drain, forming an intermediate insulation film on the polysilicon gate, performing a data coding process, forming a contact region, depositing a metal, depositing a passivation, and forming a pad The present invention utilizes a trench structure to form a bit line metal As a result, the increase in the cell size caused by the bit line metal invading the active region can be suppressed, which can also isolate the cells.
Description
본 발명은 마스크 롬 제조방법에 관한 것으로, 특히 트랜치 구조를 이용하여 비트 라인메탈을 형성함으로써 비트라인 메탈이 액티브 영역을 침범하여 발생하는 셀 사이즈 증가를 억제하고 격리(isolation)의 기능 또한 가질 수 있도록 한 마스크 롬 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a mask rom, and in particular, by forming a bit line metal using a trench structure so as to suppress the increase in the cell size caused by the intrusion of the bit line metal and to have an isolation function. It relates to a method for producing a mask rom.
종래의 마스크 롬 제조 기술에 대해 도1를 참조하여 설명하면 다음과 같다.Referring to FIG. 1, a conventional mask ROM manufacturing technique is as follows.
종래 낸드 셀(NAND CELL)에서 비트라인 메탈(3) 형성 후에 코딩(Coding)을 하기 위해서는 비트라인 메탈(3)이 액티브 영역(2)을 침범해서는 안되는데, 이는 트랜지스터가 형성되는 액티브 영역(2)에 비트라인 메탈(3)이 걸쳐있게 되면 이온주입 공정으로 데이터를 코딩해야 하므로 메탈이 존재하는 부위와 존재하지 않는 부위의 이온주입 되는 깊이가 달라지기 때문이다.In order to perform coding after forming the bit line metal 3 in the NAND cell, the bit line metal 3 should not invade the active region 2, which is an active region 2 in which a transistor is formed. If the bit line metal (3) is in contact with the data to be coded by the ion implantation process because the ion implantation depth of the portion where the metal is present and the non-existing portion is different.
따라서, 상기 설명한 비트라인 메탈(3)의 액티브 영역(2) 침범을 막고 비트라인 메탈(3)이 액티브 영역(3) 간의 오정렬(misalign)을 고려하여 존재하도록 하기 위하여 액티브 영역(2)간의 간격을 확장시켜 셀을 형성하였다.Therefore, the gap between the active regions 2 is prevented to invade the active region 2 of the bit line metal 3 described above, and to allow the bit line metal 3 to exist in consideration of misalignment between the active regions 3. Was expanded to form a cell.
그러나, 상기와 같이 액티브 영역 간의 간격을 확장시켜야 하므로 셀의 사이즈가 증가하여 메모리 용량이 큰 경우에는 칩 사이즈가 커지게 되는 문제가 발생한다.However, since the spacing between the active regions needs to be extended as described above, a problem arises in that the chip size increases when the cell size increases and the memory capacity is large.
본 발명은 상기와 같은 종래의 문제를 해결하기 위하여 창안된 것으로, 트랜치 구조를 이용하여 비트라인 메탈을 형성함으로써 비트라인 메탈이 액티브 영역을 침범하여 발생하는 셀 사이즈 증가를 억제하고 격리(isolation)의 기능 또한 가질 수 있도록 한 마스크 롬 제조방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention was devised to solve the above-mentioned conventional problem, and by forming a bitline metal using a trench structure, it is possible to suppress an increase in cell size caused by bitline metal invasion of an active region and to reduce isolation. It is an object of the present invention to provide a method for manufacturing a mask rom that also has a function.
제1도은 종래 기술에 의한 마스크 롬의 평면도.1 is a plan view of a mask ROM according to the prior art.
제2도는 본 발명에 의한 마스크 롬의 평면도.2 is a plan view of a mask ROM according to the present invention.
제3(a)도 내지 (f)는 본 발명 마스크 롬의 제조를 나타낸 공정수순도.3 (a) to (f) are process flowcharts showing the production of the mask ROM of the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
11 : 기판 12 : 안정화 산화막11 substrate 12 stabilized oxide film
13 : 질화막 14 : 트랜치13: nitride film 14: trench
15 : 필드 확산영역 16 : 살리사이드15: field diffusion area 16: salicide
17 : 게이트 산화막 18 : 게이트17 gate oxide film 18 gate
19 : CVD 산화막 20 : 붕소인유리(BPSG)19: CVD oxide film 20: boron phosphorus glass (BPSG)
21 : 포토레지스트 22 : 필드영역21: photoresist 22: field area
23 : 액티브 영역 24 : 컨택영역23: active area 24: contact area
상기와 같은 목적을 달성하기 위한 본 발명 마스크 롬 제조방법은, 기판에 안정화 산화막 및 질화막을 증착한 후 식각하여 기판내에 트랜치를 형성하는 공정과, 상기 트랜치 내에 필드 이온 주입을 하여 필드 확산 영역을 형성하는 공정과, 상기 트랜치 내에 살리사이드를 형성하는 공정과, 상기 질화막을 제거하고 셀 영역에 디플리션 이온주입 및 주변회로의 문턱전압 조절을 위한 이온주입을 하는 공정과, 상기 안정화 산화막을 제거하고 게이트 산화막을 증착한 다음 폴리실리콘 게이트를 형성하는 공정과, 소스 및 드레인을 형성하고 상기 폴리실리콘 게이트 위에 중간절 연막을 형성하는 공정과, 데이터 코딩을 실시하는 공정과, 컨택영역을 형성하고 메탈을 증착한 다음 패시베이션을 증착하고 패드를 형성하는 공정으로 이루어진다.In order to achieve the above object, the present invention provides a method for manufacturing a mask ROM, forming a trench in a substrate by depositing a stabilized oxide film and a nitride film on a substrate and etching the same, and forming a field diffusion region by implanting field ions in the trench. Forming a salicide in the trench, removing the nitride film, implanting a ion into a cell region for depletion ion implantation and controlling a threshold voltage of a peripheral circuit, and removing the stabilizing oxide film. Depositing a gate oxide film and then forming a polysilicon gate; forming a source and a drain; forming an intermediate insulation film on the polysilicon gate; performing data coding; forming a contact region and forming a metal Deposition followed by deposition of the passivation and pad formation.
이와같은 본 발명 마스크 롬 제조방법에 대해 도2 및 도3를 참조하여 좀 더 상세히 설명하면 다음과 같다.Such a method of manufacturing the mask ROM of the present invention will be described in more detail with reference to FIGS. 2 and 3 as follows.
본 발명은, 게이트 형성후에 데이타 코딩을 수행함에 따라 발생하는 셀 사이즈 증가 문제를 해결하기 위하여 데이터 코딩을 메탈 형성후에 하도록 함으로써 TAT를 줄이고 셀 사이즈 증가를 막기 위한 것으로, 이의 제조방법을 설명한다.The present invention provides a method for reducing TAT and preventing cell size increase by performing data coding after metal formation in order to solve a problem of cell size increase caused by data coding after gate formation.
먼저, 도3a에 도시한 바와 같이 실리콘 기판(11)에 안정화 산화막(reliefoxide)(12) 및 질화막(13)을 증착한 다음 식각하여 실리콘 기판(11) 내에 트랜치(14)를 설명한다.First, as illustrated in FIG. 3A, a trench 14 is deposited in the silicon substrate 11 by depositing a stabilized oxide 12 and a nitride film 13 on the silicon substrate 11 and then etching.
이후, 도3b에 도시한 바와 같이 상기 트랜치(14) 내에 필드 이온 주입으로 붕소(Boron)를 주입하여 필드 확산영역(15)을 형성하는데 이때 트랜치(14)의 벽면에 고루 붕소(Boron)이 주입될 수 있도록 붕소(Boron)를 틸트(tilt)시켜 주입시킴과 동시에 웨이퍼를 회전(rotation)시킨다.Thereafter, as shown in FIG. 3B, boron is implanted into the trench 14 by field ion implantation to form a field diffusion region 15. In this case, boron is uniformly injected into the wall of the trench 14. Boron is tilted and implanted to rotate the wafer at the same time.
다음, 도3c에 도신한 바와 같이 상기 트랜치(14) 내에 살리사이드(Self align silicide)(16)를 형성하는데 이것이 셀내의 비트라인이 된다. 이때, 상기 살리사이드(16)는 비트라인의 저항을 줄이기 위하여 선택된 것이다.Next, as shown in FIG. 3C, a self align silicide 16 is formed in the trench 14, which becomes a bit line in the cell. At this time, the salicide 16 is selected to reduce the resistance of the bit line.
이어서, 도3d에 도시한 바와 같이 상기 질화막(13)을 제거하고 셀 영역에 디플리션(depletion) 이온주입을 하고 주변회로의 문턱전압(threshold voltage) 조절을 위한 이온주입을 한다.Subsequently, as illustrated in FIG. 3D, the nitride layer 13 is removed, depletion ion implantation is performed in the cell region, and ion implantation is performed to adjust the threshold voltage of the peripheral circuit.
그런 다음, 도3e에 도시한 바와 같이 상기 안정화 산화막(12)을 제거하고 게이트 산화막(17)을 증착한 다음, 폴리실리콘 게이트(18)를 형성하고 소스/드레인을 형성한다.Then, as shown in FIG. 3E, the stabilization oxide film 12 is removed and the gate oxide film 17 is deposited. Then, a polysilicon gate 18 is formed and a source / drain is formed.
그리고, 상기 폴리실리콘 게이트(18) 위에 증간절연막을 형성하는데, 이때 형성되는 층간절연막은 CVD 산화막(19)과 붕소인유리(BPSG. 20)이다.Further, an interlayer insulating film is formed on the polysilicon gate 18, wherein the interlayer insulating film is formed of CVD oxide film 19 and boron phosphorus glass (BPSG. 20).
이후, 도3f에 도시한 바와 같이 포토레지스트(21)를 이용하여 코드 이온주입을 하여 증가형 셀(enhancement cell)을 형성하는 데이터 코딩(coding) 작업을 한다.Thereafter, as shown in FIG. 3F, a data coding operation is performed to form an enhancement cell by performing code ion implantation using the photoresist 21.
마지막으로, 컨택영역을 형성하여 메탈을 증착하고 패시베이션을 증착한 다음 패드를 형성함으로써 공정이 완료된다.Finally, the process is completed by forming contact areas to deposit metal, passivation and then forming pads.
이와같이 셀영역의 비트라인 메탈로 살리사이트(16)를 트랜치(14)에 메몰(buried)된 구조로 형성하였는데, 이로써 비트라인 메탈이 액티브 영역(23)을 침범하는 것을 방지할 수 있게 되어 셀 사이즈 증가를 억제할 수 있고 이는 또한 셀간의 격리(isolation)용으로도 사용 가능하다.In this way, the salicide 16 is buried in the trench 14 with the bit line metal of the cell region, thereby preventing the bit line metal from invading the active region 23. The increase can be suppressed and can also be used for isolation between cells.
도2는 본 발명에 의해 구현된 낸드 셀의 구조를 도시한다.2 illustrates the structure of a NAND cell implemented by the present invention.
상술한 바와 같이, 본 발명은 트랜치 구조를 이용하여 비트라인 메탈을 형성함으로써 비트라인 메탈이 액티브 영역을 침범하여 발생하는 셀 사이즈 증가를 억제할 수 있고 이는 또한 셀간을 격리(isolation)할 수 있는 효과가 있다.As described above, the present invention can suppress the increase in cell size caused by the bit line metal invading the active region by forming the bit line metal using the trench structure, which also can isolate the cells (isolation) There is.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960052280A KR100234697B1 (en) | 1996-11-06 | 1996-11-06 | Mask ROM Manufacturing Method |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960052280A KR100234697B1 (en) | 1996-11-06 | 1996-11-06 | Mask ROM Manufacturing Method |
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| KR19980034277A KR19980034277A (en) | 1998-08-05 |
| KR100234697B1 true KR100234697B1 (en) | 1999-12-15 |
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| JP3180951B2 (en) * | 1998-05-26 | 2001-07-03 | 日本電気株式会社 | Semiconductor storage device and method of manufacturing the same |
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